2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_fourcc.h>
36 #include <drm/drm_rect.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_plane_helper.h>
39 #include "intel_drv.h"
40 #include "intel_frontbuffer.h"
41 #include <drm/i915_drm.h>
43 #include <drm/drm_color_mgmt.h>
45 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
49 if (!adjusted_mode->crtc_htotal)
52 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
53 1000 * adjusted_mode->crtc_htotal);
56 /* FIXME: We should instead only take spinlocks once for the entire update
57 * instead of once per mmio. */
58 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
59 #define VBLANK_EVASION_TIME_US 250
61 #define VBLANK_EVASION_TIME_US 100
65 * intel_pipe_update_start() - start update of a set of display registers
66 * @new_crtc_state: the new crtc state
68 * Mark the start of an update to pipe registers that should be updated
69 * atomically regarding vblank. If the next vblank will happens within
70 * the next 100 us, this function waits until the vblank passes.
72 * After a successful call to this function, interrupts will be disabled
73 * until a subsequent call to intel_pipe_update_end(). That is done to
74 * avoid random delays.
76 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
78 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
79 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
80 const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
81 long timeout = msecs_to_jiffies_timeout(1);
82 int scanline, min, max, vblank_start;
83 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
84 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
85 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
89 vblank_start = adjusted_mode->crtc_vblank_start;
90 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
91 vblank_start = DIV_ROUND_UP(vblank_start, 2);
93 /* FIXME needs to be calibrated sensibly */
94 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
95 VBLANK_EVASION_TIME_US);
96 max = vblank_start - 1;
98 if (min <= 0 || max <= 0)
101 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
105 * Wait for psr to idle out after enabling the VBL interrupts
106 * VBL interrupts will start the PSR exit and prevent a PSR
109 if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
110 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
115 crtc->debug.min_vbl = min;
116 crtc->debug.max_vbl = max;
117 trace_i915_pipe_update_start(crtc);
121 * prepare_to_wait() has a memory barrier, which guarantees
122 * other CPUs can see the task state update by the time we
125 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
127 scanline = intel_get_crtc_scanline(crtc);
128 if (scanline < min || scanline > max)
132 DRM_ERROR("Potential atomic update failure on pipe %c\n",
133 pipe_name(crtc->pipe));
139 timeout = schedule_timeout(timeout);
144 finish_wait(wq, &wait);
146 drm_crtc_vblank_put(&crtc->base);
149 * On VLV/CHV DSI the scanline counter would appear to
150 * increment approx. 1/3 of a scanline before start of vblank.
151 * The registers still get latched at start of vblank however.
152 * This means we must not write any registers on the first
153 * line of vblank (since not the whole line is actually in
154 * vblank). And unfortunately we can't use the interrupt to
155 * wait here since it will fire too soon. We could use the
156 * frame start interrupt instead since it will fire after the
157 * critical scanline, but that would require more changes
158 * in the interrupt code. So for now we'll just do the nasty
159 * thing and poll for the bad scanline to pass us by.
161 * FIXME figure out if BXT+ DSI suffers from this as well
163 while (need_vlv_dsi_wa && scanline == vblank_start)
164 scanline = intel_get_crtc_scanline(crtc);
166 crtc->debug.scanline_start = scanline;
167 crtc->debug.start_vbl_time = ktime_get();
168 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
170 trace_i915_pipe_update_vblank_evaded(crtc);
178 * intel_pipe_update_end() - end update of a set of display registers
179 * @new_crtc_state: the new crtc state
181 * Mark the end of an update started with intel_pipe_update_start(). This
182 * re-enables interrupts and verifies the update was actually completed
185 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
187 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
188 enum pipe pipe = crtc->pipe;
189 int scanline_end = intel_get_crtc_scanline(crtc);
190 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
191 ktime_t end_vbl_time = ktime_get();
192 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
194 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
196 /* We're still in the vblank-evade critical section, this can't race.
197 * Would be slightly nice to just grab the vblank count and arm the
198 * event outside of the critical section - the spinlock might spin for a
200 if (new_crtc_state->base.event) {
201 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
203 spin_lock(&crtc->base.dev->event_lock);
204 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
205 spin_unlock(&crtc->base.dev->event_lock);
207 new_crtc_state->base.event = NULL;
212 if (intel_vgpu_active(dev_priv))
215 if (crtc->debug.start_vbl_count &&
216 crtc->debug.start_vbl_count != end_vbl_count) {
217 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
218 pipe_name(pipe), crtc->debug.start_vbl_count,
220 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
221 crtc->debug.min_vbl, crtc->debug.max_vbl,
222 crtc->debug.scanline_start, scanline_end);
224 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
225 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
226 VBLANK_EVASION_TIME_US)
227 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
229 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
230 VBLANK_EVASION_TIME_US);
234 int intel_plane_check_stride(const struct intel_plane_state *plane_state)
236 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
237 const struct drm_framebuffer *fb = plane_state->base.fb;
238 unsigned int rotation = plane_state->base.rotation;
239 u32 stride, max_stride;
241 /* FIXME other color planes? */
242 stride = plane_state->color_plane[0].stride;
243 max_stride = plane->max_stride(plane, fb->format->format,
244 fb->modifier, rotation);
246 if (stride > max_stride) {
247 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
249 plane->base.base.id, plane->base.name, max_stride);
256 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
258 const struct drm_framebuffer *fb = plane_state->base.fb;
259 struct drm_rect *src = &plane_state->base.src;
260 u32 src_x, src_y, src_w, src_h;
263 * Hardware doesn't handle subpixel coordinates.
264 * Adjust to (macro)pixel boundary, but be careful not to
265 * increase the source viewport size, because that could
266 * push the downscaling factor out of bounds.
268 src_x = src->x1 >> 16;
269 src_w = drm_rect_width(src) >> 16;
270 src_y = src->y1 >> 16;
271 src_h = drm_rect_height(src) >> 16;
273 src->x1 = src_x << 16;
274 src->x2 = (src_x + src_w) << 16;
275 src->y1 = src_y << 16;
276 src->y2 = (src_y + src_h) << 16;
278 if (fb->format->is_yuv &&
279 (src_x & 1 || src_w & 1)) {
280 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
285 if (fb->format->is_yuv &&
286 fb->format->num_planes > 1 &&
287 (src_y & 1 || src_h & 1)) {
288 DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of 2 for planar YUV planes\n",
297 skl_plane_max_stride(struct intel_plane *plane,
298 u32 pixel_format, u64 modifier,
299 unsigned int rotation)
301 int cpp = drm_format_plane_cpp(pixel_format, 0);
304 * "The stride in bytes must not exceed the
305 * of the size of 8K pixels and 32K bytes."
307 if (drm_rotation_90_or_270(rotation))
308 return min(8192, 32768 / cpp);
310 return min(8192 * cpp, 32768);
314 skl_program_scaler(struct intel_plane *plane,
315 const struct intel_crtc_state *crtc_state,
316 const struct intel_plane_state *plane_state)
318 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
319 enum pipe pipe = plane->pipe;
320 int scaler_id = plane_state->scaler_id;
321 const struct intel_scaler *scaler =
322 &crtc_state->scaler_state.scalers[scaler_id];
323 int crtc_x = plane_state->base.dst.x1;
324 int crtc_y = plane_state->base.dst.y1;
325 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
326 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
327 u16 y_hphase, uv_rgb_hphase;
328 u16 y_vphase, uv_rgb_vphase;
331 hscale = drm_rect_calc_hscale(&plane_state->base.src,
332 &plane_state->base.dst,
334 vscale = drm_rect_calc_vscale(&plane_state->base.src,
335 &plane_state->base.dst,
338 /* TODO: handle sub-pixel coordinates */
339 if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
340 !icl_is_hdr_plane(plane)) {
341 y_hphase = skl_scaler_calc_phase(1, hscale, false);
342 y_vphase = skl_scaler_calc_phase(1, vscale, false);
344 /* MPEG2 chroma siting convention */
345 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
346 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
352 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
353 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
356 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
357 PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
358 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
359 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
360 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
361 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
362 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
363 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
366 /* Preoffset values for YUV to RGB Conversion */
367 #define PREOFF_YUV_TO_RGB_HI 0x1800
368 #define PREOFF_YUV_TO_RGB_ME 0x1F00
369 #define PREOFF_YUV_TO_RGB_LO 0x1800
371 #define ROFF(x) (((x) & 0xffff) << 16)
372 #define GOFF(x) (((x) & 0xffff) << 0)
373 #define BOFF(x) (((x) & 0xffff) << 16)
376 icl_program_input_csc(struct intel_plane *plane,
377 const struct intel_crtc_state *crtc_state,
378 const struct intel_plane_state *plane_state)
380 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
381 enum pipe pipe = plane->pipe;
382 enum plane_id plane_id = plane->id;
384 static const u16 input_csc_matrix[][9] = {
386 * BT.601 full range YCbCr -> full range RGB
387 * The matrix required is :
388 * [1.000, 0.000, 1.371,
389 * 1.000, -0.336, -0.698,
390 * 1.000, 1.732, 0.0000]
392 [DRM_COLOR_YCBCR_BT601] = {
394 0x8B28, 0x7800, 0x9AC0,
398 * BT.709 full range YCbCr -> full range RGB
399 * The matrix required is :
400 * [1.000, 0.000, 1.574,
401 * 1.000, -0.187, -0.468,
402 * 1.000, 1.855, 0.0000]
404 [DRM_COLOR_YCBCR_BT709] = {
406 0x9EF8, 0x7800, 0xABF8,
411 /* Matrix for Limited Range to Full Range Conversion */
412 static const u16 input_csc_matrix_lr[][9] = {
414 * BT.601 Limted range YCbCr -> full range RGB
415 * The matrix required is :
416 * [1.164384, 0.000, 1.596370,
417 * 1.138393, -0.382500, -0.794598,
418 * 1.138393, 1.971696, 0.0000]
420 [DRM_COLOR_YCBCR_BT601] = {
422 0x8CB8, 0x7918, 0x9C40,
426 * BT.709 Limited range YCbCr -> full range RGB
427 * The matrix required is :
428 * [1.164, 0.000, 1.833671,
429 * 1.138393, -0.213249, -0.532909,
430 * 1.138393, 2.112402, 0.0000]
432 [DRM_COLOR_YCBCR_BT709] = {
434 0x8888, 0x7918, 0xADA8,
440 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
441 csc = input_csc_matrix[plane_state->base.color_encoding];
443 csc = input_csc_matrix_lr[plane_state->base.color_encoding];
445 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) |
447 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2]));
448 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) |
450 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5]));
451 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) |
453 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8]));
455 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
456 PREOFF_YUV_TO_RGB_HI);
457 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
458 PREOFF_YUV_TO_RGB_ME);
459 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
460 PREOFF_YUV_TO_RGB_LO);
461 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
462 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
463 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
467 skl_program_plane(struct intel_plane *plane,
468 const struct intel_crtc_state *crtc_state,
469 const struct intel_plane_state *plane_state,
470 int color_plane, bool slave, u32 plane_ctl)
472 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
473 enum plane_id plane_id = plane->id;
474 enum pipe pipe = plane->pipe;
475 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
476 u32 surf_addr = plane_state->color_plane[color_plane].offset;
477 u32 stride = skl_plane_stride(plane_state, color_plane);
478 u32 aux_stride = skl_plane_stride(plane_state, 1);
479 int crtc_x = plane_state->base.dst.x1;
480 int crtc_y = plane_state->base.dst.y1;
481 uint32_t x = plane_state->color_plane[color_plane].x;
482 uint32_t y = plane_state->color_plane[color_plane].y;
483 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
484 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
485 struct intel_plane *linked = plane_state->linked_plane;
486 const struct drm_framebuffer *fb = plane_state->base.fb;
487 u8 alpha = plane_state->base.alpha >> 8;
488 unsigned long irqflags;
491 /* Sizes are 0 based */
495 keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
497 keymsk = key->channel_mask & 0x7ffffff;
499 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
501 /* The scaler will handle the output position */
502 if (plane_state->scaler_id >= 0) {
507 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
509 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
510 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
511 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
512 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
513 (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
515 if (icl_is_hdr_plane(plane)) {
519 /* Enable and use MPEG-2 chroma siting */
520 cus_ctl = PLANE_CUS_ENABLE |
522 PLANE_CUS_VPHASE_SIGN_NEGATIVE |
523 PLANE_CUS_VPHASE_0_25;
525 if (linked->id == PLANE_SPRITE5)
526 cus_ctl |= PLANE_CUS_PLANE_7;
527 else if (linked->id == PLANE_SPRITE4)
528 cus_ctl |= PLANE_CUS_PLANE_6;
530 MISSING_CASE(linked->id);
533 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
536 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
537 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
538 plane_state->color_ctl);
540 if (fb->format->is_yuv && icl_is_hdr_plane(plane))
541 icl_program_input_csc(plane, crtc_state, plane_state);
543 skl_write_plane_wm(plane, crtc_state);
545 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
546 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
547 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
549 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
551 if (INTEL_GEN(dev_priv) < 11)
552 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
553 (plane_state->color_plane[1].y << 16) |
554 plane_state->color_plane[1].x);
557 * The control register self-arms if the plane was previously
558 * disabled. Try to make the plane enable atomic by writing
559 * the control register just before the surface register.
561 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
562 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
563 intel_plane_ggtt_offset(plane_state) + surf_addr);
565 if (!slave && plane_state->scaler_id >= 0)
566 skl_program_scaler(plane, crtc_state, plane_state);
568 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
572 skl_update_plane(struct intel_plane *plane,
573 const struct intel_crtc_state *crtc_state,
574 const struct intel_plane_state *plane_state)
578 if (plane_state->linked_plane) {
579 /* Program the UV plane */
583 skl_program_plane(plane, crtc_state, plane_state,
584 color_plane, false, plane_state->ctl);
588 icl_update_slave(struct intel_plane *plane,
589 const struct intel_crtc_state *crtc_state,
590 const struct intel_plane_state *plane_state)
592 skl_program_plane(plane, crtc_state, plane_state, 0, true,
593 plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
597 skl_disable_plane(struct intel_plane *plane,
598 const struct intel_crtc_state *crtc_state)
600 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
601 enum plane_id plane_id = plane->id;
602 enum pipe pipe = plane->pipe;
603 unsigned long irqflags;
605 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
607 skl_write_plane_wm(plane, crtc_state);
609 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
610 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
612 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
616 skl_plane_get_hw_state(struct intel_plane *plane,
619 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
620 enum intel_display_power_domain power_domain;
621 enum plane_id plane_id = plane->id;
624 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
625 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
628 ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
632 intel_display_power_put(dev_priv, power_domain);
638 chv_update_csc(const struct intel_plane_state *plane_state)
640 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
641 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
642 const struct drm_framebuffer *fb = plane_state->base.fb;
643 enum plane_id plane_id = plane->id;
645 * |r| | c0 c1 c2 | |cr|
646 * |g| = | c3 c4 c5 | x |y |
647 * |b| | c6 c7 c8 | |cb|
649 * Coefficients are s3.12.
651 * Cb and Cr apparently come in as signed already, and
652 * we always get full range data in on account of CLRC0/1.
654 static const s16 csc_matrix[][9] = {
655 /* BT.601 full range YCbCr -> full range RGB */
656 [DRM_COLOR_YCBCR_BT601] = {
661 /* BT.709 full range YCbCr -> full range RGB */
662 [DRM_COLOR_YCBCR_BT709] = {
668 const s16 *csc = csc_matrix[plane_state->base.color_encoding];
670 /* Seems RGB data bypasses the CSC always */
671 if (!fb->format->is_yuv)
674 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
675 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
676 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
678 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
679 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
680 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
681 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
682 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
684 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
685 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
686 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
688 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
689 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
690 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
697 vlv_update_clrc(const struct intel_plane_state *plane_state)
699 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
700 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
701 const struct drm_framebuffer *fb = plane_state->base.fb;
702 enum pipe pipe = plane->pipe;
703 enum plane_id plane_id = plane->id;
704 int contrast, brightness, sh_scale, sh_sin, sh_cos;
706 if (fb->format->is_yuv &&
707 plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
709 * Expand limited range to full range:
710 * Contrast is applied first and is used to expand Y range.
711 * Brightness is applied second and is used to remove the
712 * offset from Y. Saturation/hue is used to expand CbCr range.
714 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
715 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
716 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
717 sh_sin = SIN_0 * sh_scale;
718 sh_cos = COS_0 * sh_scale;
720 /* Pass-through everything. */
724 sh_sin = SIN_0 * sh_scale;
725 sh_cos = COS_0 * sh_scale;
728 /* FIXME these register are single buffered :( */
729 I915_WRITE_FW(SPCLRC0(pipe, plane_id),
730 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
731 I915_WRITE_FW(SPCLRC1(pipe, plane_id),
732 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
735 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
736 const struct intel_plane_state *plane_state)
738 const struct drm_framebuffer *fb = plane_state->base.fb;
739 unsigned int rotation = plane_state->base.rotation;
740 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
743 sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
745 switch (fb->format->format) {
746 case DRM_FORMAT_YUYV:
747 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
749 case DRM_FORMAT_YVYU:
750 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
752 case DRM_FORMAT_UYVY:
753 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
755 case DRM_FORMAT_VYUY:
756 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
758 case DRM_FORMAT_RGB565:
759 sprctl |= SP_FORMAT_BGR565;
761 case DRM_FORMAT_XRGB8888:
762 sprctl |= SP_FORMAT_BGRX8888;
764 case DRM_FORMAT_ARGB8888:
765 sprctl |= SP_FORMAT_BGRA8888;
767 case DRM_FORMAT_XBGR2101010:
768 sprctl |= SP_FORMAT_RGBX1010102;
770 case DRM_FORMAT_ABGR2101010:
771 sprctl |= SP_FORMAT_RGBA1010102;
773 case DRM_FORMAT_XBGR8888:
774 sprctl |= SP_FORMAT_RGBX8888;
776 case DRM_FORMAT_ABGR8888:
777 sprctl |= SP_FORMAT_RGBA8888;
780 MISSING_CASE(fb->format->format);
784 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
785 sprctl |= SP_YUV_FORMAT_BT709;
787 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
790 if (rotation & DRM_MODE_ROTATE_180)
791 sprctl |= SP_ROTATE_180;
793 if (rotation & DRM_MODE_REFLECT_X)
796 if (key->flags & I915_SET_COLORKEY_SOURCE)
797 sprctl |= SP_SOURCE_KEY;
803 vlv_update_plane(struct intel_plane *plane,
804 const struct intel_crtc_state *crtc_state,
805 const struct intel_plane_state *plane_state)
807 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
808 enum pipe pipe = plane->pipe;
809 enum plane_id plane_id = plane->id;
810 u32 sprctl = plane_state->ctl;
811 u32 sprsurf_offset = plane_state->color_plane[0].offset;
813 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
814 int crtc_x = plane_state->base.dst.x1;
815 int crtc_y = plane_state->base.dst.y1;
816 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
817 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
818 uint32_t x = plane_state->color_plane[0].x;
819 uint32_t y = plane_state->color_plane[0].y;
820 unsigned long irqflags;
822 /* Sizes are 0 based */
826 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
828 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
830 I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
831 plane_state->color_plane[0].stride);
832 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
833 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
834 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
836 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
837 chv_update_csc(plane_state);
840 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
841 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
842 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
845 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
846 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
849 * The control register self-arms if the plane was previously
850 * disabled. Try to make the plane enable atomic by writing
851 * the control register just before the surface register.
853 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
854 I915_WRITE_FW(SPSURF(pipe, plane_id),
855 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
857 vlv_update_clrc(plane_state);
859 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
863 vlv_disable_plane(struct intel_plane *plane,
864 const struct intel_crtc_state *crtc_state)
866 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
867 enum pipe pipe = plane->pipe;
868 enum plane_id plane_id = plane->id;
869 unsigned long irqflags;
871 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
873 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
874 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
876 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
880 vlv_plane_get_hw_state(struct intel_plane *plane,
883 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
884 enum intel_display_power_domain power_domain;
885 enum plane_id plane_id = plane->id;
888 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
889 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
892 ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
896 intel_display_power_put(dev_priv, power_domain);
901 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
902 const struct intel_plane_state *plane_state)
904 struct drm_i915_private *dev_priv =
905 to_i915(plane_state->base.plane->dev);
906 const struct drm_framebuffer *fb = plane_state->base.fb;
907 unsigned int rotation = plane_state->base.rotation;
908 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
911 sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
913 if (IS_IVYBRIDGE(dev_priv))
914 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
916 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
917 sprctl |= SPRITE_PIPE_CSC_ENABLE;
919 switch (fb->format->format) {
920 case DRM_FORMAT_XBGR8888:
921 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
923 case DRM_FORMAT_XRGB8888:
924 sprctl |= SPRITE_FORMAT_RGBX888;
926 case DRM_FORMAT_YUYV:
927 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
929 case DRM_FORMAT_YVYU:
930 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
932 case DRM_FORMAT_UYVY:
933 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
935 case DRM_FORMAT_VYUY:
936 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
939 MISSING_CASE(fb->format->format);
943 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
944 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
946 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
947 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
949 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
950 sprctl |= SPRITE_TILED;
952 if (rotation & DRM_MODE_ROTATE_180)
953 sprctl |= SPRITE_ROTATE_180;
955 if (key->flags & I915_SET_COLORKEY_DESTINATION)
956 sprctl |= SPRITE_DEST_KEY;
957 else if (key->flags & I915_SET_COLORKEY_SOURCE)
958 sprctl |= SPRITE_SOURCE_KEY;
964 ivb_update_plane(struct intel_plane *plane,
965 const struct intel_crtc_state *crtc_state,
966 const struct intel_plane_state *plane_state)
968 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
969 enum pipe pipe = plane->pipe;
970 u32 sprctl = plane_state->ctl, sprscale = 0;
971 u32 sprsurf_offset = plane_state->color_plane[0].offset;
973 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
974 int crtc_x = plane_state->base.dst.x1;
975 int crtc_y = plane_state->base.dst.y1;
976 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
977 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
978 uint32_t x = plane_state->color_plane[0].x;
979 uint32_t y = plane_state->color_plane[0].y;
980 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
981 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
982 unsigned long irqflags;
984 /* Sizes are 0 based */
990 if (crtc_w != src_w || crtc_h != src_h)
991 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
993 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
995 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
997 I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
998 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
999 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
1000 if (IS_IVYBRIDGE(dev_priv))
1001 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
1004 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
1005 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
1006 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
1009 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
1011 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1012 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
1014 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
1015 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
1019 * The control register self-arms if the plane was previously
1020 * disabled. Try to make the plane enable atomic by writing
1021 * the control register just before the surface register.
1023 I915_WRITE_FW(SPRCTL(pipe), sprctl);
1024 I915_WRITE_FW(SPRSURF(pipe),
1025 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
1027 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1031 ivb_disable_plane(struct intel_plane *plane,
1032 const struct intel_crtc_state *crtc_state)
1034 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1035 enum pipe pipe = plane->pipe;
1036 unsigned long irqflags;
1038 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1040 I915_WRITE_FW(SPRCTL(pipe), 0);
1041 /* Disable the scaler */
1042 if (IS_IVYBRIDGE(dev_priv))
1043 I915_WRITE_FW(SPRSCALE(pipe), 0);
1044 I915_WRITE_FW(SPRSURF(pipe), 0);
1046 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1050 ivb_plane_get_hw_state(struct intel_plane *plane,
1053 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1054 enum intel_display_power_domain power_domain;
1057 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1058 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1061 ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
1063 *pipe = plane->pipe;
1065 intel_display_power_put(dev_priv, power_domain);
1071 g4x_sprite_max_stride(struct intel_plane *plane,
1072 u32 pixel_format, u64 modifier,
1073 unsigned int rotation)
1078 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
1079 const struct intel_plane_state *plane_state)
1081 struct drm_i915_private *dev_priv =
1082 to_i915(plane_state->base.plane->dev);
1083 const struct drm_framebuffer *fb = plane_state->base.fb;
1084 unsigned int rotation = plane_state->base.rotation;
1085 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1088 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
1090 if (IS_GEN6(dev_priv))
1091 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
1093 switch (fb->format->format) {
1094 case DRM_FORMAT_XBGR8888:
1095 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
1097 case DRM_FORMAT_XRGB8888:
1098 dvscntr |= DVS_FORMAT_RGBX888;
1100 case DRM_FORMAT_YUYV:
1101 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
1103 case DRM_FORMAT_YVYU:
1104 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
1106 case DRM_FORMAT_UYVY:
1107 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
1109 case DRM_FORMAT_VYUY:
1110 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
1113 MISSING_CASE(fb->format->format);
1117 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
1118 dvscntr |= DVS_YUV_FORMAT_BT709;
1120 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1121 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
1123 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1124 dvscntr |= DVS_TILED;
1126 if (rotation & DRM_MODE_ROTATE_180)
1127 dvscntr |= DVS_ROTATE_180;
1129 if (key->flags & I915_SET_COLORKEY_DESTINATION)
1130 dvscntr |= DVS_DEST_KEY;
1131 else if (key->flags & I915_SET_COLORKEY_SOURCE)
1132 dvscntr |= DVS_SOURCE_KEY;
1138 g4x_update_plane(struct intel_plane *plane,
1139 const struct intel_crtc_state *crtc_state,
1140 const struct intel_plane_state *plane_state)
1142 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1143 enum pipe pipe = plane->pipe;
1144 u32 dvscntr = plane_state->ctl, dvsscale = 0;
1145 u32 dvssurf_offset = plane_state->color_plane[0].offset;
1147 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1148 int crtc_x = plane_state->base.dst.x1;
1149 int crtc_y = plane_state->base.dst.y1;
1150 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
1151 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
1152 uint32_t x = plane_state->color_plane[0].x;
1153 uint32_t y = plane_state->color_plane[0].y;
1154 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
1155 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
1156 unsigned long irqflags;
1158 /* Sizes are 0 based */
1164 if (crtc_w != src_w || crtc_h != src_h)
1165 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
1167 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1169 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1171 I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
1172 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
1173 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
1174 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
1177 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
1178 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
1179 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
1182 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
1183 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
1186 * The control register self-arms if the plane was previously
1187 * disabled. Try to make the plane enable atomic by writing
1188 * the control register just before the surface register.
1190 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
1191 I915_WRITE_FW(DVSSURF(pipe),
1192 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
1194 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1198 g4x_disable_plane(struct intel_plane *plane,
1199 const struct intel_crtc_state *crtc_state)
1201 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1202 enum pipe pipe = plane->pipe;
1203 unsigned long irqflags;
1205 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1207 I915_WRITE_FW(DVSCNTR(pipe), 0);
1208 /* Disable the scaler */
1209 I915_WRITE_FW(DVSSCALE(pipe), 0);
1210 I915_WRITE_FW(DVSSURF(pipe), 0);
1212 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1216 g4x_plane_get_hw_state(struct intel_plane *plane,
1219 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1220 enum intel_display_power_domain power_domain;
1223 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1224 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1227 ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
1229 *pipe = plane->pipe;
1231 intel_display_power_put(dev_priv, power_domain);
1236 static bool intel_fb_scalable(const struct drm_framebuffer *fb)
1241 switch (fb->format->format) {
1250 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
1251 struct intel_plane_state *plane_state)
1253 const struct drm_framebuffer *fb = plane_state->base.fb;
1254 const struct drm_rect *src = &plane_state->base.src;
1255 const struct drm_rect *dst = &plane_state->base.dst;
1256 int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
1257 const struct drm_display_mode *adjusted_mode =
1258 &crtc_state->base.adjusted_mode;
1259 unsigned int cpp = fb->format->cpp[0];
1260 unsigned int width_bytes;
1261 int min_width, min_height;
1263 crtc_w = drm_rect_width(dst);
1264 crtc_h = drm_rect_height(dst);
1266 src_x = src->x1 >> 16;
1267 src_y = src->y1 >> 16;
1268 src_w = drm_rect_width(src) >> 16;
1269 src_h = drm_rect_height(src) >> 16;
1271 if (src_w == crtc_w && src_h == crtc_h)
1276 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1278 DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
1286 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1288 if (src_w < min_width || src_h < min_height ||
1289 src_w > 2048 || src_h > 2048) {
1290 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1291 src_w, src_h, min_width, min_height, 2048, 2048);
1295 if (width_bytes > 4096) {
1296 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1301 if (width_bytes > 4096 || fb->pitches[0] > 4096) {
1302 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1303 fb->pitches[0], 4096);
1311 g4x_sprite_check(struct intel_crtc_state *crtc_state,
1312 struct intel_plane_state *plane_state)
1314 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1315 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1316 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
1317 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1320 if (intel_fb_scalable(plane_state->base.fb)) {
1321 if (INTEL_GEN(dev_priv) < 7) {
1323 max_scale = 16 << 16;
1324 } else if (IS_IVYBRIDGE(dev_priv)) {
1326 max_scale = 2 << 16;
1330 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1332 min_scale, max_scale,
1337 if (!plane_state->base.visible)
1340 ret = intel_plane_check_src_coordinates(plane_state);
1344 ret = g4x_sprite_check_scaling(crtc_state, plane_state);
1348 ret = i9xx_check_plane_surface(plane_state);
1352 if (INTEL_GEN(dev_priv) >= 7)
1353 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
1355 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
1360 int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
1362 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1363 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1364 unsigned int rotation = plane_state->base.rotation;
1366 /* CHV ignores the mirror bit when the rotate bit is set :( */
1367 if (IS_CHERRYVIEW(dev_priv) &&
1368 rotation & DRM_MODE_ROTATE_180 &&
1369 rotation & DRM_MODE_REFLECT_X) {
1370 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
1378 vlv_sprite_check(struct intel_crtc_state *crtc_state,
1379 struct intel_plane_state *plane_state)
1383 ret = chv_plane_check_rotation(plane_state);
1387 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1389 DRM_PLANE_HELPER_NO_SCALING,
1390 DRM_PLANE_HELPER_NO_SCALING,
1395 if (!plane_state->base.visible)
1398 ret = intel_plane_check_src_coordinates(plane_state);
1402 ret = i9xx_check_plane_surface(plane_state);
1406 plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
1411 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1412 const struct intel_plane_state *plane_state)
1414 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1415 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1416 const struct drm_framebuffer *fb = plane_state->base.fb;
1417 unsigned int rotation = plane_state->base.rotation;
1418 struct drm_format_name_buf format_name;
1423 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1424 is_ccs_modifier(fb->modifier)) {
1425 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
1430 if (rotation & DRM_MODE_REFLECT_X &&
1431 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1432 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
1436 if (drm_rotation_90_or_270(rotation)) {
1437 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
1438 fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
1439 DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
1444 * 90/270 is not allowed with RGB64 16:16:16:16 and
1445 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
1446 * TBD: Add RGB64 case once its added in supported format
1449 switch (fb->format->format) {
1450 case DRM_FORMAT_RGB565:
1451 if (INTEL_GEN(dev_priv) >= 11)
1455 DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
1456 drm_get_format_name(fb->format->format,
1464 /* Y-tiling is not supported in IF-ID Interlace mode */
1465 if (crtc_state->base.enable &&
1466 crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1467 (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
1468 fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
1469 fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1470 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
1471 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
1478 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1479 const struct intel_plane_state *plane_state)
1481 struct drm_i915_private *dev_priv =
1482 to_i915(plane_state->base.plane->dev);
1483 int crtc_x = plane_state->base.dst.x1;
1484 int crtc_w = drm_rect_width(&plane_state->base.dst);
1485 int pipe_src_w = crtc_state->pipe_src_w;
1488 * Display WA #1175: cnl,glk
1489 * Planes other than the cursor may cause FIFO underflow and display
1490 * corruption if starting less than 4 pixels from the right edge of
1492 * Besides the above WA fix the similar problem, where planes other
1493 * than the cursor ending less than 4 pixels from the left edge of the
1494 * screen may cause FIFO underflow and display corruption.
1496 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
1497 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1498 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
1499 crtc_x + crtc_w < 4 ? "end" : "start",
1500 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1508 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
1510 const struct drm_framebuffer *fb = plane_state->base.fb;
1511 unsigned int rotation = plane_state->base.rotation;
1512 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
1514 /* Display WA #1106 */
1515 if (fb->format->format == DRM_FORMAT_NV12 && src_w & 3 &&
1516 (rotation == DRM_MODE_ROTATE_270 ||
1517 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
1518 DRM_DEBUG_KMS("src width must be multiple of 4 for rotated NV12\n");
1525 static int skl_plane_check(struct intel_crtc_state *crtc_state,
1526 struct intel_plane_state *plane_state)
1528 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1529 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1530 const struct drm_framebuffer *fb = plane_state->base.fb;
1531 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
1532 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1535 ret = skl_plane_check_fb(crtc_state, plane_state);
1539 /* use scaler when colorkey is not required */
1540 if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
1542 max_scale = skl_max_scale(crtc_state, fb->format->format);
1545 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1547 min_scale, max_scale,
1552 if (!plane_state->base.visible)
1555 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1559 ret = intel_plane_check_src_coordinates(plane_state);
1563 ret = skl_plane_check_nv12_rotation(plane_state);
1567 ret = skl_check_plane_surface(plane_state);
1571 /* HW only has 8 bits pixel precision, disable plane if invisible */
1572 if (!(plane_state->base.alpha >> 8))
1573 plane_state->base.visible = false;
1575 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1577 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1578 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1584 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
1586 return INTEL_GEN(dev_priv) >= 9;
1589 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
1590 const struct drm_intel_sprite_colorkey *set)
1592 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1593 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1594 struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1599 * We want src key enabled on the
1600 * sprite and not on the primary.
1602 if (plane->id == PLANE_PRIMARY &&
1603 set->flags & I915_SET_COLORKEY_SOURCE)
1607 * On SKL+ we want dst key enabled on
1608 * the primary and not on the sprite.
1610 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
1611 set->flags & I915_SET_COLORKEY_DESTINATION)
1615 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1616 struct drm_file *file_priv)
1618 struct drm_i915_private *dev_priv = to_i915(dev);
1619 struct drm_intel_sprite_colorkey *set = data;
1620 struct drm_plane *plane;
1621 struct drm_plane_state *plane_state;
1622 struct drm_atomic_state *state;
1623 struct drm_modeset_acquire_ctx ctx;
1626 /* ignore the pointless "none" flag */
1627 set->flags &= ~I915_SET_COLORKEY_NONE;
1629 if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1632 /* Make sure we don't try to enable both src & dest simultaneously */
1633 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1636 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1637 set->flags & I915_SET_COLORKEY_DESTINATION)
1640 plane = drm_plane_find(dev, file_priv, set->plane_id);
1641 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1645 * SKL+ only plane 2 can do destination keying against plane 1.
1646 * Also multiple planes can't do destination keying on the same
1647 * pipe simultaneously.
1649 if (INTEL_GEN(dev_priv) >= 9 &&
1650 to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
1651 set->flags & I915_SET_COLORKEY_DESTINATION)
1654 drm_modeset_acquire_init(&ctx, 0);
1656 state = drm_atomic_state_alloc(plane->dev);
1661 state->acquire_ctx = &ctx;
1664 plane_state = drm_atomic_get_plane_state(state, plane);
1665 ret = PTR_ERR_OR_ZERO(plane_state);
1667 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1670 * On some platforms we have to configure
1671 * the dst colorkey on the primary plane.
1673 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
1674 struct intel_crtc *crtc =
1675 intel_get_crtc_for_pipe(dev_priv,
1676 to_intel_plane(plane)->pipe);
1678 plane_state = drm_atomic_get_plane_state(state,
1679 crtc->base.primary);
1680 ret = PTR_ERR_OR_ZERO(plane_state);
1682 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1686 ret = drm_atomic_commit(state);
1688 if (ret != -EDEADLK)
1691 drm_atomic_state_clear(state);
1692 drm_modeset_backoff(&ctx);
1695 drm_atomic_state_put(state);
1697 drm_modeset_drop_locks(&ctx);
1698 drm_modeset_acquire_fini(&ctx);
1702 static const uint32_t g4x_plane_formats[] = {
1703 DRM_FORMAT_XRGB8888,
1710 static const uint64_t i9xx_plane_format_modifiers[] = {
1711 I915_FORMAT_MOD_X_TILED,
1712 DRM_FORMAT_MOD_LINEAR,
1713 DRM_FORMAT_MOD_INVALID
1716 static const uint32_t snb_plane_formats[] = {
1717 DRM_FORMAT_XBGR8888,
1718 DRM_FORMAT_XRGB8888,
1725 static const uint32_t vlv_plane_formats[] = {
1727 DRM_FORMAT_ABGR8888,
1728 DRM_FORMAT_ARGB8888,
1729 DRM_FORMAT_XBGR8888,
1730 DRM_FORMAT_XRGB8888,
1731 DRM_FORMAT_XBGR2101010,
1732 DRM_FORMAT_ABGR2101010,
1739 static const uint32_t skl_plane_formats[] = {
1742 DRM_FORMAT_XRGB8888,
1743 DRM_FORMAT_XBGR8888,
1744 DRM_FORMAT_ARGB8888,
1745 DRM_FORMAT_ABGR8888,
1746 DRM_FORMAT_XRGB2101010,
1747 DRM_FORMAT_XBGR2101010,
1754 static const uint32_t skl_planar_formats[] = {
1757 DRM_FORMAT_XRGB8888,
1758 DRM_FORMAT_XBGR8888,
1759 DRM_FORMAT_ARGB8888,
1760 DRM_FORMAT_ABGR8888,
1761 DRM_FORMAT_XRGB2101010,
1762 DRM_FORMAT_XBGR2101010,
1770 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1771 I915_FORMAT_MOD_Yf_TILED,
1772 I915_FORMAT_MOD_Y_TILED,
1773 I915_FORMAT_MOD_X_TILED,
1774 DRM_FORMAT_MOD_LINEAR,
1775 DRM_FORMAT_MOD_INVALID
1778 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1779 I915_FORMAT_MOD_Yf_TILED_CCS,
1780 I915_FORMAT_MOD_Y_TILED_CCS,
1781 I915_FORMAT_MOD_Yf_TILED,
1782 I915_FORMAT_MOD_Y_TILED,
1783 I915_FORMAT_MOD_X_TILED,
1784 DRM_FORMAT_MOD_LINEAR,
1785 DRM_FORMAT_MOD_INVALID
1788 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
1789 u32 format, u64 modifier)
1792 case DRM_FORMAT_MOD_LINEAR:
1793 case I915_FORMAT_MOD_X_TILED:
1800 case DRM_FORMAT_XRGB8888:
1801 case DRM_FORMAT_YUYV:
1802 case DRM_FORMAT_YVYU:
1803 case DRM_FORMAT_UYVY:
1804 case DRM_FORMAT_VYUY:
1805 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1806 modifier == I915_FORMAT_MOD_X_TILED)
1814 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
1815 u32 format, u64 modifier)
1818 case DRM_FORMAT_MOD_LINEAR:
1819 case I915_FORMAT_MOD_X_TILED:
1826 case DRM_FORMAT_XRGB8888:
1827 case DRM_FORMAT_XBGR8888:
1828 case DRM_FORMAT_YUYV:
1829 case DRM_FORMAT_YVYU:
1830 case DRM_FORMAT_UYVY:
1831 case DRM_FORMAT_VYUY:
1832 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1833 modifier == I915_FORMAT_MOD_X_TILED)
1841 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
1842 u32 format, u64 modifier)
1845 case DRM_FORMAT_MOD_LINEAR:
1846 case I915_FORMAT_MOD_X_TILED:
1853 case DRM_FORMAT_RGB565:
1854 case DRM_FORMAT_ABGR8888:
1855 case DRM_FORMAT_ARGB8888:
1856 case DRM_FORMAT_XBGR8888:
1857 case DRM_FORMAT_XRGB8888:
1858 case DRM_FORMAT_XBGR2101010:
1859 case DRM_FORMAT_ABGR2101010:
1860 case DRM_FORMAT_YUYV:
1861 case DRM_FORMAT_YVYU:
1862 case DRM_FORMAT_UYVY:
1863 case DRM_FORMAT_VYUY:
1864 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1865 modifier == I915_FORMAT_MOD_X_TILED)
1873 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1874 u32 format, u64 modifier)
1876 struct intel_plane *plane = to_intel_plane(_plane);
1879 case DRM_FORMAT_MOD_LINEAR:
1880 case I915_FORMAT_MOD_X_TILED:
1881 case I915_FORMAT_MOD_Y_TILED:
1882 case I915_FORMAT_MOD_Yf_TILED:
1884 case I915_FORMAT_MOD_Y_TILED_CCS:
1885 case I915_FORMAT_MOD_Yf_TILED_CCS:
1886 if (!plane->has_ccs)
1894 case DRM_FORMAT_XRGB8888:
1895 case DRM_FORMAT_XBGR8888:
1896 case DRM_FORMAT_ARGB8888:
1897 case DRM_FORMAT_ABGR8888:
1898 if (is_ccs_modifier(modifier))
1901 case DRM_FORMAT_RGB565:
1902 case DRM_FORMAT_XRGB2101010:
1903 case DRM_FORMAT_XBGR2101010:
1904 case DRM_FORMAT_YUYV:
1905 case DRM_FORMAT_YVYU:
1906 case DRM_FORMAT_UYVY:
1907 case DRM_FORMAT_VYUY:
1908 case DRM_FORMAT_NV12:
1909 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1913 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1914 modifier == I915_FORMAT_MOD_X_TILED ||
1915 modifier == I915_FORMAT_MOD_Y_TILED)
1923 static const struct drm_plane_funcs g4x_sprite_funcs = {
1924 .update_plane = drm_atomic_helper_update_plane,
1925 .disable_plane = drm_atomic_helper_disable_plane,
1926 .destroy = intel_plane_destroy,
1927 .atomic_get_property = intel_plane_atomic_get_property,
1928 .atomic_set_property = intel_plane_atomic_set_property,
1929 .atomic_duplicate_state = intel_plane_duplicate_state,
1930 .atomic_destroy_state = intel_plane_destroy_state,
1931 .format_mod_supported = g4x_sprite_format_mod_supported,
1934 static const struct drm_plane_funcs snb_sprite_funcs = {
1935 .update_plane = drm_atomic_helper_update_plane,
1936 .disable_plane = drm_atomic_helper_disable_plane,
1937 .destroy = intel_plane_destroy,
1938 .atomic_get_property = intel_plane_atomic_get_property,
1939 .atomic_set_property = intel_plane_atomic_set_property,
1940 .atomic_duplicate_state = intel_plane_duplicate_state,
1941 .atomic_destroy_state = intel_plane_destroy_state,
1942 .format_mod_supported = snb_sprite_format_mod_supported,
1945 static const struct drm_plane_funcs vlv_sprite_funcs = {
1946 .update_plane = drm_atomic_helper_update_plane,
1947 .disable_plane = drm_atomic_helper_disable_plane,
1948 .destroy = intel_plane_destroy,
1949 .atomic_get_property = intel_plane_atomic_get_property,
1950 .atomic_set_property = intel_plane_atomic_set_property,
1951 .atomic_duplicate_state = intel_plane_duplicate_state,
1952 .atomic_destroy_state = intel_plane_destroy_state,
1953 .format_mod_supported = vlv_sprite_format_mod_supported,
1956 static const struct drm_plane_funcs skl_plane_funcs = {
1957 .update_plane = drm_atomic_helper_update_plane,
1958 .disable_plane = drm_atomic_helper_disable_plane,
1959 .destroy = intel_plane_destroy,
1960 .atomic_get_property = intel_plane_atomic_get_property,
1961 .atomic_set_property = intel_plane_atomic_set_property,
1962 .atomic_duplicate_state = intel_plane_duplicate_state,
1963 .atomic_destroy_state = intel_plane_destroy_state,
1964 .format_mod_supported = skl_plane_format_mod_supported,
1967 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
1968 enum pipe pipe, enum plane_id plane_id)
1970 if (!HAS_FBC(dev_priv))
1973 return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
1976 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
1977 enum pipe pipe, enum plane_id plane_id)
1979 if (INTEL_GEN(dev_priv) >= 11)
1980 return plane_id <= PLANE_SPRITE3;
1982 /* Display WA #0870: skl, bxt */
1983 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
1986 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
1989 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
1995 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1996 enum pipe pipe, enum plane_id plane_id)
1998 if (plane_id == PLANE_CURSOR)
2001 if (INTEL_GEN(dev_priv) >= 10)
2004 if (IS_GEMINILAKE(dev_priv))
2005 return pipe != PIPE_C;
2007 return pipe != PIPE_C &&
2008 (plane_id == PLANE_PRIMARY ||
2009 plane_id == PLANE_SPRITE0);
2012 struct intel_plane *
2013 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2014 enum pipe pipe, enum plane_id plane_id)
2016 struct intel_plane *plane;
2017 enum drm_plane_type plane_type;
2018 unsigned int supported_rotations;
2019 unsigned int possible_crtcs;
2020 const u64 *modifiers;
2025 plane = intel_plane_alloc();
2030 plane->id = plane_id;
2031 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
2033 plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id);
2034 if (plane->has_fbc) {
2035 struct intel_fbc *fbc = &dev_priv->fbc;
2037 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
2040 plane->max_stride = skl_plane_max_stride;
2041 plane->update_plane = skl_update_plane;
2042 plane->disable_plane = skl_disable_plane;
2043 plane->get_hw_state = skl_plane_get_hw_state;
2044 plane->check_plane = skl_plane_check;
2045 if (icl_is_nv12_y_plane(plane_id))
2046 plane->update_slave = icl_update_slave;
2048 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2049 formats = skl_planar_formats;
2050 num_formats = ARRAY_SIZE(skl_planar_formats);
2052 formats = skl_plane_formats;
2053 num_formats = ARRAY_SIZE(skl_plane_formats);
2056 plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
2058 modifiers = skl_plane_format_modifiers_ccs;
2060 modifiers = skl_plane_format_modifiers_noccs;
2062 if (plane_id == PLANE_PRIMARY)
2063 plane_type = DRM_PLANE_TYPE_PRIMARY;
2065 plane_type = DRM_PLANE_TYPE_OVERLAY;
2067 possible_crtcs = BIT(pipe);
2069 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2070 possible_crtcs, &skl_plane_funcs,
2071 formats, num_formats, modifiers,
2073 "plane %d%c", plane_id + 1,
2078 supported_rotations =
2079 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
2080 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
2082 if (INTEL_GEN(dev_priv) >= 10)
2083 supported_rotations |= DRM_MODE_REFLECT_X;
2085 drm_plane_create_rotation_property(&plane->base,
2087 supported_rotations);
2089 drm_plane_create_color_properties(&plane->base,
2090 BIT(DRM_COLOR_YCBCR_BT601) |
2091 BIT(DRM_COLOR_YCBCR_BT709),
2092 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2093 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2094 DRM_COLOR_YCBCR_BT709,
2095 DRM_COLOR_YCBCR_LIMITED_RANGE);
2097 drm_plane_create_alpha_property(&plane->base);
2098 drm_plane_create_blend_mode_property(&plane->base,
2099 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2100 BIT(DRM_MODE_BLEND_PREMULTI) |
2101 BIT(DRM_MODE_BLEND_COVERAGE));
2103 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
2108 intel_plane_free(plane);
2110 return ERR_PTR(ret);
2113 struct intel_plane *
2114 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2115 enum pipe pipe, int sprite)
2117 struct intel_plane *plane;
2118 const struct drm_plane_funcs *plane_funcs;
2119 unsigned long possible_crtcs;
2120 unsigned int supported_rotations;
2121 const u64 *modifiers;
2126 if (INTEL_GEN(dev_priv) >= 9)
2127 return skl_universal_plane_create(dev_priv, pipe,
2128 PLANE_SPRITE0 + sprite);
2130 plane = intel_plane_alloc();
2134 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2135 plane->max_stride = i9xx_plane_max_stride;
2136 plane->update_plane = vlv_update_plane;
2137 plane->disable_plane = vlv_disable_plane;
2138 plane->get_hw_state = vlv_plane_get_hw_state;
2139 plane->check_plane = vlv_sprite_check;
2141 formats = vlv_plane_formats;
2142 num_formats = ARRAY_SIZE(vlv_plane_formats);
2143 modifiers = i9xx_plane_format_modifiers;
2145 plane_funcs = &vlv_sprite_funcs;
2146 } else if (INTEL_GEN(dev_priv) >= 7) {
2147 plane->max_stride = g4x_sprite_max_stride;
2148 plane->update_plane = ivb_update_plane;
2149 plane->disable_plane = ivb_disable_plane;
2150 plane->get_hw_state = ivb_plane_get_hw_state;
2151 plane->check_plane = g4x_sprite_check;
2153 formats = snb_plane_formats;
2154 num_formats = ARRAY_SIZE(snb_plane_formats);
2155 modifiers = i9xx_plane_format_modifiers;
2157 plane_funcs = &snb_sprite_funcs;
2159 plane->max_stride = g4x_sprite_max_stride;
2160 plane->update_plane = g4x_update_plane;
2161 plane->disable_plane = g4x_disable_plane;
2162 plane->get_hw_state = g4x_plane_get_hw_state;
2163 plane->check_plane = g4x_sprite_check;
2165 modifiers = i9xx_plane_format_modifiers;
2166 if (IS_GEN6(dev_priv)) {
2167 formats = snb_plane_formats;
2168 num_formats = ARRAY_SIZE(snb_plane_formats);
2170 plane_funcs = &snb_sprite_funcs;
2172 formats = g4x_plane_formats;
2173 num_formats = ARRAY_SIZE(g4x_plane_formats);
2175 plane_funcs = &g4x_sprite_funcs;
2179 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2180 supported_rotations =
2181 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
2184 supported_rotations =
2185 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
2189 plane->id = PLANE_SPRITE0 + sprite;
2190 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
2192 possible_crtcs = BIT(pipe);
2194 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2195 possible_crtcs, plane_funcs,
2196 formats, num_formats, modifiers,
2197 DRM_PLANE_TYPE_OVERLAY,
2198 "sprite %c", sprite_name(pipe, sprite));
2202 drm_plane_create_rotation_property(&plane->base,
2204 supported_rotations);
2206 drm_plane_create_color_properties(&plane->base,
2207 BIT(DRM_COLOR_YCBCR_BT601) |
2208 BIT(DRM_COLOR_YCBCR_BT709),
2209 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2210 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2211 DRM_COLOR_YCBCR_BT709,
2212 DRM_COLOR_YCBCR_LIMITED_RANGE);
2214 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
2219 intel_plane_free(plane);
2221 return ERR_PTR(ret);