2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include "intel_frontbuffer.h"
40 #include <drm/i915_drm.h>
42 #include <drm/drm_color_mgmt.h>
44 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
48 if (!adjusted_mode->crtc_htotal)
51 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
52 1000 * adjusted_mode->crtc_htotal);
55 /* FIXME: We should instead only take spinlocks once for the entire update
56 * instead of once per mmio. */
57 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
58 #define VBLANK_EVASION_TIME_US 250
60 #define VBLANK_EVASION_TIME_US 100
64 * intel_pipe_update_start() - start update of a set of display registers
65 * @new_crtc_state: the new crtc state
67 * Mark the start of an update to pipe registers that should be updated
68 * atomically regarding vblank. If the next vblank will happens within
69 * the next 100 us, this function waits until the vblank passes.
71 * After a successful call to this function, interrupts will be disabled
72 * until a subsequent call to intel_pipe_update_end(). That is done to
73 * avoid random delays.
75 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
77 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
78 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
79 const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
80 long timeout = msecs_to_jiffies_timeout(1);
81 int scanline, min, max, vblank_start;
82 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
83 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
84 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
88 vblank_start = adjusted_mode->crtc_vblank_start;
89 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
90 vblank_start = DIV_ROUND_UP(vblank_start, 2);
92 /* FIXME needs to be calibrated sensibly */
93 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
94 VBLANK_EVASION_TIME_US);
95 max = vblank_start - 1;
97 if (min <= 0 || max <= 0)
100 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
104 * Wait for psr to idle out after enabling the VBL interrupts
105 * VBL interrupts will start the PSR exit and prevent a PSR
108 if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
109 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
114 crtc->debug.min_vbl = min;
115 crtc->debug.max_vbl = max;
116 trace_i915_pipe_update_start(crtc);
120 * prepare_to_wait() has a memory barrier, which guarantees
121 * other CPUs can see the task state update by the time we
124 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
126 scanline = intel_get_crtc_scanline(crtc);
127 if (scanline < min || scanline > max)
131 DRM_ERROR("Potential atomic update failure on pipe %c\n",
132 pipe_name(crtc->pipe));
138 timeout = schedule_timeout(timeout);
143 finish_wait(wq, &wait);
145 drm_crtc_vblank_put(&crtc->base);
148 * On VLV/CHV DSI the scanline counter would appear to
149 * increment approx. 1/3 of a scanline before start of vblank.
150 * The registers still get latched at start of vblank however.
151 * This means we must not write any registers on the first
152 * line of vblank (since not the whole line is actually in
153 * vblank). And unfortunately we can't use the interrupt to
154 * wait here since it will fire too soon. We could use the
155 * frame start interrupt instead since it will fire after the
156 * critical scanline, but that would require more changes
157 * in the interrupt code. So for now we'll just do the nasty
158 * thing and poll for the bad scanline to pass us by.
160 * FIXME figure out if BXT+ DSI suffers from this as well
162 while (need_vlv_dsi_wa && scanline == vblank_start)
163 scanline = intel_get_crtc_scanline(crtc);
165 crtc->debug.scanline_start = scanline;
166 crtc->debug.start_vbl_time = ktime_get();
167 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
169 trace_i915_pipe_update_vblank_evaded(crtc);
177 * intel_pipe_update_end() - end update of a set of display registers
178 * @new_crtc_state: the new crtc state
180 * Mark the end of an update started with intel_pipe_update_start(). This
181 * re-enables interrupts and verifies the update was actually completed
184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
186 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
187 enum pipe pipe = crtc->pipe;
188 int scanline_end = intel_get_crtc_scanline(crtc);
189 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
190 ktime_t end_vbl_time = ktime_get();
191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
193 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
195 /* We're still in the vblank-evade critical section, this can't race.
196 * Would be slightly nice to just grab the vblank count and arm the
197 * event outside of the critical section - the spinlock might spin for a
199 if (new_crtc_state->base.event) {
200 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
202 spin_lock(&crtc->base.dev->event_lock);
203 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
204 spin_unlock(&crtc->base.dev->event_lock);
206 new_crtc_state->base.event = NULL;
211 if (intel_vgpu_active(dev_priv))
214 if (crtc->debug.start_vbl_count &&
215 crtc->debug.start_vbl_count != end_vbl_count) {
216 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
217 pipe_name(pipe), crtc->debug.start_vbl_count,
219 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
220 crtc->debug.min_vbl, crtc->debug.max_vbl,
221 crtc->debug.scanline_start, scanline_end);
223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
224 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
225 VBLANK_EVASION_TIME_US)
226 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
228 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
229 VBLANK_EVASION_TIME_US);
233 int intel_plane_check_stride(const struct intel_plane_state *plane_state)
235 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
236 const struct drm_framebuffer *fb = plane_state->base.fb;
237 unsigned int rotation = plane_state->base.rotation;
238 u32 stride, max_stride;
240 /* FIXME other color planes? */
241 stride = plane_state->color_plane[0].stride;
242 max_stride = plane->max_stride(plane, fb->format->format,
243 fb->modifier, rotation);
245 if (stride > max_stride) {
246 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
248 plane->base.base.id, plane->base.name, max_stride);
255 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
257 const struct drm_framebuffer *fb = plane_state->base.fb;
258 struct drm_rect *src = &plane_state->base.src;
259 u32 src_x, src_y, src_w, src_h;
262 * Hardware doesn't handle subpixel coordinates.
263 * Adjust to (macro)pixel boundary, but be careful not to
264 * increase the source viewport size, because that could
265 * push the downscaling factor out of bounds.
267 src_x = src->x1 >> 16;
268 src_w = drm_rect_width(src) >> 16;
269 src_y = src->y1 >> 16;
270 src_h = drm_rect_height(src) >> 16;
272 src->x1 = src_x << 16;
273 src->x2 = (src_x + src_w) << 16;
274 src->y1 = src_y << 16;
275 src->y2 = (src_y + src_h) << 16;
277 if (fb->format->is_yuv &&
278 (src_x & 1 || src_w & 1)) {
279 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
284 if (fb->format->is_yuv &&
285 fb->format->num_planes > 1 &&
286 (src_y & 1 || src_h & 1)) {
287 DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of 2 for planar YUV planes\n",
296 skl_plane_max_stride(struct intel_plane *plane,
297 u32 pixel_format, u64 modifier,
298 unsigned int rotation)
300 int cpp = drm_format_plane_cpp(pixel_format, 0);
303 * "The stride in bytes must not exceed the
304 * of the size of 8K pixels and 32K bytes."
306 if (drm_rotation_90_or_270(rotation))
307 return min(8192, 32768 / cpp);
309 return min(8192 * cpp, 32768);
313 skl_program_scaler(struct intel_plane *plane,
314 const struct intel_crtc_state *crtc_state,
315 const struct intel_plane_state *plane_state)
317 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
318 enum pipe pipe = plane->pipe;
319 int scaler_id = plane_state->scaler_id;
320 const struct intel_scaler *scaler =
321 &crtc_state->scaler_state.scalers[scaler_id];
322 int crtc_x = plane_state->base.dst.x1;
323 int crtc_y = plane_state->base.dst.y1;
324 u32 crtc_w = drm_rect_width(&plane_state->base.dst);
325 u32 crtc_h = drm_rect_height(&plane_state->base.dst);
326 u16 y_hphase, uv_rgb_hphase;
327 u16 y_vphase, uv_rgb_vphase;
330 hscale = drm_rect_calc_hscale(&plane_state->base.src,
331 &plane_state->base.dst,
333 vscale = drm_rect_calc_vscale(&plane_state->base.src,
334 &plane_state->base.dst,
337 /* TODO: handle sub-pixel coordinates */
338 if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
339 !icl_is_hdr_plane(plane)) {
340 y_hphase = skl_scaler_calc_phase(1, hscale, false);
341 y_vphase = skl_scaler_calc_phase(1, vscale, false);
343 /* MPEG2 chroma siting convention */
344 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
345 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
351 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
352 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
355 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
356 PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
357 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
358 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
359 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
360 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
361 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
362 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
365 /* Preoffset values for YUV to RGB Conversion */
366 #define PREOFF_YUV_TO_RGB_HI 0x1800
367 #define PREOFF_YUV_TO_RGB_ME 0x1F00
368 #define PREOFF_YUV_TO_RGB_LO 0x1800
370 #define ROFF(x) (((x) & 0xffff) << 16)
371 #define GOFF(x) (((x) & 0xffff) << 0)
372 #define BOFF(x) (((x) & 0xffff) << 16)
375 icl_program_input_csc(struct intel_plane *plane,
376 const struct intel_crtc_state *crtc_state,
377 const struct intel_plane_state *plane_state)
379 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
380 enum pipe pipe = plane->pipe;
381 enum plane_id plane_id = plane->id;
383 static const u16 input_csc_matrix[][9] = {
385 * BT.601 full range YCbCr -> full range RGB
386 * The matrix required is :
387 * [1.000, 0.000, 1.371,
388 * 1.000, -0.336, -0.698,
389 * 1.000, 1.732, 0.0000]
391 [DRM_COLOR_YCBCR_BT601] = {
393 0x8B28, 0x7800, 0x9AC0,
397 * BT.709 full range YCbCr -> full range RGB
398 * The matrix required is :
399 * [1.000, 0.000, 1.574,
400 * 1.000, -0.187, -0.468,
401 * 1.000, 1.855, 0.0000]
403 [DRM_COLOR_YCBCR_BT709] = {
405 0x9EF8, 0x7800, 0xABF8,
410 /* Matrix for Limited Range to Full Range Conversion */
411 static const u16 input_csc_matrix_lr[][9] = {
413 * BT.601 Limted range YCbCr -> full range RGB
414 * The matrix required is :
415 * [1.164384, 0.000, 1.596370,
416 * 1.138393, -0.382500, -0.794598,
417 * 1.138393, 1.971696, 0.0000]
419 [DRM_COLOR_YCBCR_BT601] = {
421 0x8CB8, 0x7918, 0x9C40,
425 * BT.709 Limited range YCbCr -> full range RGB
426 * The matrix required is :
427 * [1.164, 0.000, 1.833671,
428 * 1.138393, -0.213249, -0.532909,
429 * 1.138393, 2.112402, 0.0000]
431 [DRM_COLOR_YCBCR_BT709] = {
433 0x8888, 0x7918, 0xADA8,
439 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
440 csc = input_csc_matrix[plane_state->base.color_encoding];
442 csc = input_csc_matrix_lr[plane_state->base.color_encoding];
444 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) |
446 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2]));
447 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) |
449 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5]));
450 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) |
452 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8]));
454 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
455 PREOFF_YUV_TO_RGB_HI);
456 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
457 PREOFF_YUV_TO_RGB_ME);
458 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
459 PREOFF_YUV_TO_RGB_LO);
460 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
461 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
462 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
466 skl_program_plane(struct intel_plane *plane,
467 const struct intel_crtc_state *crtc_state,
468 const struct intel_plane_state *plane_state,
469 int color_plane, bool slave, u32 plane_ctl)
471 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
472 enum plane_id plane_id = plane->id;
473 enum pipe pipe = plane->pipe;
474 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
475 u32 surf_addr = plane_state->color_plane[color_plane].offset;
476 u32 stride = skl_plane_stride(plane_state, color_plane);
477 u32 aux_stride = skl_plane_stride(plane_state, 1);
478 int crtc_x = plane_state->base.dst.x1;
479 int crtc_y = plane_state->base.dst.y1;
480 u32 x = plane_state->color_plane[color_plane].x;
481 u32 y = plane_state->color_plane[color_plane].y;
482 u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
483 u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
484 struct intel_plane *linked = plane_state->linked_plane;
485 const struct drm_framebuffer *fb = plane_state->base.fb;
486 u8 alpha = plane_state->base.alpha >> 8;
487 u32 plane_color_ctl = 0;
488 unsigned long irqflags;
491 plane_ctl |= skl_plane_ctl_crtc(crtc_state);
493 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
494 plane_color_ctl = plane_state->color_ctl |
495 glk_plane_color_ctl_crtc(crtc_state);
497 /* Sizes are 0 based */
501 keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
503 keymsk = key->channel_mask & 0x7ffffff;
505 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
507 /* The scaler will handle the output position */
508 if (plane_state->scaler_id >= 0) {
513 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
515 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
516 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
517 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
518 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
519 (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
521 if (icl_is_hdr_plane(plane)) {
525 /* Enable and use MPEG-2 chroma siting */
526 cus_ctl = PLANE_CUS_ENABLE |
528 PLANE_CUS_VPHASE_SIGN_NEGATIVE |
529 PLANE_CUS_VPHASE_0_25;
531 if (linked->id == PLANE_SPRITE5)
532 cus_ctl |= PLANE_CUS_PLANE_7;
533 else if (linked->id == PLANE_SPRITE4)
534 cus_ctl |= PLANE_CUS_PLANE_6;
536 MISSING_CASE(linked->id);
539 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
542 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
543 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
545 if (fb->format->is_yuv && icl_is_hdr_plane(plane))
546 icl_program_input_csc(plane, crtc_state, plane_state);
548 skl_write_plane_wm(plane, crtc_state);
550 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
551 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
552 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
554 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
556 if (INTEL_GEN(dev_priv) < 11)
557 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
558 (plane_state->color_plane[1].y << 16) |
559 plane_state->color_plane[1].x);
562 * The control register self-arms if the plane was previously
563 * disabled. Try to make the plane enable atomic by writing
564 * the control register just before the surface register.
566 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
567 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
568 intel_plane_ggtt_offset(plane_state) + surf_addr);
570 if (!slave && plane_state->scaler_id >= 0)
571 skl_program_scaler(plane, crtc_state, plane_state);
573 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
577 skl_update_plane(struct intel_plane *plane,
578 const struct intel_crtc_state *crtc_state,
579 const struct intel_plane_state *plane_state)
583 if (plane_state->linked_plane) {
584 /* Program the UV plane */
588 skl_program_plane(plane, crtc_state, plane_state,
589 color_plane, false, plane_state->ctl);
593 icl_update_slave(struct intel_plane *plane,
594 const struct intel_crtc_state *crtc_state,
595 const struct intel_plane_state *plane_state)
597 skl_program_plane(plane, crtc_state, plane_state, 0, true,
598 plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
602 skl_disable_plane(struct intel_plane *plane,
603 const struct intel_crtc_state *crtc_state)
605 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
606 enum plane_id plane_id = plane->id;
607 enum pipe pipe = plane->pipe;
608 unsigned long irqflags;
610 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
612 skl_write_plane_wm(plane, crtc_state);
614 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
615 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
617 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
621 skl_plane_get_hw_state(struct intel_plane *plane,
624 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
625 enum intel_display_power_domain power_domain;
626 enum plane_id plane_id = plane->id;
627 intel_wakeref_t wakeref;
630 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
631 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
635 ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
639 intel_display_power_put(dev_priv, power_domain, wakeref);
645 chv_update_csc(const struct intel_plane_state *plane_state)
647 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
648 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
649 const struct drm_framebuffer *fb = plane_state->base.fb;
650 enum plane_id plane_id = plane->id;
652 * |r| | c0 c1 c2 | |cr|
653 * |g| = | c3 c4 c5 | x |y |
654 * |b| | c6 c7 c8 | |cb|
656 * Coefficients are s3.12.
658 * Cb and Cr apparently come in as signed already, and
659 * we always get full range data in on account of CLRC0/1.
661 static const s16 csc_matrix[][9] = {
662 /* BT.601 full range YCbCr -> full range RGB */
663 [DRM_COLOR_YCBCR_BT601] = {
668 /* BT.709 full range YCbCr -> full range RGB */
669 [DRM_COLOR_YCBCR_BT709] = {
675 const s16 *csc = csc_matrix[plane_state->base.color_encoding];
677 /* Seems RGB data bypasses the CSC always */
678 if (!fb->format->is_yuv)
681 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
682 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
683 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
685 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
686 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
687 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
688 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
689 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
691 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
692 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
693 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
695 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
696 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
697 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
704 vlv_update_clrc(const struct intel_plane_state *plane_state)
706 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
707 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
708 const struct drm_framebuffer *fb = plane_state->base.fb;
709 enum pipe pipe = plane->pipe;
710 enum plane_id plane_id = plane->id;
711 int contrast, brightness, sh_scale, sh_sin, sh_cos;
713 if (fb->format->is_yuv &&
714 plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
716 * Expand limited range to full range:
717 * Contrast is applied first and is used to expand Y range.
718 * Brightness is applied second and is used to remove the
719 * offset from Y. Saturation/hue is used to expand CbCr range.
721 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
722 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
723 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
724 sh_sin = SIN_0 * sh_scale;
725 sh_cos = COS_0 * sh_scale;
727 /* Pass-through everything. */
731 sh_sin = SIN_0 * sh_scale;
732 sh_cos = COS_0 * sh_scale;
735 /* FIXME these register are single buffered :( */
736 I915_WRITE_FW(SPCLRC0(pipe, plane_id),
737 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
738 I915_WRITE_FW(SPCLRC1(pipe, plane_id),
739 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
742 static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
744 return SP_GAMMA_ENABLE;
747 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
748 const struct intel_plane_state *plane_state)
750 const struct drm_framebuffer *fb = plane_state->base.fb;
751 unsigned int rotation = plane_state->base.rotation;
752 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
757 switch (fb->format->format) {
758 case DRM_FORMAT_YUYV:
759 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
761 case DRM_FORMAT_YVYU:
762 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
764 case DRM_FORMAT_UYVY:
765 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
767 case DRM_FORMAT_VYUY:
768 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
770 case DRM_FORMAT_RGB565:
771 sprctl |= SP_FORMAT_BGR565;
773 case DRM_FORMAT_XRGB8888:
774 sprctl |= SP_FORMAT_BGRX8888;
776 case DRM_FORMAT_ARGB8888:
777 sprctl |= SP_FORMAT_BGRA8888;
779 case DRM_FORMAT_XBGR2101010:
780 sprctl |= SP_FORMAT_RGBX1010102;
782 case DRM_FORMAT_ABGR2101010:
783 sprctl |= SP_FORMAT_RGBA1010102;
785 case DRM_FORMAT_XBGR8888:
786 sprctl |= SP_FORMAT_RGBX8888;
788 case DRM_FORMAT_ABGR8888:
789 sprctl |= SP_FORMAT_RGBA8888;
792 MISSING_CASE(fb->format->format);
796 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
797 sprctl |= SP_YUV_FORMAT_BT709;
799 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
802 if (rotation & DRM_MODE_ROTATE_180)
803 sprctl |= SP_ROTATE_180;
805 if (rotation & DRM_MODE_REFLECT_X)
808 if (key->flags & I915_SET_COLORKEY_SOURCE)
809 sprctl |= SP_SOURCE_KEY;
815 vlv_update_plane(struct intel_plane *plane,
816 const struct intel_crtc_state *crtc_state,
817 const struct intel_plane_state *plane_state)
819 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
820 enum pipe pipe = plane->pipe;
821 enum plane_id plane_id = plane->id;
822 u32 sprsurf_offset = plane_state->color_plane[0].offset;
824 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
825 int crtc_x = plane_state->base.dst.x1;
826 int crtc_y = plane_state->base.dst.y1;
827 u32 crtc_w = drm_rect_width(&plane_state->base.dst);
828 u32 crtc_h = drm_rect_height(&plane_state->base.dst);
829 u32 x = plane_state->color_plane[0].x;
830 u32 y = plane_state->color_plane[0].y;
831 unsigned long irqflags;
834 sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
836 /* Sizes are 0 based */
840 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
842 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
844 I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
845 plane_state->color_plane[0].stride);
846 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
847 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
848 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
850 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
851 chv_update_csc(plane_state);
854 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
855 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
856 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
859 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
860 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
863 * The control register self-arms if the plane was previously
864 * disabled. Try to make the plane enable atomic by writing
865 * the control register just before the surface register.
867 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
868 I915_WRITE_FW(SPSURF(pipe, plane_id),
869 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
871 vlv_update_clrc(plane_state);
873 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
877 vlv_disable_plane(struct intel_plane *plane,
878 const struct intel_crtc_state *crtc_state)
880 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
881 enum pipe pipe = plane->pipe;
882 enum plane_id plane_id = plane->id;
883 unsigned long irqflags;
885 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
887 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
888 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
890 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
894 vlv_plane_get_hw_state(struct intel_plane *plane,
897 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
898 enum intel_display_power_domain power_domain;
899 enum plane_id plane_id = plane->id;
900 intel_wakeref_t wakeref;
903 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
904 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
908 ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
912 intel_display_power_put(dev_priv, power_domain, wakeref);
917 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
919 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
922 sprctl |= SPRITE_GAMMA_ENABLE;
924 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
925 sprctl |= SPRITE_PIPE_CSC_ENABLE;
930 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
931 const struct intel_plane_state *plane_state)
933 struct drm_i915_private *dev_priv =
934 to_i915(plane_state->base.plane->dev);
935 const struct drm_framebuffer *fb = plane_state->base.fb;
936 unsigned int rotation = plane_state->base.rotation;
937 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
940 sprctl = SPRITE_ENABLE;
942 if (IS_IVYBRIDGE(dev_priv))
943 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
945 switch (fb->format->format) {
946 case DRM_FORMAT_XBGR8888:
947 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
949 case DRM_FORMAT_XRGB8888:
950 sprctl |= SPRITE_FORMAT_RGBX888;
952 case DRM_FORMAT_YUYV:
953 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
955 case DRM_FORMAT_YVYU:
956 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
958 case DRM_FORMAT_UYVY:
959 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
961 case DRM_FORMAT_VYUY:
962 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
965 MISSING_CASE(fb->format->format);
969 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
970 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
972 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
973 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
975 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
976 sprctl |= SPRITE_TILED;
978 if (rotation & DRM_MODE_ROTATE_180)
979 sprctl |= SPRITE_ROTATE_180;
981 if (key->flags & I915_SET_COLORKEY_DESTINATION)
982 sprctl |= SPRITE_DEST_KEY;
983 else if (key->flags & I915_SET_COLORKEY_SOURCE)
984 sprctl |= SPRITE_SOURCE_KEY;
990 ivb_update_plane(struct intel_plane *plane,
991 const struct intel_crtc_state *crtc_state,
992 const struct intel_plane_state *plane_state)
994 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
995 enum pipe pipe = plane->pipe;
996 u32 sprsurf_offset = plane_state->color_plane[0].offset;
998 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
999 int crtc_x = plane_state->base.dst.x1;
1000 int crtc_y = plane_state->base.dst.y1;
1001 u32 crtc_w = drm_rect_width(&plane_state->base.dst);
1002 u32 crtc_h = drm_rect_height(&plane_state->base.dst);
1003 u32 x = plane_state->color_plane[0].x;
1004 u32 y = plane_state->color_plane[0].y;
1005 u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
1006 u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
1007 u32 sprctl, sprscale = 0;
1008 unsigned long irqflags;
1010 sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
1012 /* Sizes are 0 based */
1018 if (crtc_w != src_w || crtc_h != src_h)
1019 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
1021 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1023 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1025 I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
1026 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
1027 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
1028 if (IS_IVYBRIDGE(dev_priv))
1029 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
1032 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
1033 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
1034 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
1037 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
1039 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1040 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
1042 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
1043 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
1047 * The control register self-arms if the plane was previously
1048 * disabled. Try to make the plane enable atomic by writing
1049 * the control register just before the surface register.
1051 I915_WRITE_FW(SPRCTL(pipe), sprctl);
1052 I915_WRITE_FW(SPRSURF(pipe),
1053 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
1055 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1059 ivb_disable_plane(struct intel_plane *plane,
1060 const struct intel_crtc_state *crtc_state)
1062 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1063 enum pipe pipe = plane->pipe;
1064 unsigned long irqflags;
1066 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1068 I915_WRITE_FW(SPRCTL(pipe), 0);
1069 /* Disable the scaler */
1070 if (IS_IVYBRIDGE(dev_priv))
1071 I915_WRITE_FW(SPRSCALE(pipe), 0);
1072 I915_WRITE_FW(SPRSURF(pipe), 0);
1074 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1078 ivb_plane_get_hw_state(struct intel_plane *plane,
1081 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1082 enum intel_display_power_domain power_domain;
1083 intel_wakeref_t wakeref;
1086 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1087 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1091 ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
1093 *pipe = plane->pipe;
1095 intel_display_power_put(dev_priv, power_domain, wakeref);
1101 g4x_sprite_max_stride(struct intel_plane *plane,
1102 u32 pixel_format, u64 modifier,
1103 unsigned int rotation)
1108 static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
1110 return DVS_GAMMA_ENABLE;
1113 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
1114 const struct intel_plane_state *plane_state)
1116 struct drm_i915_private *dev_priv =
1117 to_i915(plane_state->base.plane->dev);
1118 const struct drm_framebuffer *fb = plane_state->base.fb;
1119 unsigned int rotation = plane_state->base.rotation;
1120 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1123 dvscntr = DVS_ENABLE;
1125 if (IS_GEN(dev_priv, 6))
1126 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
1128 switch (fb->format->format) {
1129 case DRM_FORMAT_XBGR8888:
1130 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
1132 case DRM_FORMAT_XRGB8888:
1133 dvscntr |= DVS_FORMAT_RGBX888;
1135 case DRM_FORMAT_YUYV:
1136 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
1138 case DRM_FORMAT_YVYU:
1139 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
1141 case DRM_FORMAT_UYVY:
1142 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
1144 case DRM_FORMAT_VYUY:
1145 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
1148 MISSING_CASE(fb->format->format);
1152 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
1153 dvscntr |= DVS_YUV_FORMAT_BT709;
1155 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1156 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
1158 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1159 dvscntr |= DVS_TILED;
1161 if (rotation & DRM_MODE_ROTATE_180)
1162 dvscntr |= DVS_ROTATE_180;
1164 if (key->flags & I915_SET_COLORKEY_DESTINATION)
1165 dvscntr |= DVS_DEST_KEY;
1166 else if (key->flags & I915_SET_COLORKEY_SOURCE)
1167 dvscntr |= DVS_SOURCE_KEY;
1173 g4x_update_plane(struct intel_plane *plane,
1174 const struct intel_crtc_state *crtc_state,
1175 const struct intel_plane_state *plane_state)
1177 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1178 enum pipe pipe = plane->pipe;
1179 u32 dvssurf_offset = plane_state->color_plane[0].offset;
1181 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1182 int crtc_x = plane_state->base.dst.x1;
1183 int crtc_y = plane_state->base.dst.y1;
1184 u32 crtc_w = drm_rect_width(&plane_state->base.dst);
1185 u32 crtc_h = drm_rect_height(&plane_state->base.dst);
1186 u32 x = plane_state->color_plane[0].x;
1187 u32 y = plane_state->color_plane[0].y;
1188 u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
1189 u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
1190 u32 dvscntr, dvsscale = 0;
1191 unsigned long irqflags;
1193 dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
1195 /* Sizes are 0 based */
1201 if (crtc_w != src_w || crtc_h != src_h)
1202 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
1204 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1206 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1208 I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
1209 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
1210 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
1211 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
1214 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
1215 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
1216 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
1219 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
1220 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
1223 * The control register self-arms if the plane was previously
1224 * disabled. Try to make the plane enable atomic by writing
1225 * the control register just before the surface register.
1227 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
1228 I915_WRITE_FW(DVSSURF(pipe),
1229 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
1231 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1235 g4x_disable_plane(struct intel_plane *plane,
1236 const struct intel_crtc_state *crtc_state)
1238 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1239 enum pipe pipe = plane->pipe;
1240 unsigned long irqflags;
1242 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1244 I915_WRITE_FW(DVSCNTR(pipe), 0);
1245 /* Disable the scaler */
1246 I915_WRITE_FW(DVSSCALE(pipe), 0);
1247 I915_WRITE_FW(DVSSURF(pipe), 0);
1249 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1253 g4x_plane_get_hw_state(struct intel_plane *plane,
1256 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1257 enum intel_display_power_domain power_domain;
1258 intel_wakeref_t wakeref;
1261 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1262 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1266 ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
1268 *pipe = plane->pipe;
1270 intel_display_power_put(dev_priv, power_domain, wakeref);
1275 static bool intel_fb_scalable(const struct drm_framebuffer *fb)
1280 switch (fb->format->format) {
1289 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
1290 struct intel_plane_state *plane_state)
1292 const struct drm_framebuffer *fb = plane_state->base.fb;
1293 const struct drm_rect *src = &plane_state->base.src;
1294 const struct drm_rect *dst = &plane_state->base.dst;
1295 int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
1296 const struct drm_display_mode *adjusted_mode =
1297 &crtc_state->base.adjusted_mode;
1298 unsigned int cpp = fb->format->cpp[0];
1299 unsigned int width_bytes;
1300 int min_width, min_height;
1302 crtc_w = drm_rect_width(dst);
1303 crtc_h = drm_rect_height(dst);
1305 src_x = src->x1 >> 16;
1306 src_y = src->y1 >> 16;
1307 src_w = drm_rect_width(src) >> 16;
1308 src_h = drm_rect_height(src) >> 16;
1310 if (src_w == crtc_w && src_h == crtc_h)
1315 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1317 DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
1325 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1327 if (src_w < min_width || src_h < min_height ||
1328 src_w > 2048 || src_h > 2048) {
1329 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1330 src_w, src_h, min_width, min_height, 2048, 2048);
1334 if (width_bytes > 4096) {
1335 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1340 if (width_bytes > 4096 || fb->pitches[0] > 4096) {
1341 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1342 fb->pitches[0], 4096);
1350 g4x_sprite_check(struct intel_crtc_state *crtc_state,
1351 struct intel_plane_state *plane_state)
1353 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1354 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1355 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
1356 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1359 if (intel_fb_scalable(plane_state->base.fb)) {
1360 if (INTEL_GEN(dev_priv) < 7) {
1362 max_scale = 16 << 16;
1363 } else if (IS_IVYBRIDGE(dev_priv)) {
1365 max_scale = 2 << 16;
1369 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1371 min_scale, max_scale,
1376 if (!plane_state->base.visible)
1379 ret = intel_plane_check_src_coordinates(plane_state);
1383 ret = g4x_sprite_check_scaling(crtc_state, plane_state);
1387 ret = i9xx_check_plane_surface(plane_state);
1391 if (INTEL_GEN(dev_priv) >= 7)
1392 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
1394 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
1399 int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
1401 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1402 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1403 unsigned int rotation = plane_state->base.rotation;
1405 /* CHV ignores the mirror bit when the rotate bit is set :( */
1406 if (IS_CHERRYVIEW(dev_priv) &&
1407 rotation & DRM_MODE_ROTATE_180 &&
1408 rotation & DRM_MODE_REFLECT_X) {
1409 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
1417 vlv_sprite_check(struct intel_crtc_state *crtc_state,
1418 struct intel_plane_state *plane_state)
1422 ret = chv_plane_check_rotation(plane_state);
1426 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1428 DRM_PLANE_HELPER_NO_SCALING,
1429 DRM_PLANE_HELPER_NO_SCALING,
1434 if (!plane_state->base.visible)
1437 ret = intel_plane_check_src_coordinates(plane_state);
1441 ret = i9xx_check_plane_surface(plane_state);
1445 plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
1450 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1451 const struct intel_plane_state *plane_state)
1453 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1454 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1455 const struct drm_framebuffer *fb = plane_state->base.fb;
1456 unsigned int rotation = plane_state->base.rotation;
1457 struct drm_format_name_buf format_name;
1462 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1463 is_ccs_modifier(fb->modifier)) {
1464 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
1469 if (rotation & DRM_MODE_REFLECT_X &&
1470 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1471 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
1475 if (drm_rotation_90_or_270(rotation)) {
1476 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
1477 fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
1478 DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
1483 * 90/270 is not allowed with RGB64 16:16:16:16 and
1484 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
1485 * TBD: Add RGB64 case once its added in supported format
1488 switch (fb->format->format) {
1489 case DRM_FORMAT_RGB565:
1490 if (INTEL_GEN(dev_priv) >= 11)
1494 DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
1495 drm_get_format_name(fb->format->format,
1503 /* Y-tiling is not supported in IF-ID Interlace mode */
1504 if (crtc_state->base.enable &&
1505 crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1506 (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
1507 fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
1508 fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1509 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
1510 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
1517 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1518 const struct intel_plane_state *plane_state)
1520 struct drm_i915_private *dev_priv =
1521 to_i915(plane_state->base.plane->dev);
1522 int crtc_x = plane_state->base.dst.x1;
1523 int crtc_w = drm_rect_width(&plane_state->base.dst);
1524 int pipe_src_w = crtc_state->pipe_src_w;
1527 * Display WA #1175: cnl,glk
1528 * Planes other than the cursor may cause FIFO underflow and display
1529 * corruption if starting less than 4 pixels from the right edge of
1531 * Besides the above WA fix the similar problem, where planes other
1532 * than the cursor ending less than 4 pixels from the left edge of the
1533 * screen may cause FIFO underflow and display corruption.
1535 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
1536 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1537 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
1538 crtc_x + crtc_w < 4 ? "end" : "start",
1539 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1547 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
1549 const struct drm_framebuffer *fb = plane_state->base.fb;
1550 unsigned int rotation = plane_state->base.rotation;
1551 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
1553 /* Display WA #1106 */
1554 if (fb->format->format == DRM_FORMAT_NV12 && src_w & 3 &&
1555 (rotation == DRM_MODE_ROTATE_270 ||
1556 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
1557 DRM_DEBUG_KMS("src width must be multiple of 4 for rotated NV12\n");
1564 static int skl_plane_check(struct intel_crtc_state *crtc_state,
1565 struct intel_plane_state *plane_state)
1567 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1568 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1569 const struct drm_framebuffer *fb = plane_state->base.fb;
1570 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
1571 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1574 ret = skl_plane_check_fb(crtc_state, plane_state);
1578 /* use scaler when colorkey is not required */
1579 if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
1581 max_scale = skl_max_scale(crtc_state, fb->format->format);
1584 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1586 min_scale, max_scale,
1591 if (!plane_state->base.visible)
1594 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1598 ret = intel_plane_check_src_coordinates(plane_state);
1602 ret = skl_plane_check_nv12_rotation(plane_state);
1606 ret = skl_check_plane_surface(plane_state);
1610 /* HW only has 8 bits pixel precision, disable plane if invisible */
1611 if (!(plane_state->base.alpha >> 8))
1612 plane_state->base.visible = false;
1614 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1616 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1617 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1623 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
1625 return INTEL_GEN(dev_priv) >= 9;
1628 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
1629 const struct drm_intel_sprite_colorkey *set)
1631 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1632 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1633 struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1638 * We want src key enabled on the
1639 * sprite and not on the primary.
1641 if (plane->id == PLANE_PRIMARY &&
1642 set->flags & I915_SET_COLORKEY_SOURCE)
1646 * On SKL+ we want dst key enabled on
1647 * the primary and not on the sprite.
1649 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
1650 set->flags & I915_SET_COLORKEY_DESTINATION)
1654 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1655 struct drm_file *file_priv)
1657 struct drm_i915_private *dev_priv = to_i915(dev);
1658 struct drm_intel_sprite_colorkey *set = data;
1659 struct drm_plane *plane;
1660 struct drm_plane_state *plane_state;
1661 struct drm_atomic_state *state;
1662 struct drm_modeset_acquire_ctx ctx;
1665 /* ignore the pointless "none" flag */
1666 set->flags &= ~I915_SET_COLORKEY_NONE;
1668 if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1671 /* Make sure we don't try to enable both src & dest simultaneously */
1672 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1675 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1676 set->flags & I915_SET_COLORKEY_DESTINATION)
1679 plane = drm_plane_find(dev, file_priv, set->plane_id);
1680 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1684 * SKL+ only plane 2 can do destination keying against plane 1.
1685 * Also multiple planes can't do destination keying on the same
1686 * pipe simultaneously.
1688 if (INTEL_GEN(dev_priv) >= 9 &&
1689 to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
1690 set->flags & I915_SET_COLORKEY_DESTINATION)
1693 drm_modeset_acquire_init(&ctx, 0);
1695 state = drm_atomic_state_alloc(plane->dev);
1700 state->acquire_ctx = &ctx;
1703 plane_state = drm_atomic_get_plane_state(state, plane);
1704 ret = PTR_ERR_OR_ZERO(plane_state);
1706 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1709 * On some platforms we have to configure
1710 * the dst colorkey on the primary plane.
1712 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
1713 struct intel_crtc *crtc =
1714 intel_get_crtc_for_pipe(dev_priv,
1715 to_intel_plane(plane)->pipe);
1717 plane_state = drm_atomic_get_plane_state(state,
1718 crtc->base.primary);
1719 ret = PTR_ERR_OR_ZERO(plane_state);
1721 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1725 ret = drm_atomic_commit(state);
1727 if (ret != -EDEADLK)
1730 drm_atomic_state_clear(state);
1731 drm_modeset_backoff(&ctx);
1734 drm_atomic_state_put(state);
1736 drm_modeset_drop_locks(&ctx);
1737 drm_modeset_acquire_fini(&ctx);
1741 static const u32 g4x_plane_formats[] = {
1742 DRM_FORMAT_XRGB8888,
1749 static const u64 i9xx_plane_format_modifiers[] = {
1750 I915_FORMAT_MOD_X_TILED,
1751 DRM_FORMAT_MOD_LINEAR,
1752 DRM_FORMAT_MOD_INVALID
1755 static const u32 snb_plane_formats[] = {
1756 DRM_FORMAT_XBGR8888,
1757 DRM_FORMAT_XRGB8888,
1764 static const u32 vlv_plane_formats[] = {
1766 DRM_FORMAT_ABGR8888,
1767 DRM_FORMAT_ARGB8888,
1768 DRM_FORMAT_XBGR8888,
1769 DRM_FORMAT_XRGB8888,
1770 DRM_FORMAT_XBGR2101010,
1771 DRM_FORMAT_ABGR2101010,
1778 static const u32 skl_plane_formats[] = {
1781 DRM_FORMAT_XRGB8888,
1782 DRM_FORMAT_XBGR8888,
1783 DRM_FORMAT_ARGB8888,
1784 DRM_FORMAT_ABGR8888,
1785 DRM_FORMAT_XRGB2101010,
1786 DRM_FORMAT_XBGR2101010,
1793 static const u32 skl_planar_formats[] = {
1796 DRM_FORMAT_XRGB8888,
1797 DRM_FORMAT_XBGR8888,
1798 DRM_FORMAT_ARGB8888,
1799 DRM_FORMAT_ABGR8888,
1800 DRM_FORMAT_XRGB2101010,
1801 DRM_FORMAT_XBGR2101010,
1809 static const u64 skl_plane_format_modifiers_noccs[] = {
1810 I915_FORMAT_MOD_Yf_TILED,
1811 I915_FORMAT_MOD_Y_TILED,
1812 I915_FORMAT_MOD_X_TILED,
1813 DRM_FORMAT_MOD_LINEAR,
1814 DRM_FORMAT_MOD_INVALID
1817 static const u64 skl_plane_format_modifiers_ccs[] = {
1818 I915_FORMAT_MOD_Yf_TILED_CCS,
1819 I915_FORMAT_MOD_Y_TILED_CCS,
1820 I915_FORMAT_MOD_Yf_TILED,
1821 I915_FORMAT_MOD_Y_TILED,
1822 I915_FORMAT_MOD_X_TILED,
1823 DRM_FORMAT_MOD_LINEAR,
1824 DRM_FORMAT_MOD_INVALID
1827 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
1828 u32 format, u64 modifier)
1831 case DRM_FORMAT_MOD_LINEAR:
1832 case I915_FORMAT_MOD_X_TILED:
1839 case DRM_FORMAT_XRGB8888:
1840 case DRM_FORMAT_YUYV:
1841 case DRM_FORMAT_YVYU:
1842 case DRM_FORMAT_UYVY:
1843 case DRM_FORMAT_VYUY:
1844 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1845 modifier == I915_FORMAT_MOD_X_TILED)
1853 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
1854 u32 format, u64 modifier)
1857 case DRM_FORMAT_MOD_LINEAR:
1858 case I915_FORMAT_MOD_X_TILED:
1865 case DRM_FORMAT_XRGB8888:
1866 case DRM_FORMAT_XBGR8888:
1867 case DRM_FORMAT_YUYV:
1868 case DRM_FORMAT_YVYU:
1869 case DRM_FORMAT_UYVY:
1870 case DRM_FORMAT_VYUY:
1871 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1872 modifier == I915_FORMAT_MOD_X_TILED)
1880 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
1881 u32 format, u64 modifier)
1884 case DRM_FORMAT_MOD_LINEAR:
1885 case I915_FORMAT_MOD_X_TILED:
1892 case DRM_FORMAT_RGB565:
1893 case DRM_FORMAT_ABGR8888:
1894 case DRM_FORMAT_ARGB8888:
1895 case DRM_FORMAT_XBGR8888:
1896 case DRM_FORMAT_XRGB8888:
1897 case DRM_FORMAT_XBGR2101010:
1898 case DRM_FORMAT_ABGR2101010:
1899 case DRM_FORMAT_YUYV:
1900 case DRM_FORMAT_YVYU:
1901 case DRM_FORMAT_UYVY:
1902 case DRM_FORMAT_VYUY:
1903 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1904 modifier == I915_FORMAT_MOD_X_TILED)
1912 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1913 u32 format, u64 modifier)
1915 struct intel_plane *plane = to_intel_plane(_plane);
1918 case DRM_FORMAT_MOD_LINEAR:
1919 case I915_FORMAT_MOD_X_TILED:
1920 case I915_FORMAT_MOD_Y_TILED:
1921 case I915_FORMAT_MOD_Yf_TILED:
1923 case I915_FORMAT_MOD_Y_TILED_CCS:
1924 case I915_FORMAT_MOD_Yf_TILED_CCS:
1925 if (!plane->has_ccs)
1933 case DRM_FORMAT_XRGB8888:
1934 case DRM_FORMAT_XBGR8888:
1935 case DRM_FORMAT_ARGB8888:
1936 case DRM_FORMAT_ABGR8888:
1937 if (is_ccs_modifier(modifier))
1940 case DRM_FORMAT_RGB565:
1941 case DRM_FORMAT_XRGB2101010:
1942 case DRM_FORMAT_XBGR2101010:
1943 case DRM_FORMAT_YUYV:
1944 case DRM_FORMAT_YVYU:
1945 case DRM_FORMAT_UYVY:
1946 case DRM_FORMAT_VYUY:
1947 case DRM_FORMAT_NV12:
1948 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1952 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1953 modifier == I915_FORMAT_MOD_X_TILED ||
1954 modifier == I915_FORMAT_MOD_Y_TILED)
1962 static const struct drm_plane_funcs g4x_sprite_funcs = {
1963 .update_plane = drm_atomic_helper_update_plane,
1964 .disable_plane = drm_atomic_helper_disable_plane,
1965 .destroy = intel_plane_destroy,
1966 .atomic_get_property = intel_plane_atomic_get_property,
1967 .atomic_set_property = intel_plane_atomic_set_property,
1968 .atomic_duplicate_state = intel_plane_duplicate_state,
1969 .atomic_destroy_state = intel_plane_destroy_state,
1970 .format_mod_supported = g4x_sprite_format_mod_supported,
1973 static const struct drm_plane_funcs snb_sprite_funcs = {
1974 .update_plane = drm_atomic_helper_update_plane,
1975 .disable_plane = drm_atomic_helper_disable_plane,
1976 .destroy = intel_plane_destroy,
1977 .atomic_get_property = intel_plane_atomic_get_property,
1978 .atomic_set_property = intel_plane_atomic_set_property,
1979 .atomic_duplicate_state = intel_plane_duplicate_state,
1980 .atomic_destroy_state = intel_plane_destroy_state,
1981 .format_mod_supported = snb_sprite_format_mod_supported,
1984 static const struct drm_plane_funcs vlv_sprite_funcs = {
1985 .update_plane = drm_atomic_helper_update_plane,
1986 .disable_plane = drm_atomic_helper_disable_plane,
1987 .destroy = intel_plane_destroy,
1988 .atomic_get_property = intel_plane_atomic_get_property,
1989 .atomic_set_property = intel_plane_atomic_set_property,
1990 .atomic_duplicate_state = intel_plane_duplicate_state,
1991 .atomic_destroy_state = intel_plane_destroy_state,
1992 .format_mod_supported = vlv_sprite_format_mod_supported,
1995 static const struct drm_plane_funcs skl_plane_funcs = {
1996 .update_plane = drm_atomic_helper_update_plane,
1997 .disable_plane = drm_atomic_helper_disable_plane,
1998 .destroy = intel_plane_destroy,
1999 .atomic_get_property = intel_plane_atomic_get_property,
2000 .atomic_set_property = intel_plane_atomic_set_property,
2001 .atomic_duplicate_state = intel_plane_duplicate_state,
2002 .atomic_destroy_state = intel_plane_destroy_state,
2003 .format_mod_supported = skl_plane_format_mod_supported,
2006 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
2007 enum pipe pipe, enum plane_id plane_id)
2009 if (!HAS_FBC(dev_priv))
2012 return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
2015 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2016 enum pipe pipe, enum plane_id plane_id)
2018 if (INTEL_GEN(dev_priv) >= 11)
2019 return plane_id <= PLANE_SPRITE3;
2021 /* Display WA #0870: skl, bxt */
2022 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
2025 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
2028 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
2034 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2035 enum pipe pipe, enum plane_id plane_id)
2037 if (plane_id == PLANE_CURSOR)
2040 if (INTEL_GEN(dev_priv) >= 10)
2043 if (IS_GEMINILAKE(dev_priv))
2044 return pipe != PIPE_C;
2046 return pipe != PIPE_C &&
2047 (plane_id == PLANE_PRIMARY ||
2048 plane_id == PLANE_SPRITE0);
2051 struct intel_plane *
2052 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2053 enum pipe pipe, enum plane_id plane_id)
2055 struct intel_plane *plane;
2056 enum drm_plane_type plane_type;
2057 unsigned int supported_rotations;
2058 unsigned int possible_crtcs;
2059 const u64 *modifiers;
2064 plane = intel_plane_alloc();
2069 plane->id = plane_id;
2070 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
2072 plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id);
2073 if (plane->has_fbc) {
2074 struct intel_fbc *fbc = &dev_priv->fbc;
2076 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
2079 plane->max_stride = skl_plane_max_stride;
2080 plane->update_plane = skl_update_plane;
2081 plane->disable_plane = skl_disable_plane;
2082 plane->get_hw_state = skl_plane_get_hw_state;
2083 plane->check_plane = skl_plane_check;
2084 if (icl_is_nv12_y_plane(plane_id))
2085 plane->update_slave = icl_update_slave;
2087 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2088 formats = skl_planar_formats;
2089 num_formats = ARRAY_SIZE(skl_planar_formats);
2091 formats = skl_plane_formats;
2092 num_formats = ARRAY_SIZE(skl_plane_formats);
2095 plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
2097 modifiers = skl_plane_format_modifiers_ccs;
2099 modifiers = skl_plane_format_modifiers_noccs;
2101 if (plane_id == PLANE_PRIMARY)
2102 plane_type = DRM_PLANE_TYPE_PRIMARY;
2104 plane_type = DRM_PLANE_TYPE_OVERLAY;
2106 possible_crtcs = BIT(pipe);
2108 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2109 possible_crtcs, &skl_plane_funcs,
2110 formats, num_formats, modifiers,
2112 "plane %d%c", plane_id + 1,
2117 supported_rotations =
2118 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
2119 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
2121 if (INTEL_GEN(dev_priv) >= 10)
2122 supported_rotations |= DRM_MODE_REFLECT_X;
2124 drm_plane_create_rotation_property(&plane->base,
2126 supported_rotations);
2128 drm_plane_create_color_properties(&plane->base,
2129 BIT(DRM_COLOR_YCBCR_BT601) |
2130 BIT(DRM_COLOR_YCBCR_BT709),
2131 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2132 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2133 DRM_COLOR_YCBCR_BT709,
2134 DRM_COLOR_YCBCR_LIMITED_RANGE);
2136 drm_plane_create_alpha_property(&plane->base);
2137 drm_plane_create_blend_mode_property(&plane->base,
2138 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2139 BIT(DRM_MODE_BLEND_PREMULTI) |
2140 BIT(DRM_MODE_BLEND_COVERAGE));
2142 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
2147 intel_plane_free(plane);
2149 return ERR_PTR(ret);
2152 struct intel_plane *
2153 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2154 enum pipe pipe, int sprite)
2156 struct intel_plane *plane;
2157 const struct drm_plane_funcs *plane_funcs;
2158 unsigned long possible_crtcs;
2159 unsigned int supported_rotations;
2160 const u64 *modifiers;
2165 if (INTEL_GEN(dev_priv) >= 9)
2166 return skl_universal_plane_create(dev_priv, pipe,
2167 PLANE_SPRITE0 + sprite);
2169 plane = intel_plane_alloc();
2173 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2174 plane->max_stride = i9xx_plane_max_stride;
2175 plane->update_plane = vlv_update_plane;
2176 plane->disable_plane = vlv_disable_plane;
2177 plane->get_hw_state = vlv_plane_get_hw_state;
2178 plane->check_plane = vlv_sprite_check;
2180 formats = vlv_plane_formats;
2181 num_formats = ARRAY_SIZE(vlv_plane_formats);
2182 modifiers = i9xx_plane_format_modifiers;
2184 plane_funcs = &vlv_sprite_funcs;
2185 } else if (INTEL_GEN(dev_priv) >= 7) {
2186 plane->max_stride = g4x_sprite_max_stride;
2187 plane->update_plane = ivb_update_plane;
2188 plane->disable_plane = ivb_disable_plane;
2189 plane->get_hw_state = ivb_plane_get_hw_state;
2190 plane->check_plane = g4x_sprite_check;
2192 formats = snb_plane_formats;
2193 num_formats = ARRAY_SIZE(snb_plane_formats);
2194 modifiers = i9xx_plane_format_modifiers;
2196 plane_funcs = &snb_sprite_funcs;
2198 plane->max_stride = g4x_sprite_max_stride;
2199 plane->update_plane = g4x_update_plane;
2200 plane->disable_plane = g4x_disable_plane;
2201 plane->get_hw_state = g4x_plane_get_hw_state;
2202 plane->check_plane = g4x_sprite_check;
2204 modifiers = i9xx_plane_format_modifiers;
2205 if (IS_GEN(dev_priv, 6)) {
2206 formats = snb_plane_formats;
2207 num_formats = ARRAY_SIZE(snb_plane_formats);
2209 plane_funcs = &snb_sprite_funcs;
2211 formats = g4x_plane_formats;
2212 num_formats = ARRAY_SIZE(g4x_plane_formats);
2214 plane_funcs = &g4x_sprite_funcs;
2218 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2219 supported_rotations =
2220 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
2223 supported_rotations =
2224 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
2228 plane->id = PLANE_SPRITE0 + sprite;
2229 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
2231 possible_crtcs = BIT(pipe);
2233 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2234 possible_crtcs, plane_funcs,
2235 formats, num_formats, modifiers,
2236 DRM_PLANE_TYPE_OVERLAY,
2237 "sprite %c", sprite_name(pipe, sprite));
2241 drm_plane_create_rotation_property(&plane->base,
2243 supported_rotations);
2245 drm_plane_create_color_properties(&plane->base,
2246 BIT(DRM_COLOR_YCBCR_BT601) |
2247 BIT(DRM_COLOR_YCBCR_BT709),
2248 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2249 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2250 DRM_COLOR_YCBCR_BT709,
2251 DRM_COLOR_YCBCR_LIMITED_RANGE);
2253 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
2258 intel_plane_free(plane);
2260 return ERR_PTR(ret);