2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
34 static const char * const forcewake_domain_names[] = {
41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
45 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
46 return forcewake_domain_names[id];
54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
56 WARN_ON(!i915_mmio_reg_valid(d->reg_set));
57 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
64 hrtimer_start_range_ns(&d->timer,
71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
73 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
74 FORCEWAKE_KERNEL) == 0,
75 FORCEWAKE_ACK_TIMEOUT_MS))
76 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
77 intel_uncore_forcewake_domain_to_str(d->id));
81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
83 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
89 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
91 FORCEWAKE_ACK_TIMEOUT_MS))
92 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
93 intel_uncore_forcewake_domain_to_str(d->id));
97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
99 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
105 /* something from same cacheline, but not from the set register */
106 if (i915_mmio_reg_valid(d->reg_post))
107 __raw_posting_read(d->i915, d->reg_post);
111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
113 struct intel_uncore_forcewake_domain *d;
115 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
116 fw_domain_wait_ack_clear(d);
120 for_each_fw_domain_masked(d, fw_domains, dev_priv)
121 fw_domain_wait_ack(d);
125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
127 struct intel_uncore_forcewake_domain *d;
129 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
131 fw_domain_posting_read(d);
136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
138 struct intel_uncore_forcewake_domain *d;
140 /* No need to do for all, just do for first found */
141 for_each_fw_domain(d, dev_priv) {
142 fw_domain_posting_read(d);
148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
150 struct intel_uncore_forcewake_domain *d;
152 if (dev_priv->uncore.fw_domains == 0)
155 for_each_fw_domain_masked(d, fw_domains, dev_priv)
158 fw_domains_posting_read(dev_priv);
161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
163 /* w/a for a sporadic read returning 0 by waiting for the GT
166 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
167 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
168 DRM_ERROR("GT thread status wait timed out\n");
171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
172 enum forcewake_domains fw_domains)
174 fw_domains_get(dev_priv, fw_domains);
176 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
177 __gen6_gt_wait_for_thread_c0(dev_priv);
180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
184 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
185 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
186 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
190 enum forcewake_domains fw_domains)
192 fw_domains_put(dev_priv, fw_domains);
193 gen6_gt_check_fifodbg(dev_priv);
196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
198 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
200 return count & GT_FIFO_FREE_ENTRIES_MASK;
203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
207 /* On VLV, FIFO will be shared by both SW and HW.
208 * So, we need to read the FREE_ENTRIES everytime */
209 if (IS_VALLEYVIEW(dev_priv))
210 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
212 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
214 u32 fifo = fifo_free_entries(dev_priv);
216 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
218 fifo = fifo_free_entries(dev_priv);
220 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
222 dev_priv->uncore.fifo_count = fifo;
224 dev_priv->uncore.fifo_count--;
229 static enum hrtimer_restart
230 intel_uncore_fw_release_timer(struct hrtimer *timer)
232 struct intel_uncore_forcewake_domain *domain =
233 container_of(timer, struct intel_uncore_forcewake_domain, timer);
234 struct drm_i915_private *dev_priv = domain->i915;
235 unsigned long irqflags;
237 assert_rpm_device_not_suspended(dev_priv);
239 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
240 if (WARN_ON(domain->wake_count == 0))
241 domain->wake_count++;
243 if (--domain->wake_count == 0) {
244 dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
245 dev_priv->uncore.fw_domains_active &= ~domain->mask;
248 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
250 return HRTIMER_NORESTART;
253 void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
256 unsigned long irqflags;
257 struct intel_uncore_forcewake_domain *domain;
258 int retry_count = 100;
259 enum forcewake_domains fw, active_domains;
261 /* Hold uncore.lock across reset to prevent any register access
262 * with forcewake not set correctly. Wait until all pending
263 * timers are run before holding.
268 for_each_fw_domain(domain, dev_priv) {
269 if (hrtimer_cancel(&domain->timer) == 0)
272 intel_uncore_fw_release_timer(&domain->timer);
275 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
277 for_each_fw_domain(domain, dev_priv) {
278 if (hrtimer_active(&domain->timer))
279 active_domains |= domain->mask;
282 if (active_domains == 0)
285 if (--retry_count == 0) {
286 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
290 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
294 WARN_ON(active_domains);
296 fw = dev_priv->uncore.fw_domains_active;
298 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
300 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
302 if (restore) { /* If reset with a user forcewake, try to restore */
304 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
306 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
307 dev_priv->uncore.fifo_count =
308 fifo_free_entries(dev_priv);
312 assert_forcewakes_inactive(dev_priv);
314 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
317 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
319 const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
320 const unsigned int sets[4] = { 1, 1, 2, 2 };
321 const u32 cap = dev_priv->edram_cap;
323 return EDRAM_NUM_BANKS(cap) *
324 ways[EDRAM_WAYS_IDX(cap)] *
325 sets[EDRAM_SETS_IDX(cap)] *
329 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
331 if (!HAS_EDRAM(dev_priv))
334 /* The needed capability bits for size calculation
335 * are not there with pre gen9 so return 128MB always.
337 if (INTEL_GEN(dev_priv) < 9)
338 return 128 * 1024 * 1024;
340 return gen9_edram_size(dev_priv);
343 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
345 if (IS_HASWELL(dev_priv) ||
346 IS_BROADWELL(dev_priv) ||
347 INTEL_GEN(dev_priv) >= 9) {
348 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
351 /* NB: We can't write IDICR yet because we do not have gt funcs
354 dev_priv->edram_cap = 0;
357 if (HAS_EDRAM(dev_priv))
358 DRM_INFO("Found %lluMB of eDRAM\n",
359 intel_uncore_edram_size(dev_priv) / (1024 * 1024));
363 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
367 dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
368 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
371 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
377 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
381 cer = __raw_i915_read32(dev_priv, CLAIM_ER);
382 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
385 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
391 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
393 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
394 return fpga_check_for_unclaimed_mmio(dev_priv);
396 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
397 return vlv_check_for_unclaimed_mmio(dev_priv);
402 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
403 bool restore_forcewake)
405 struct intel_device_info *info = mkwrite_device_info(dev_priv);
407 /* clear out unclaimed reg detection bit */
408 if (check_for_unclaimed_mmio(dev_priv))
409 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
411 /* clear out old GT FIFO errors */
412 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
413 __raw_i915_write32(dev_priv, GTFIFODBG,
414 __raw_i915_read32(dev_priv, GTFIFODBG));
416 /* WaDisableShadowRegForCpd:chv */
417 if (IS_CHERRYVIEW(dev_priv)) {
418 __raw_i915_write32(dev_priv, GTFIFOCTL,
419 __raw_i915_read32(dev_priv, GTFIFOCTL) |
420 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
421 GT_FIFO_CTL_RC6_POLICY_STALL);
424 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST))
425 info->has_decoupled_mmio = false;
427 intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
430 void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
431 bool restore_forcewake)
433 __intel_uncore_early_sanitize(dev_priv, restore_forcewake);
434 i915_check_and_clear_faults(dev_priv);
437 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
439 i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
441 /* BIOS often leaves RC6 enabled, but disable it for hw init */
442 intel_sanitize_gt_powersave(dev_priv);
445 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
446 enum forcewake_domains fw_domains)
448 struct intel_uncore_forcewake_domain *domain;
450 fw_domains &= dev_priv->uncore.fw_domains;
452 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
453 if (domain->wake_count++)
454 fw_domains &= ~domain->mask;
458 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
459 dev_priv->uncore.fw_domains_active |= fw_domains;
464 * intel_uncore_forcewake_get - grab forcewake domain references
465 * @dev_priv: i915 device instance
466 * @fw_domains: forcewake domains to get reference on
468 * This function can be used get GT's forcewake domain references.
469 * Normal register access will handle the forcewake domains automatically.
470 * However if some sequence requires the GT to not power down a particular
471 * forcewake domains this function should be called at the beginning of the
472 * sequence. And subsequently the reference should be dropped by symmetric
473 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
474 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
476 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
477 enum forcewake_domains fw_domains)
479 unsigned long irqflags;
481 if (!dev_priv->uncore.funcs.force_wake_get)
484 assert_rpm_wakelock_held(dev_priv);
486 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
487 __intel_uncore_forcewake_get(dev_priv, fw_domains);
488 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
492 * intel_uncore_forcewake_get__locked - grab forcewake domain references
493 * @dev_priv: i915 device instance
494 * @fw_domains: forcewake domains to get reference on
496 * See intel_uncore_forcewake_get(). This variant places the onus
497 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
499 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
500 enum forcewake_domains fw_domains)
502 assert_spin_locked(&dev_priv->uncore.lock);
504 if (!dev_priv->uncore.funcs.force_wake_get)
507 __intel_uncore_forcewake_get(dev_priv, fw_domains);
510 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
511 enum forcewake_domains fw_domains)
513 struct intel_uncore_forcewake_domain *domain;
515 fw_domains &= dev_priv->uncore.fw_domains;
517 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
518 if (WARN_ON(domain->wake_count == 0))
521 if (--domain->wake_count)
524 fw_domain_arm_timer(domain);
529 * intel_uncore_forcewake_put - release a forcewake domain reference
530 * @dev_priv: i915 device instance
531 * @fw_domains: forcewake domains to put references
533 * This function drops the device-level forcewakes for specified
534 * domains obtained by intel_uncore_forcewake_get().
536 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
537 enum forcewake_domains fw_domains)
539 unsigned long irqflags;
541 if (!dev_priv->uncore.funcs.force_wake_put)
544 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
545 __intel_uncore_forcewake_put(dev_priv, fw_domains);
546 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
550 * intel_uncore_forcewake_put__locked - grab forcewake domain references
551 * @dev_priv: i915 device instance
552 * @fw_domains: forcewake domains to get reference on
554 * See intel_uncore_forcewake_put(). This variant places the onus
555 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
557 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
558 enum forcewake_domains fw_domains)
560 assert_spin_locked(&dev_priv->uncore.lock);
562 if (!dev_priv->uncore.funcs.force_wake_put)
565 __intel_uncore_forcewake_put(dev_priv, fw_domains);
568 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
570 if (!dev_priv->uncore.funcs.force_wake_get)
573 WARN_ON(dev_priv->uncore.fw_domains_active);
576 /* We give fast paths for the really cool registers */
577 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
579 #define __gen6_reg_read_fw_domains(offset) \
581 enum forcewake_domains __fwd; \
582 if (NEEDS_FORCE_WAKE(offset)) \
583 __fwd = FORCEWAKE_RENDER; \
589 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
591 if (offset < entry->start)
593 else if (offset > entry->end)
599 /* Copied and "macroized" from lib/bsearch.c */
600 #define BSEARCH(key, base, num, cmp) ({ \
601 unsigned int start__ = 0, end__ = (num); \
602 typeof(base) result__ = NULL; \
603 while (start__ < end__) { \
604 unsigned int mid__ = start__ + (end__ - start__) / 2; \
605 int ret__ = (cmp)((key), (base) + mid__); \
608 } else if (ret__ > 0) { \
609 start__ = mid__ + 1; \
611 result__ = (base) + mid__; \
618 static enum forcewake_domains
619 find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
621 const struct intel_forcewake_range *entry;
623 entry = BSEARCH(offset,
624 dev_priv->uncore.fw_domains_table,
625 dev_priv->uncore.fw_domains_table_entries,
631 WARN(entry->domains & ~dev_priv->uncore.fw_domains,
632 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
633 entry->domains & ~dev_priv->uncore.fw_domains, offset);
635 return entry->domains;
639 intel_fw_table_check(struct drm_i915_private *dev_priv)
641 const struct intel_forcewake_range *ranges;
642 unsigned int num_ranges;
646 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
649 ranges = dev_priv->uncore.fw_domains_table;
653 num_ranges = dev_priv->uncore.fw_domains_table_entries;
655 for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
656 WARN_ON_ONCE(IS_GEN9(dev_priv) &&
657 (prev + 1) != (s32)ranges->start);
658 WARN_ON_ONCE(prev >= (s32)ranges->start);
659 prev = ranges->start;
660 WARN_ON_ONCE(prev >= (s32)ranges->end);
665 #define GEN_FW_RANGE(s, e, d) \
666 { .start = (s), .end = (e), .domains = (d) }
668 #define HAS_FWTABLE(dev_priv) \
669 (IS_GEN9(dev_priv) || \
670 IS_CHERRYVIEW(dev_priv) || \
671 IS_VALLEYVIEW(dev_priv))
673 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
674 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
675 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
676 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
677 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
678 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
679 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
680 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
681 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
684 #define __fwtable_reg_read_fw_domains(offset) \
686 enum forcewake_domains __fwd = 0; \
687 if (NEEDS_FORCE_WAKE((offset))) \
688 __fwd = find_fw_domain(dev_priv, offset); \
692 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
693 static const i915_reg_t gen8_shadowed_regs[] = {
694 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
695 GEN6_RPNSWREQ, /* 0xA008 */
696 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
697 RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
698 RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
699 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
700 /* TODO: Other registers are not yet used */
703 static void intel_shadow_table_check(void)
705 const i915_reg_t *reg = gen8_shadowed_regs;
710 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
713 for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) {
714 offset = i915_mmio_reg_offset(*reg);
715 WARN_ON_ONCE(prev >= (s32)offset);
720 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
722 u32 offset = i915_mmio_reg_offset(*reg);
726 else if (key > offset)
732 static bool is_gen8_shadowed(u32 offset)
734 const i915_reg_t *regs = gen8_shadowed_regs;
736 return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs),
740 #define __gen8_reg_write_fw_domains(offset) \
742 enum forcewake_domains __fwd; \
743 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
744 __fwd = FORCEWAKE_RENDER; \
750 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
751 static const struct intel_forcewake_range __chv_fw_ranges[] = {
752 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
753 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
754 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
755 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
756 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
757 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
758 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
759 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
760 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
761 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
762 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
763 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
764 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
765 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
766 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
767 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
770 #define __fwtable_reg_write_fw_domains(offset) \
772 enum forcewake_domains __fwd = 0; \
773 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
774 __fwd = find_fw_domain(dev_priv, offset); \
778 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
779 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
780 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
781 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
782 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
783 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
784 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
785 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
786 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
787 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
788 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
789 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
790 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
791 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
792 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
793 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
794 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
795 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
796 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
797 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
798 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
799 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
800 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
801 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
802 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
803 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
804 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
805 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
806 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
807 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
808 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
809 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
810 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
811 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
815 ilk_dummy_write(struct drm_i915_private *dev_priv)
817 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
818 * the chip from rc6 before touching it for real. MI_MODE is masked,
819 * hence harmless to write 0 into. */
820 __raw_i915_write32(dev_priv, MI_MODE, 0);
824 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
825 const i915_reg_t reg,
829 if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
830 "Unclaimed %s register 0x%x\n",
831 read ? "read from" : "write to",
832 i915_mmio_reg_offset(reg)))
833 i915.mmio_debug--; /* Only report the first N failures */
837 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
838 const i915_reg_t reg,
842 if (likely(!i915.mmio_debug))
845 __unclaimed_reg_debug(dev_priv, reg, read, before);
848 static const enum decoupled_power_domain fw2dpd_domain[] = {
849 GEN9_DECOUPLED_PD_RENDER,
850 GEN9_DECOUPLED_PD_BLITTER,
851 GEN9_DECOUPLED_PD_ALL,
852 GEN9_DECOUPLED_PD_MEDIA,
853 GEN9_DECOUPLED_PD_ALL,
854 GEN9_DECOUPLED_PD_ALL,
855 GEN9_DECOUPLED_PD_ALL
859 * Decoupled MMIO access for only 1 DWORD
861 static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,
863 enum forcewake_domains fw_domain,
864 enum decoupled_ops operation)
866 enum decoupled_power_domain dp_domain;
867 u32 ctrl_reg_data = 0;
869 dp_domain = fw2dpd_domain[fw_domain - 1];
871 ctrl_reg_data |= reg;
872 ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT);
873 ctrl_reg_data |= (dp_domain << GEN9_DECOUPLED_PD_SHIFT);
874 ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO;
875 __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
877 if (wait_for_atomic((__raw_i915_read32(dev_priv,
878 GEN9_DECOUPLED_REG0_DW1) &
879 GEN9_DECOUPLED_DW1_GO) == 0,
880 FORCEWAKE_ACK_TIMEOUT_MS))
881 DRM_ERROR("Decoupled MMIO wait timed out\n");
885 __gen9_decoupled_mmio_read32(struct drm_i915_private *dev_priv,
887 enum forcewake_domains fw_domain)
889 __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
890 GEN9_DECOUPLED_OP_READ);
892 return __raw_i915_read32(dev_priv, GEN9_DECOUPLED_REG0_DW0);
896 __gen9_decoupled_mmio_write(struct drm_i915_private *dev_priv,
898 enum forcewake_domains fw_domain)
901 __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW0, data);
903 __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
904 GEN9_DECOUPLED_OP_WRITE);
908 #define GEN2_READ_HEADER(x) \
910 assert_rpm_wakelock_held(dev_priv);
912 #define GEN2_READ_FOOTER \
913 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
916 #define __gen2_read(x) \
918 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
919 GEN2_READ_HEADER(x); \
920 val = __raw_i915_read##x(dev_priv, reg); \
924 #define __gen5_read(x) \
926 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
927 GEN2_READ_HEADER(x); \
928 ilk_dummy_write(dev_priv); \
929 val = __raw_i915_read##x(dev_priv, reg); \
945 #undef GEN2_READ_FOOTER
946 #undef GEN2_READ_HEADER
948 #define GEN6_READ_HEADER(x) \
949 u32 offset = i915_mmio_reg_offset(reg); \
950 unsigned long irqflags; \
952 assert_rpm_wakelock_held(dev_priv); \
953 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
954 unclaimed_reg_debug(dev_priv, reg, true, true)
956 #define GEN6_READ_FOOTER \
957 unclaimed_reg_debug(dev_priv, reg, true, false); \
958 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
959 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
962 static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
963 enum forcewake_domains fw_domains)
965 struct intel_uncore_forcewake_domain *domain;
967 for_each_fw_domain_masked(domain, fw_domains, dev_priv)
968 fw_domain_arm_timer(domain);
970 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
971 dev_priv->uncore.fw_domains_active |= fw_domains;
974 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
975 enum forcewake_domains fw_domains)
977 if (WARN_ON(!fw_domains))
980 /* Turn on all requested but inactive supported forcewake domains. */
981 fw_domains &= dev_priv->uncore.fw_domains;
982 fw_domains &= ~dev_priv->uncore.fw_domains_active;
985 ___force_wake_auto(dev_priv, fw_domains);
988 #define __gen6_read(x) \
990 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
991 enum forcewake_domains fw_engine; \
992 GEN6_READ_HEADER(x); \
993 fw_engine = __gen6_reg_read_fw_domains(offset); \
995 __force_wake_auto(dev_priv, fw_engine); \
996 val = __raw_i915_read##x(dev_priv, reg); \
1000 #define __fwtable_read(x) \
1002 fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1003 enum forcewake_domains fw_engine; \
1004 GEN6_READ_HEADER(x); \
1005 fw_engine = __fwtable_reg_read_fw_domains(offset); \
1007 __force_wake_auto(dev_priv, fw_engine); \
1008 val = __raw_i915_read##x(dev_priv, reg); \
1012 #define __gen9_decoupled_read(x) \
1014 gen9_decoupled_read##x(struct drm_i915_private *dev_priv, \
1015 i915_reg_t reg, bool trace) { \
1016 enum forcewake_domains fw_engine; \
1017 GEN6_READ_HEADER(x); \
1018 fw_engine = __fwtable_reg_read_fw_domains(offset); \
1019 if (fw_engine & ~dev_priv->uncore.fw_domains_active) { \
1021 u32 *ptr_data = (u32 *) &val; \
1022 for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \
1023 *ptr_data = __gen9_decoupled_mmio_read32(dev_priv, \
1027 val = __raw_i915_read##x(dev_priv, reg); \
1032 __gen9_decoupled_read(32)
1033 __gen9_decoupled_read(64)
1043 #undef __fwtable_read
1045 #undef GEN6_READ_FOOTER
1046 #undef GEN6_READ_HEADER
1048 #define VGPU_READ_HEADER(x) \
1049 unsigned long irqflags; \
1051 assert_rpm_device_not_suspended(dev_priv); \
1052 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1054 #define VGPU_READ_FOOTER \
1055 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
1056 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1059 #define __vgpu_read(x) \
1061 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1062 VGPU_READ_HEADER(x); \
1063 val = __raw_i915_read##x(dev_priv, reg); \
1073 #undef VGPU_READ_FOOTER
1074 #undef VGPU_READ_HEADER
1076 #define GEN2_WRITE_HEADER \
1077 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1078 assert_rpm_wakelock_held(dev_priv); \
1080 #define GEN2_WRITE_FOOTER
1082 #define __gen2_write(x) \
1084 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1085 GEN2_WRITE_HEADER; \
1086 __raw_i915_write##x(dev_priv, reg, val); \
1087 GEN2_WRITE_FOOTER; \
1090 #define __gen5_write(x) \
1092 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1093 GEN2_WRITE_HEADER; \
1094 ilk_dummy_write(dev_priv); \
1095 __raw_i915_write##x(dev_priv, reg, val); \
1096 GEN2_WRITE_FOOTER; \
1109 #undef GEN2_WRITE_FOOTER
1110 #undef GEN2_WRITE_HEADER
1112 #define GEN6_WRITE_HEADER \
1113 u32 offset = i915_mmio_reg_offset(reg); \
1114 unsigned long irqflags; \
1115 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1116 assert_rpm_wakelock_held(dev_priv); \
1117 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1118 unclaimed_reg_debug(dev_priv, reg, false, true)
1120 #define GEN6_WRITE_FOOTER \
1121 unclaimed_reg_debug(dev_priv, reg, false, false); \
1122 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1124 #define __gen6_write(x) \
1126 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1127 u32 __fifo_ret = 0; \
1128 GEN6_WRITE_HEADER; \
1129 if (NEEDS_FORCE_WAKE(offset)) { \
1130 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1132 __raw_i915_write##x(dev_priv, reg, val); \
1133 if (unlikely(__fifo_ret)) { \
1134 gen6_gt_check_fifodbg(dev_priv); \
1136 GEN6_WRITE_FOOTER; \
1139 #define __gen8_write(x) \
1141 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1142 enum forcewake_domains fw_engine; \
1143 GEN6_WRITE_HEADER; \
1144 fw_engine = __gen8_reg_write_fw_domains(offset); \
1146 __force_wake_auto(dev_priv, fw_engine); \
1147 __raw_i915_write##x(dev_priv, reg, val); \
1148 GEN6_WRITE_FOOTER; \
1151 #define __fwtable_write(x) \
1153 fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1154 enum forcewake_domains fw_engine; \
1155 GEN6_WRITE_HEADER; \
1156 fw_engine = __fwtable_reg_write_fw_domains(offset); \
1158 __force_wake_auto(dev_priv, fw_engine); \
1159 __raw_i915_write##x(dev_priv, reg, val); \
1160 GEN6_WRITE_FOOTER; \
1163 #define __gen9_decoupled_write(x) \
1165 gen9_decoupled_write##x(struct drm_i915_private *dev_priv, \
1166 i915_reg_t reg, u##x val, \
1168 enum forcewake_domains fw_engine; \
1169 GEN6_WRITE_HEADER; \
1170 fw_engine = __fwtable_reg_write_fw_domains(offset); \
1171 if (fw_engine & ~dev_priv->uncore.fw_domains_active) \
1172 __gen9_decoupled_mmio_write(dev_priv, \
1177 __raw_i915_write##x(dev_priv, reg, val); \
1178 GEN6_WRITE_FOOTER; \
1181 __gen9_decoupled_write(32)
1192 #undef __fwtable_write
1195 #undef GEN6_WRITE_FOOTER
1196 #undef GEN6_WRITE_HEADER
1198 #define VGPU_WRITE_HEADER \
1199 unsigned long irqflags; \
1200 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1201 assert_rpm_device_not_suspended(dev_priv); \
1202 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1204 #define VGPU_WRITE_FOOTER \
1205 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1207 #define __vgpu_write(x) \
1208 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1209 i915_reg_t reg, u##x val, bool trace) { \
1210 VGPU_WRITE_HEADER; \
1211 __raw_i915_write##x(dev_priv, reg, val); \
1212 VGPU_WRITE_FOOTER; \
1220 #undef VGPU_WRITE_FOOTER
1221 #undef VGPU_WRITE_HEADER
1223 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1225 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1226 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1227 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1230 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1232 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1233 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1234 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1235 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1239 static void fw_domain_init(struct drm_i915_private *dev_priv,
1240 enum forcewake_domain_id domain_id,
1244 struct intel_uncore_forcewake_domain *d;
1246 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1249 d = &dev_priv->uncore.fw_domain[domain_id];
1251 WARN_ON(d->wake_count);
1254 d->reg_set = reg_set;
1255 d->reg_ack = reg_ack;
1257 if (IS_GEN6(dev_priv)) {
1259 d->val_set = FORCEWAKE_KERNEL;
1262 /* WaRsClearFWBitsAtReset:bdw,skl */
1263 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1264 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1265 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1268 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1269 d->reg_post = FORCEWAKE_ACK_VLV;
1270 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1271 d->reg_post = ECOBUS;
1276 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1277 BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1278 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1280 d->mask = 1 << domain_id;
1282 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1283 d->timer.function = intel_uncore_fw_release_timer;
1285 dev_priv->uncore.fw_domains |= (1 << domain_id);
1290 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1292 if (INTEL_INFO(dev_priv)->gen <= 5)
1295 if (IS_GEN9(dev_priv)) {
1296 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1297 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1298 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1299 FORCEWAKE_RENDER_GEN9,
1300 FORCEWAKE_ACK_RENDER_GEN9);
1301 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1302 FORCEWAKE_BLITTER_GEN9,
1303 FORCEWAKE_ACK_BLITTER_GEN9);
1304 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1305 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1306 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1307 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1308 if (!IS_CHERRYVIEW(dev_priv))
1309 dev_priv->uncore.funcs.force_wake_put =
1310 fw_domains_put_with_fifo;
1312 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1313 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1314 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1315 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1316 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1317 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1318 dev_priv->uncore.funcs.force_wake_get =
1319 fw_domains_get_with_thread_status;
1320 if (IS_HASWELL(dev_priv))
1321 dev_priv->uncore.funcs.force_wake_put =
1322 fw_domains_put_with_fifo;
1324 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1325 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1326 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1327 } else if (IS_IVYBRIDGE(dev_priv)) {
1330 /* IVB configs may use multi-threaded forcewake */
1332 /* A small trick here - if the bios hasn't configured
1333 * MT forcewake, and if the device is in RC6, then
1334 * force_wake_mt_get will not wake the device and the
1335 * ECOBUS read will return zero. Which will be
1336 * (correctly) interpreted by the test below as MT
1337 * forcewake being disabled.
1339 dev_priv->uncore.funcs.force_wake_get =
1340 fw_domains_get_with_thread_status;
1341 dev_priv->uncore.funcs.force_wake_put =
1342 fw_domains_put_with_fifo;
1344 /* We need to init first for ECOBUS access and then
1345 * determine later if we want to reinit, in case of MT access is
1346 * not working. In this stage we don't know which flavour this
1347 * ivb is, so it is better to reset also the gen6 fw registers
1348 * before the ecobus check.
1351 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1352 __raw_posting_read(dev_priv, ECOBUS);
1354 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1355 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1357 spin_lock_irq(&dev_priv->uncore.lock);
1358 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1359 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1360 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1361 spin_unlock_irq(&dev_priv->uncore.lock);
1363 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1364 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1365 DRM_INFO("when using vblank-synced partial screen updates.\n");
1366 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1367 FORCEWAKE, FORCEWAKE_ACK);
1369 } else if (IS_GEN6(dev_priv)) {
1370 dev_priv->uncore.funcs.force_wake_get =
1371 fw_domains_get_with_thread_status;
1372 dev_priv->uncore.funcs.force_wake_put =
1373 fw_domains_put_with_fifo;
1374 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1375 FORCEWAKE, FORCEWAKE_ACK);
1378 /* All future platforms are expected to require complex power gating */
1379 WARN_ON(dev_priv->uncore.fw_domains == 0);
1382 #define ASSIGN_FW_DOMAINS_TABLE(d) \
1384 dev_priv->uncore.fw_domains_table = \
1385 (struct intel_forcewake_range *)(d); \
1386 dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
1389 void intel_uncore_init(struct drm_i915_private *dev_priv)
1391 i915_check_vgpu(dev_priv);
1393 intel_uncore_edram_detect(dev_priv);
1394 intel_uncore_fw_domains_init(dev_priv);
1395 __intel_uncore_early_sanitize(dev_priv, false);
1397 dev_priv->uncore.unclaimed_mmio_check = 1;
1399 switch (INTEL_INFO(dev_priv)->gen) {
1402 ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
1403 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1404 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1405 if (HAS_DECOUPLED_MMIO(dev_priv)) {
1406 dev_priv->uncore.funcs.mmio_readl =
1407 gen9_decoupled_read32;
1408 dev_priv->uncore.funcs.mmio_readq =
1409 gen9_decoupled_read64;
1410 dev_priv->uncore.funcs.mmio_writel =
1411 gen9_decoupled_write32;
1415 if (IS_CHERRYVIEW(dev_priv)) {
1416 ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1417 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1418 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1421 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1422 ASSIGN_READ_MMIO_VFUNCS(gen6);
1427 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1429 if (IS_VALLEYVIEW(dev_priv)) {
1430 ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
1431 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1433 ASSIGN_READ_MMIO_VFUNCS(gen6);
1437 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1438 ASSIGN_READ_MMIO_VFUNCS(gen5);
1443 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1444 ASSIGN_READ_MMIO_VFUNCS(gen2);
1448 intel_fw_table_check(dev_priv);
1449 if (INTEL_GEN(dev_priv) >= 8)
1450 intel_shadow_table_check();
1452 if (intel_vgpu_active(dev_priv)) {
1453 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1454 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1457 i915_check_and_clear_faults(dev_priv);
1459 #undef ASSIGN_WRITE_MMIO_VFUNCS
1460 #undef ASSIGN_READ_MMIO_VFUNCS
1462 void intel_uncore_fini(struct drm_i915_private *dev_priv)
1464 /* Paranoia: make sure we have disabled everything before we exit. */
1465 intel_uncore_sanitize(dev_priv);
1466 intel_uncore_forcewake_reset(dev_priv, false);
1469 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1471 static const struct register_whitelist {
1472 i915_reg_t offset_ldw, offset_udw;
1474 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1475 uint32_t gen_bitmask;
1477 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1478 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1479 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1482 int i915_reg_read_ioctl(struct drm_device *dev,
1483 void *data, struct drm_file *file)
1485 struct drm_i915_private *dev_priv = to_i915(dev);
1486 struct drm_i915_reg_read *reg = data;
1487 struct register_whitelist const *entry = whitelist;
1489 i915_reg_t offset_ldw, offset_udw;
1492 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1493 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1494 (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
1498 if (i == ARRAY_SIZE(whitelist))
1501 /* We use the low bits to encode extra flags as the register should
1502 * be naturally aligned (and those that are not so aligned merely
1503 * limit the available flags for that register).
1505 offset_ldw = entry->offset_ldw;
1506 offset_udw = entry->offset_udw;
1508 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1510 intel_runtime_pm_get(dev_priv);
1514 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1517 reg->val = I915_READ64(offset_ldw);
1520 reg->val = I915_READ(offset_ldw);
1523 reg->val = I915_READ16(offset_ldw);
1526 reg->val = I915_READ8(offset_ldw);
1534 intel_runtime_pm_put(dev_priv);
1538 static int i915_reset_complete(struct pci_dev *pdev)
1541 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1542 return (gdrst & GRDOM_RESET_STATUS) == 0;
1545 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1547 struct pci_dev *pdev = dev_priv->drm.pdev;
1549 /* assert reset for at least 20 usec */
1550 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1552 pci_write_config_byte(pdev, I915_GDRST, 0);
1554 return wait_for(i915_reset_complete(pdev), 500);
1557 static int g4x_reset_complete(struct pci_dev *pdev)
1560 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1561 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1564 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1566 struct pci_dev *pdev = dev_priv->drm.pdev;
1567 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1568 return wait_for(g4x_reset_complete(pdev), 500);
1571 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1573 struct pci_dev *pdev = dev_priv->drm.pdev;
1576 pci_write_config_byte(pdev, I915_GDRST,
1577 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1578 ret = wait_for(g4x_reset_complete(pdev), 500);
1582 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1583 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1584 POSTING_READ(VDECCLK_GATE_D);
1586 pci_write_config_byte(pdev, I915_GDRST,
1587 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1588 ret = wait_for(g4x_reset_complete(pdev), 500);
1592 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1593 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1594 POSTING_READ(VDECCLK_GATE_D);
1596 pci_write_config_byte(pdev, I915_GDRST, 0);
1601 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1602 unsigned engine_mask)
1606 I915_WRITE(ILK_GDSR,
1607 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1608 ret = intel_wait_for_register(dev_priv,
1609 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1614 I915_WRITE(ILK_GDSR,
1615 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1616 ret = intel_wait_for_register(dev_priv,
1617 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1622 I915_WRITE(ILK_GDSR, 0);
1627 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1628 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1631 /* GEN6_GDRST is not in the gt power well, no need to check
1632 * for fifo space for the write or forcewake the chip for
1635 __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1637 /* Spin waiting for the device to ack the reset requests */
1638 return intel_wait_for_register_fw(dev_priv,
1639 GEN6_GDRST, hw_domain_mask, 0,
1644 * gen6_reset_engines - reset individual engines
1645 * @dev_priv: i915 device
1646 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1648 * This function will reset the individual engines that are set in engine_mask.
1649 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1651 * Note: It is responsibility of the caller to handle the difference between
1652 * asking full domain reset versus reset for all available individual engines.
1654 * Returns 0 on success, nonzero on error.
1656 static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1657 unsigned engine_mask)
1659 struct intel_engine_cs *engine;
1660 const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1661 [RCS] = GEN6_GRDOM_RENDER,
1662 [BCS] = GEN6_GRDOM_BLT,
1663 [VCS] = GEN6_GRDOM_MEDIA,
1664 [VCS2] = GEN8_GRDOM_MEDIA2,
1665 [VECS] = GEN6_GRDOM_VECS,
1670 if (engine_mask == ALL_ENGINES) {
1671 hw_mask = GEN6_GRDOM_FULL;
1676 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1677 hw_mask |= hw_engine_mask[engine->id];
1680 ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1682 intel_uncore_forcewake_reset(dev_priv, true);
1688 * intel_wait_for_register_fw - wait until register matches expected state
1689 * @dev_priv: the i915 device
1690 * @reg: the register to read
1691 * @mask: mask to apply to register value
1692 * @value: expected value
1693 * @timeout_ms: timeout in millisecond
1695 * This routine waits until the target register @reg contains the expected
1696 * @value after applying the @mask, i.e. it waits until ::
1698 * (I915_READ_FW(reg) & mask) == value
1700 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1702 * Note that this routine assumes the caller holds forcewake asserted, it is
1703 * not suitable for very long waits. See intel_wait_for_register() if you
1704 * wish to wait without holding forcewake for the duration (i.e. you expect
1705 * the wait to be slow).
1707 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1709 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1713 const unsigned long timeout_ms)
1715 #define done ((I915_READ_FW(reg) & mask) == value)
1716 int ret = wait_for_us(done, 2);
1718 ret = wait_for(done, timeout_ms);
1724 * intel_wait_for_register - wait until register matches expected state
1725 * @dev_priv: the i915 device
1726 * @reg: the register to read
1727 * @mask: mask to apply to register value
1728 * @value: expected value
1729 * @timeout_ms: timeout in millisecond
1731 * This routine waits until the target register @reg contains the expected
1732 * @value after applying the @mask, i.e. it waits until ::
1734 * (I915_READ(reg) & mask) == value
1736 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1738 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1740 int intel_wait_for_register(struct drm_i915_private *dev_priv,
1744 const unsigned long timeout_ms)
1748 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1751 intel_uncore_forcewake_get(dev_priv, fw);
1752 ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
1753 intel_uncore_forcewake_put(dev_priv, fw);
1755 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
1761 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1763 struct drm_i915_private *dev_priv = engine->i915;
1766 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1767 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1769 ret = intel_wait_for_register_fw(dev_priv,
1770 RING_RESET_CTL(engine->mmio_base),
1771 RESET_CTL_READY_TO_RESET,
1772 RESET_CTL_READY_TO_RESET,
1775 DRM_ERROR("%s: reset request timeout\n", engine->name);
1780 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1782 struct drm_i915_private *dev_priv = engine->i915;
1784 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1785 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1788 static int gen8_reset_engines(struct drm_i915_private *dev_priv,
1789 unsigned engine_mask)
1791 struct intel_engine_cs *engine;
1794 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1795 if (gen8_request_engine_reset(engine))
1798 return gen6_reset_engines(dev_priv, engine_mask);
1801 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1802 gen8_unrequest_engine_reset(engine);
1807 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
1809 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
1814 if (INTEL_INFO(dev_priv)->gen >= 8)
1815 return gen8_reset_engines;
1816 else if (INTEL_INFO(dev_priv)->gen >= 6)
1817 return gen6_reset_engines;
1818 else if (IS_GEN5(dev_priv))
1819 return ironlake_do_reset;
1820 else if (IS_G4X(dev_priv))
1821 return g4x_do_reset;
1822 else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
1823 return g33_do_reset;
1824 else if (INTEL_INFO(dev_priv)->gen >= 3)
1825 return i915_do_reset;
1830 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1835 reset = intel_get_gpu_reset(dev_priv);
1839 /* If the power well sleeps during the reset, the reset
1840 * request may be dropped and never completes (causing -EIO).
1842 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1843 ret = reset(dev_priv, engine_mask);
1844 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1849 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
1851 return intel_get_gpu_reset(dev_priv) != NULL;
1854 int intel_guc_reset(struct drm_i915_private *dev_priv)
1857 unsigned long irqflags;
1859 if (!HAS_GUC(dev_priv))
1862 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1863 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1865 ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1867 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1868 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1873 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1875 return check_for_unclaimed_mmio(dev_priv);
1879 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1881 if (unlikely(i915.mmio_debug ||
1882 dev_priv->uncore.unclaimed_mmio_check <= 0))
1885 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1886 DRM_DEBUG("Unclaimed register detected, "
1887 "enabling oneshot unclaimed register reporting. "
1888 "Please use i915.mmio_debug=N for more information.\n");
1890 dev_priv->uncore.unclaimed_mmio_check--;
1897 static enum forcewake_domains
1898 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1901 u32 offset = i915_mmio_reg_offset(reg);
1902 enum forcewake_domains fw_domains;
1904 if (HAS_FWTABLE(dev_priv)) {
1905 fw_domains = __fwtable_reg_read_fw_domains(offset);
1906 } else if (INTEL_GEN(dev_priv) >= 6) {
1907 fw_domains = __gen6_reg_read_fw_domains(offset);
1909 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1913 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1918 static enum forcewake_domains
1919 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1922 u32 offset = i915_mmio_reg_offset(reg);
1923 enum forcewake_domains fw_domains;
1925 if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
1926 fw_domains = __fwtable_reg_write_fw_domains(offset);
1927 } else if (IS_GEN8(dev_priv)) {
1928 fw_domains = __gen8_reg_write_fw_domains(offset);
1929 } else if (IS_GEN(dev_priv, 6, 7)) {
1930 fw_domains = FORCEWAKE_RENDER;
1932 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1936 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1942 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1944 * @dev_priv: pointer to struct drm_i915_private
1945 * @reg: register in question
1946 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1948 * Returns a set of forcewake domains required to be taken with for example
1949 * intel_uncore_forcewake_get for the specified register to be accessible in the
1950 * specified mode (read, write or read/write) with raw mmio accessors.
1952 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1953 * callers to do FIFO management on their own or risk losing writes.
1955 enum forcewake_domains
1956 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1957 i915_reg_t reg, unsigned int op)
1959 enum forcewake_domains fw_domains = 0;
1963 if (intel_vgpu_active(dev_priv))
1966 if (op & FW_REG_READ)
1967 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1969 if (op & FW_REG_WRITE)
1970 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);