drivers/gpu/drm/i915/intel_uncore.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef __INTEL_UNCORE_H__
  26 #define __INTEL_UNCORE_H__
  27
  28 #include <linux/spinlock.h>
  29 #include <linux/notifier.h>
  30 #include <linux/hrtimer.h>
  31
  32 #include "i915_reg.h"
  33
  34 struct drm_i915_private;
  35 struct i915_runtime_pm;
  36 struct intel_uncore;
  37
  38 enum forcewake_domain_id {
  39         FW_DOMAIN_ID_RENDER = 0,
  40         FW_DOMAIN_ID_BLITTER,
  41         FW_DOMAIN_ID_MEDIA,
  42         FW_DOMAIN_ID_MEDIA_VDBOX0,
  43         FW_DOMAIN_ID_MEDIA_VDBOX1,
  44         FW_DOMAIN_ID_MEDIA_VDBOX2,
  45         FW_DOMAIN_ID_MEDIA_VDBOX3,
  46         FW_DOMAIN_ID_MEDIA_VEBOX0,
  47         FW_DOMAIN_ID_MEDIA_VEBOX1,
  48
  49         FW_DOMAIN_ID_COUNT
  50 };
  51
  52 enum forcewake_domains {
  53         FORCEWAKE_RENDER        = BIT(FW_DOMAIN_ID_RENDER),
  54         FORCEWAKE_BLITTER       = BIT(FW_DOMAIN_ID_BLITTER),
  55         FORCEWAKE_MEDIA         = BIT(FW_DOMAIN_ID_MEDIA),
  56         FORCEWAKE_MEDIA_VDBOX0  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
  57         FORCEWAKE_MEDIA_VDBOX1  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
  58         FORCEWAKE_MEDIA_VDBOX2  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
  59         FORCEWAKE_MEDIA_VDBOX3  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
  60         FORCEWAKE_MEDIA_VEBOX0  = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
  61         FORCEWAKE_MEDIA_VEBOX1  = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
  62
  63         FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
  64 };
  65
  66 struct intel_uncore_funcs {
  67         void (*force_wake_get)(struct intel_uncore *uncore,
  68                                enum forcewake_domains domains);
  69         void (*force_wake_put)(struct intel_uncore *uncore,
  70                                enum forcewake_domains domains);
  71
  72         u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
  73                          i915_reg_t r, bool trace);
  74         u16 (*mmio_readw)(struct drm_i915_private *dev_priv,
  75                           i915_reg_t r, bool trace);
  76         u32 (*mmio_readl)(struct drm_i915_private *dev_priv,
  77                           i915_reg_t r, bool trace);
  78         u64 (*mmio_readq)(struct drm_i915_private *dev_priv,
  79                           i915_reg_t r, bool trace);
  80
  81         void (*mmio_writeb)(struct drm_i915_private *dev_priv,
  82                             i915_reg_t r, u8 val, bool trace);
  83         void (*mmio_writew)(struct drm_i915_private *dev_priv,
  84                             i915_reg_t r, u16 val, bool trace);
  85         void (*mmio_writel)(struct drm_i915_private *dev_priv,
  86                             i915_reg_t r, u32 val, bool trace);
  87 };
  88
  89 struct intel_forcewake_range {
  90         u32 start;
  91         u32 end;
  92
  93         enum forcewake_domains domains;
  94 };
  95
  96 struct intel_uncore {
  97         void __iomem *regs;
  98
  99         struct i915_runtime_pm *rpm;
 100
 101         spinlock_t lock; /** lock is also taken in irq contexts. */
 102
 103         unsigned int flags;
 104 #define UNCORE_HAS_FORCEWAKE            BIT(0)
 105 #define UNCORE_HAS_FPGA_DBG_UNCLAIMED   BIT(1)
 106 #define UNCORE_HAS_DBG_UNCLAIMED        BIT(2)
 107 #define UNCORE_HAS_FIFO                 BIT(3)
 108
 109         const struct intel_forcewake_range *fw_domains_table;
 110         unsigned int fw_domains_table_entries;
 111
 112         struct notifier_block pmic_bus_access_nb;
 113         struct intel_uncore_funcs funcs;
 114
 115         unsigned int fifo_count;
 116
 117         enum forcewake_domains fw_domains;
 118         enum forcewake_domains fw_domains_active;
 119         enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
 120
 121         struct intel_uncore_forcewake_domain {
 122                 enum forcewake_domain_id id;
 123                 enum forcewake_domains mask;
 124                 unsigned int wake_count;
 125                 bool active;
 126                 struct hrtimer timer;
 127                 u32 __iomem *reg_set;
 128                 u32 __iomem *reg_ack;
 129         } fw_domain[FW_DOMAIN_ID_COUNT];
 130
 131         struct {
 132                 unsigned int count;
 133
 134                 int saved_mmio_check;
 135                 int saved_mmio_debug;
 136         } user_forcewake;
 137
 138         int unclaimed_mmio_check;
 139 };
 140
 141 /* Iterate over initialised fw domains */
 142 #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
 143         for (tmp__ = (mask__); \
 144              tmp__ ? (domain__ = &(uncore__)->fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
 145
 146 #define for_each_fw_domain(domain__, uncore__, tmp__) \
 147         for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
 148
 149 static inline struct intel_uncore *
 150 forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
 151 {
 152         return container_of(d, struct intel_uncore, fw_domain[d->id]);
 153 }
 154
 155 static inline bool
 156 intel_uncore_has_forcewake(const struct intel_uncore *uncore)
 157 {
 158         return uncore->flags & UNCORE_HAS_FORCEWAKE;
 159 }
 160
 161 static inline bool
 162 intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
 163 {
 164         return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
 165 }
 166
 167 static inline bool
 168 intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
 169 {
 170         return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
 171 }
 172
 173 static inline bool
 174 intel_uncore_has_fifo(const struct intel_uncore *uncore)
 175 {
 176         return uncore->flags & UNCORE_HAS_FIFO;
 177 }
 178
 179 void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
 180 int intel_uncore_init(struct intel_uncore *uncore);
 181 void intel_uncore_prune(struct intel_uncore *uncore);
 182 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
 183 bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
 184 void intel_uncore_fini(struct intel_uncore *uncore);
 185 void intel_uncore_suspend(struct intel_uncore *uncore);
 186 void intel_uncore_resume_early(struct intel_uncore *uncore);
 187 void intel_uncore_runtime_resume(struct intel_uncore *uncore);
 188
 189 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
 190 void assert_forcewakes_inactive(struct intel_uncore *uncore);
 191 void assert_forcewakes_active(struct intel_uncore *uncore,
 192                               enum forcewake_domains fw_domains);
 193 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
 194
 195 enum forcewake_domains
 196 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
 197                                i915_reg_t reg, unsigned int op);
 198 #define FW_REG_READ  (1)
 199 #define FW_REG_WRITE (2)
 200
 201 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 202                                 enum forcewake_domains domains);
 203 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 204                                 enum forcewake_domains domains);
 205 /* Like above but the caller must manage the uncore.lock itself.
 206  * Must be used with I915_READ_FW and friends.
 207  */
 208 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 209                                         enum forcewake_domains domains);
 210 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 211                                         enum forcewake_domains domains);
 212
 213 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
 214 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
 215
 216 int __intel_wait_for_register(struct drm_i915_private *dev_priv,
 217                               i915_reg_t reg,
 218                               u32 mask,
 219                               u32 value,
 220                               unsigned int fast_timeout_us,
 221                               unsigned int slow_timeout_ms,
 222                               u32 *out_value);
 223 static inline
 224 int intel_wait_for_register(struct drm_i915_private *dev_priv,
 225                             i915_reg_t reg,
 226                             u32 mask,
 227                             u32 value,
 228                             unsigned int timeout_ms)
 229 {
 230         return __intel_wait_for_register(dev_priv, reg, mask, value, 2,
 231                                          timeout_ms, NULL);
 232 }
 233 int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
 234                                  i915_reg_t reg,
 235                                  u32 mask,
 236                                  u32 value,
 237                                  unsigned int fast_timeout_us,
 238                                  unsigned int slow_timeout_ms,
 239                                  u32 *out_value);
 240 static inline
 241 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
 242                                i915_reg_t reg,
 243                                u32 mask,
 244                                u32 value,
 245                                unsigned int timeout_ms)
 246 {
 247         return __intel_wait_for_register_fw(dev_priv, reg, mask, value,
 248                                             2, timeout_ms, NULL);
 249 }
 250
 251 /* register access functions */
 252 #define __raw_read(x__, s__) \
 253 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
 254                                             i915_reg_t reg) \
 255 { \
 256         return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
 257 }
 258
 259 #define __raw_write(x__, s__) \
 260 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
 261                                            i915_reg_t reg, u##x__ val) \
 262 { \
 263         write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
 264 }
 265 __raw_read(8, b)
 266 __raw_read(16, w)
 267 __raw_read(32, l)
 268 __raw_read(64, q)
 269
 270 __raw_write(8, b)
 271 __raw_write(16, w)
 272 __raw_write(32, l)
 273 __raw_write(64, q)
 274
 275 #undef __raw_read
 276 #undef __raw_write
 277
 278 #define raw_reg_read(base, reg) \
 279         readl(base + i915_mmio_reg_offset(reg))
 280 #define raw_reg_write(base, reg, value) \
 281         writel(value, base + i915_mmio_reg_offset(reg))
 282
 283 #endif /* !__INTEL_UNCORE_H__ */