2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_UNCORE_H__
26 #define __INTEL_UNCORE_H__
28 #include <linux/spinlock.h>
29 #include <linux/notifier.h>
30 #include <linux/hrtimer.h>
34 struct drm_i915_private;
35 struct i915_runtime_pm;
38 enum forcewake_domain_id {
39 FW_DOMAIN_ID_RENDER = 0,
42 FW_DOMAIN_ID_MEDIA_VDBOX0,
43 FW_DOMAIN_ID_MEDIA_VDBOX1,
44 FW_DOMAIN_ID_MEDIA_VDBOX2,
45 FW_DOMAIN_ID_MEDIA_VDBOX3,
46 FW_DOMAIN_ID_MEDIA_VEBOX0,
47 FW_DOMAIN_ID_MEDIA_VEBOX1,
52 enum forcewake_domains {
53 FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
54 FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),
55 FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
56 FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
57 FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
58 FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
59 FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
60 FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
61 FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
63 FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
66 struct intel_uncore_funcs {
67 void (*force_wake_get)(struct intel_uncore *uncore,
68 enum forcewake_domains domains);
69 void (*force_wake_put)(struct intel_uncore *uncore,
70 enum forcewake_domains domains);
72 u8 (*mmio_readb)(struct intel_uncore *uncore,
73 i915_reg_t r, bool trace);
74 u16 (*mmio_readw)(struct intel_uncore *uncore,
75 i915_reg_t r, bool trace);
76 u32 (*mmio_readl)(struct intel_uncore *uncore,
77 i915_reg_t r, bool trace);
78 u64 (*mmio_readq)(struct intel_uncore *uncore,
79 i915_reg_t r, bool trace);
81 void (*mmio_writeb)(struct intel_uncore *uncore,
82 i915_reg_t r, u8 val, bool trace);
83 void (*mmio_writew)(struct intel_uncore *uncore,
84 i915_reg_t r, u16 val, bool trace);
85 void (*mmio_writel)(struct intel_uncore *uncore,
86 i915_reg_t r, u32 val, bool trace);
89 struct intel_forcewake_range {
93 enum forcewake_domains domains;
99 struct i915_runtime_pm *rpm;
101 spinlock_t lock; /** lock is also taken in irq contexts. */
104 #define UNCORE_HAS_FORCEWAKE BIT(0)
105 #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
106 #define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
107 #define UNCORE_HAS_FIFO BIT(3)
109 const struct intel_forcewake_range *fw_domains_table;
110 unsigned int fw_domains_table_entries;
112 struct notifier_block pmic_bus_access_nb;
113 struct intel_uncore_funcs funcs;
115 unsigned int fifo_count;
117 enum forcewake_domains fw_domains;
118 enum forcewake_domains fw_domains_active;
119 enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
121 struct intel_uncore_forcewake_domain {
122 enum forcewake_domain_id id;
123 enum forcewake_domains mask;
124 unsigned int wake_count;
126 struct hrtimer timer;
127 u32 __iomem *reg_set;
128 u32 __iomem *reg_ack;
129 } fw_domain[FW_DOMAIN_ID_COUNT];
134 int saved_mmio_check;
135 int saved_mmio_debug;
138 int unclaimed_mmio_check;
141 /* Iterate over initialised fw domains */
142 #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
143 for (tmp__ = (mask__); \
144 tmp__ ? (domain__ = &(uncore__)->fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
146 #define for_each_fw_domain(domain__, uncore__, tmp__) \
147 for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
149 static inline struct intel_uncore *
150 forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
152 return container_of(d, struct intel_uncore, fw_domain[d->id]);
156 intel_uncore_has_forcewake(const struct intel_uncore *uncore)
158 return uncore->flags & UNCORE_HAS_FORCEWAKE;
162 intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
164 return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
168 intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
170 return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
174 intel_uncore_has_fifo(const struct intel_uncore *uncore)
176 return uncore->flags & UNCORE_HAS_FIFO;
179 void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
180 int intel_uncore_init(struct intel_uncore *uncore);
181 void intel_uncore_prune(struct intel_uncore *uncore);
182 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
183 bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
184 void intel_uncore_fini(struct intel_uncore *uncore);
185 void intel_uncore_suspend(struct intel_uncore *uncore);
186 void intel_uncore_resume_early(struct intel_uncore *uncore);
187 void intel_uncore_runtime_resume(struct intel_uncore *uncore);
189 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
190 void assert_forcewakes_inactive(struct intel_uncore *uncore);
191 void assert_forcewakes_active(struct intel_uncore *uncore,
192 enum forcewake_domains fw_domains);
193 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
195 enum forcewake_domains
196 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
197 i915_reg_t reg, unsigned int op);
198 #define FW_REG_READ (1)
199 #define FW_REG_WRITE (2)
201 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
202 enum forcewake_domains domains);
203 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
204 enum forcewake_domains domains);
205 /* Like above but the caller must manage the uncore.lock itself.
206 * Must be used with I915_READ_FW and friends.
208 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
209 enum forcewake_domains domains);
210 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
211 enum forcewake_domains domains);
213 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
214 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
216 int __intel_wait_for_register(struct drm_i915_private *dev_priv,
220 unsigned int fast_timeout_us,
221 unsigned int slow_timeout_ms,
224 intel_wait_for_register(struct drm_i915_private *dev_priv,
228 unsigned int timeout_ms)
230 return __intel_wait_for_register(dev_priv, reg, mask, value, 2,
234 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
238 unsigned int fast_timeout_us,
239 unsigned int slow_timeout_ms,
242 intel_wait_for_register_fw(struct intel_uncore *uncore,
246 unsigned int timeout_ms)
248 return __intel_wait_for_register_fw(uncore, reg, mask, value,
249 2, timeout_ms, NULL);
252 /* register access functions */
253 #define __raw_read(x__, s__) \
254 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
257 return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
260 #define __raw_write(x__, s__) \
261 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
262 i915_reg_t reg, u##x__ val) \
264 write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
279 #define __uncore_read(name__, x__, s__, trace__) \
280 static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
283 return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
286 #define __uncore_write(name__, x__, s__, trace__) \
287 static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
288 i915_reg_t reg, u##x__ val) \
290 uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
293 __uncore_read(read8, 8, b, true)
294 __uncore_read(read16, 16, w, true)
295 __uncore_read(read, 32, l, true)
296 __uncore_read(read16_notrace, 16, w, false)
297 __uncore_read(read_notrace, 32, l, false)
299 __uncore_write(write8, 8, b, true)
300 __uncore_write(write16, 16, w, true)
301 __uncore_write(write, 32, l, true)
302 __uncore_write(write_notrace, 32, l, false)
304 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
305 * will be implemented using 2 32-bit writes in an arbitrary order with
306 * an arbitrary delay between them. This can cause the hardware to
307 * act upon the intermediate value, possibly leading to corruption and
308 * machine death. For this reason we do not support I915_WRITE64, or
309 * uncore->funcs.mmio_writeq.
311 * When reading a 64-bit value as two 32-bit values, the delay may cause
312 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
313 * occasionally a 64-bit register does not actually support a full readq
314 * and must be read using two 32-bit reads.
316 * You have been warned.
318 __uncore_read(read64, 64, q, true)
321 intel_uncore_read64_2x32(struct intel_uncore *uncore,
322 i915_reg_t lower_reg, i915_reg_t upper_reg)
324 u32 upper, lower, old_upper, loop = 0;
325 upper = intel_uncore_read(uncore, upper_reg);
328 lower = intel_uncore_read(uncore, lower_reg);
329 upper = intel_uncore_read(uncore, upper_reg);
330 } while (upper != old_upper && loop++ < 2);
331 return (u64)upper << 32 | lower;
334 #define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
335 #define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
338 #undef __uncore_write
340 /* These are untraced mmio-accessors that are only valid to be used inside
341 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
344 * Think twice, and think again, before using these.
346 * As an example, these accessors can possibly be used between:
348 * spin_lock_irq(&uncore->lock);
349 * intel_uncore_forcewake_get__locked();
353 * intel_uncore_forcewake_put__locked();
354 * spin_unlock_irq(&uncore->lock);
357 * Note: some registers may not need forcewake held, so
358 * intel_uncore_forcewake_{get,put} can be omitted, see
359 * intel_uncore_forcewake_for_reg().
361 * Certain architectures will die if the same cacheline is concurrently accessed
362 * by different clients (e.g. on Ivybridge). Access to registers should
363 * therefore generally be serialised, by either the dev_priv->uncore.lock or
364 * a more localised lock guarding all access to that bank of registers.
366 #define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
367 #define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
368 #define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
369 #define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
371 static inline void intel_uncore_rmw_or_fw(struct intel_uncore *uncore,
372 i915_reg_t reg, u32 or_val)
374 intel_uncore_write_fw(uncore, reg,
375 intel_uncore_read_fw(uncore, reg) | or_val);
378 #define raw_reg_read(base, reg) \
379 readl(base + i915_mmio_reg_offset(reg))
380 #define raw_reg_write(base, reg, value) \
381 writel(value, base + i915_mmio_reg_offset(reg))
383 #endif /* !__INTEL_UNCORE_H__ */