drivers/gpu/drm/i915/intel_uncore.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef __INTEL_UNCORE_H__
  26 #define __INTEL_UNCORE_H__
  27
  28 #include <linux/spinlock.h>
  29 #include <linux/notifier.h>
  30 #include <linux/hrtimer.h>
  31
  32 #include "i915_reg.h"
  33
  34 struct drm_i915_private;
  35 struct intel_uncore;
  36
  37 enum forcewake_domain_id {
  38         FW_DOMAIN_ID_RENDER = 0,
  39         FW_DOMAIN_ID_BLITTER,
  40         FW_DOMAIN_ID_MEDIA,
  41         FW_DOMAIN_ID_MEDIA_VDBOX0,
  42         FW_DOMAIN_ID_MEDIA_VDBOX1,
  43         FW_DOMAIN_ID_MEDIA_VDBOX2,
  44         FW_DOMAIN_ID_MEDIA_VDBOX3,
  45         FW_DOMAIN_ID_MEDIA_VEBOX0,
  46         FW_DOMAIN_ID_MEDIA_VEBOX1,
  47
  48         FW_DOMAIN_ID_COUNT
  49 };
  50
  51 enum forcewake_domains {
  52         FORCEWAKE_RENDER        = BIT(FW_DOMAIN_ID_RENDER),
  53         FORCEWAKE_BLITTER       = BIT(FW_DOMAIN_ID_BLITTER),
  54         FORCEWAKE_MEDIA         = BIT(FW_DOMAIN_ID_MEDIA),
  55         FORCEWAKE_MEDIA_VDBOX0  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
  56         FORCEWAKE_MEDIA_VDBOX1  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
  57         FORCEWAKE_MEDIA_VDBOX2  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
  58         FORCEWAKE_MEDIA_VDBOX3  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
  59         FORCEWAKE_MEDIA_VEBOX0  = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
  60         FORCEWAKE_MEDIA_VEBOX1  = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
  61
  62         FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
  63 };
  64
  65 struct intel_uncore_funcs {
  66         void (*force_wake_get)(struct intel_uncore *uncore,
  67                                enum forcewake_domains domains);
  68         void (*force_wake_put)(struct intel_uncore *uncore,
  69                                enum forcewake_domains domains);
  70
  71         u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
  72                          i915_reg_t r, bool trace);
  73         u16 (*mmio_readw)(struct drm_i915_private *dev_priv,
  74                           i915_reg_t r, bool trace);
  75         u32 (*mmio_readl)(struct drm_i915_private *dev_priv,
  76                           i915_reg_t r, bool trace);
  77         u64 (*mmio_readq)(struct drm_i915_private *dev_priv,
  78                           i915_reg_t r, bool trace);
  79
  80         void (*mmio_writeb)(struct drm_i915_private *dev_priv,
  81                             i915_reg_t r, u8 val, bool trace);
  82         void (*mmio_writew)(struct drm_i915_private *dev_priv,
  83                             i915_reg_t r, u16 val, bool trace);
  84         void (*mmio_writel)(struct drm_i915_private *dev_priv,
  85                             i915_reg_t r, u32 val, bool trace);
  86 };
  87
  88 struct intel_forcewake_range {
  89         u32 start;
  90         u32 end;
  91
  92         enum forcewake_domains domains;
  93 };
  94
  95 struct intel_uncore {
  96         void __iomem *regs;
  97
  98         spinlock_t lock; /** lock is also taken in irq contexts. */
  99
 100         const struct intel_forcewake_range *fw_domains_table;
 101         unsigned int fw_domains_table_entries;
 102
 103         struct notifier_block pmic_bus_access_nb;
 104         struct intel_uncore_funcs funcs;
 105
 106         unsigned int fifo_count;
 107
 108         enum forcewake_domains fw_domains;
 109         enum forcewake_domains fw_domains_active;
 110         enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
 111
 112         struct intel_uncore_forcewake_domain {
 113                 enum forcewake_domain_id id;
 114                 enum forcewake_domains mask;
 115                 unsigned int wake_count;
 116                 bool active;
 117                 struct hrtimer timer;
 118                 u32 __iomem *reg_set;
 119                 u32 __iomem *reg_ack;
 120         } fw_domain[FW_DOMAIN_ID_COUNT];
 121
 122         struct {
 123                 unsigned int count;
 124
 125                 int saved_mmio_check;
 126                 int saved_mmio_debug;
 127         } user_forcewake;
 128
 129         int unclaimed_mmio_check;
 130 };
 131
 132 /* Iterate over initialised fw domains */
 133 #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
 134         for (tmp__ = (mask__); \
 135              tmp__ ? (domain__ = &(uncore__)->fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
 136
 137 #define for_each_fw_domain(domain__, uncore__, tmp__) \
 138         for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
 139
 140 static inline struct intel_uncore *
 141 forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
 142 {
 143         return container_of(d, struct intel_uncore, fw_domain[d->id]);
 144 }
 145
 146 void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
 147 int intel_uncore_init(struct intel_uncore *uncore);
 148 void intel_uncore_prune(struct intel_uncore *uncore);
 149 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
 150 bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
 151 void intel_uncore_fini(struct intel_uncore *uncore);
 152 void intel_uncore_suspend(struct intel_uncore *uncore);
 153 void intel_uncore_resume_early(struct intel_uncore *uncore);
 154 void intel_uncore_runtime_resume(struct intel_uncore *uncore);
 155
 156 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
 157 void assert_forcewakes_inactive(struct intel_uncore *uncore);
 158 void assert_forcewakes_active(struct intel_uncore *uncore,
 159                               enum forcewake_domains fw_domains);
 160 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
 161
 162 enum forcewake_domains
 163 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
 164                                i915_reg_t reg, unsigned int op);
 165 #define FW_REG_READ  (1)
 166 #define FW_REG_WRITE (2)
 167
 168 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 169                                 enum forcewake_domains domains);
 170 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 171                                 enum forcewake_domains domains);
 172 /* Like above but the caller must manage the uncore.lock itself.
 173  * Must be used with I915_READ_FW and friends.
 174  */
 175 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 176                                         enum forcewake_domains domains);
 177 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 178                                         enum forcewake_domains domains);
 179
 180 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
 181 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
 182
 183 int __intel_wait_for_register(struct drm_i915_private *dev_priv,
 184                               i915_reg_t reg,
 185                               u32 mask,
 186                               u32 value,
 187                               unsigned int fast_timeout_us,
 188                               unsigned int slow_timeout_ms,
 189                               u32 *out_value);
 190 static inline
 191 int intel_wait_for_register(struct drm_i915_private *dev_priv,
 192                             i915_reg_t reg,
 193                             u32 mask,
 194                             u32 value,
 195                             unsigned int timeout_ms)
 196 {
 197         return __intel_wait_for_register(dev_priv, reg, mask, value, 2,
 198                                          timeout_ms, NULL);
 199 }
 200 int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
 201                                  i915_reg_t reg,
 202                                  u32 mask,
 203                                  u32 value,
 204                                  unsigned int fast_timeout_us,
 205                                  unsigned int slow_timeout_ms,
 206                                  u32 *out_value);
 207 static inline
 208 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
 209                                i915_reg_t reg,
 210                                u32 mask,
 211                                u32 value,
 212                                unsigned int timeout_ms)
 213 {
 214         return __intel_wait_for_register_fw(dev_priv, reg, mask, value,
 215                                             2, timeout_ms, NULL);
 216 }
 217
 218 /* register access functions */
 219 #define __raw_read(x__, s__) \
 220 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
 221                                             i915_reg_t reg) \
 222 { \
 223         return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
 224 }
 225
 226 #define __raw_write(x__, s__) \
 227 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
 228                                            i915_reg_t reg, u##x__ val) \
 229 { \
 230         write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
 231 }
 232 __raw_read(8, b)
 233 __raw_read(16, w)
 234 __raw_read(32, l)
 235 __raw_read(64, q)
 236
 237 __raw_write(8, b)
 238 __raw_write(16, w)
 239 __raw_write(32, l)
 240 __raw_write(64, q)
 241
 242 #undef __raw_read
 243 #undef __raw_write
 244
 245 #define raw_reg_read(base, reg) \
 246         readl(base + i915_mmio_reg_offset(reg))
 247 #define raw_reg_write(base, reg, value) \
 248         writel(value, base + i915_mmio_reg_offset(reg))
 249
 250 #endif /* !__INTEL_UNCORE_H__ */