2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Shobhit Kumar <shobhit.kumar@intel.com>
25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
28 #include <linux/kernel.h>
29 #include "intel_drv.h"
31 #include "intel_dsi.h"
33 static const u16 lfsr_converts[] = {
34 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
35 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
36 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
37 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
40 /* Get DSI clock from pixel clock */
41 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
45 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
47 /* DSI data rate = pixel clock * bits per pixel / lane count
48 pixel clock is converted from KHz to Hz */
49 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
54 static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
55 struct intel_crtc_state *config,
58 unsigned int m_min, m_max, p_min = 2, p_max = 6;
60 unsigned int calc_m, calc_p;
63 /* target_dsi_clk is expected in kHz */
64 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
65 DRM_ERROR("DSI CLK Out of Range\n");
69 if (IS_CHERRYVIEW(dev_priv)) {
83 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
85 for (m = m_min; m <= m_max && delta; m++) {
86 for (p = p_min; p <= p_max && delta; p++) {
88 * Find the optimal m and p divisors with minimal delta
89 * +/- the required clock
91 int calc_dsi_clk = (m * ref_clk) / (p * n);
92 int d = abs(target_dsi_clk - calc_dsi_clk);
101 /* register has log2(N1), this works fine for powers of two */
102 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
103 config->dsi_pll.div =
104 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
105 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
111 * XXX: The muxing and gating is hard coded for now. Need to add support for
112 * sharing PLLs with two DSI outputs.
114 int vlv_dsi_pll_compute(struct intel_encoder *encoder,
115 struct intel_crtc_state *config)
117 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
118 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
122 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
123 intel_dsi->lane_count);
125 ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
127 DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
131 if (intel_dsi->ports & (1 << PORT_A))
132 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
134 if (intel_dsi->ports & (1 << PORT_C))
135 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
137 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
139 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
140 config->dsi_pll.div, config->dsi_pll.ctrl);
145 void vlv_dsi_pll_enable(struct intel_encoder *encoder,
146 const struct intel_crtc_state *config)
148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
152 mutex_lock(&dev_priv->sb_lock);
154 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
155 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
156 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
157 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
159 /* wait at least 0.5 us after ungating before enabling VCO,
160 * allow hrtimer subsystem optimization by relaxing timing
162 usleep_range(10, 50);
164 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
166 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
169 mutex_unlock(&dev_priv->sb_lock);
170 DRM_ERROR("DSI PLL lock failed\n");
173 mutex_unlock(&dev_priv->sb_lock);
175 DRM_DEBUG_KMS("DSI PLL locked\n");
178 void vlv_dsi_pll_disable(struct intel_encoder *encoder)
180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
185 mutex_lock(&dev_priv->sb_lock);
187 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
188 tmp &= ~DSI_PLL_VCO_EN;
189 tmp |= DSI_PLL_LDO_GATE;
190 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
192 mutex_unlock(&dev_priv->sb_lock);
195 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
201 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
202 val = I915_READ(BXT_DSI_PLL_ENABLE);
203 enabled = (val & mask) == mask;
209 * Dividers must be programmed with valid values. As per BSEPC, for
210 * GEMINLAKE only PORT A divider values are checked while for BXT
211 * both divider values are validated. Check this here for
212 * paranoia, since BIOS is known to misconfigure PLLs in this way at
213 * times, and since accessing DSI registers with invalid dividers
214 * causes a system hang.
216 val = I915_READ(BXT_DSI_PLL_CTL);
217 if (IS_GEMINILAKE(dev_priv)) {
218 if (!(val & BXT_DSIA_16X_MASK)) {
219 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
223 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
224 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
232 void bxt_dsi_pll_disable(struct intel_encoder *encoder)
234 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
239 val = I915_READ(BXT_DSI_PLL_ENABLE);
240 val &= ~BXT_DSI_PLL_DO_ENABLE;
241 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
244 * PLL lock should deassert within 200us.
245 * Wait up to 1ms before timing out.
247 if (intel_wait_for_register(&dev_priv->uncore,
252 DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
255 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
256 struct intel_crtc_state *config)
258 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
259 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
260 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
262 u32 pll_ctl, pll_div;
264 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
269 mutex_lock(&dev_priv->sb_lock);
270 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
271 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
272 mutex_unlock(&dev_priv->sb_lock);
274 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
275 config->dsi_pll.div = pll_div;
277 /* mask out other bits and extract the P1 divisor */
278 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
279 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
282 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
283 n = 1 << n; /* register has log2(N1) */
285 /* mask out the other bits and extract the M1 divisor */
286 pll_div &= DSI_PLL_M1_DIV_MASK;
287 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
290 pll_ctl = pll_ctl >> 1;
296 DRM_ERROR("wrong P1 divisor\n");
300 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
301 if (lfsr_converts[i] == pll_div)
305 if (i == ARRAY_SIZE(lfsr_converts)) {
306 DRM_ERROR("wrong m_seed programmed\n");
312 dsi_clock = (m * refclk) / (p * n);
314 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
319 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
320 struct intel_crtc_state *config)
325 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
327 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
329 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
331 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
333 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
335 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
337 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
341 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
344 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
345 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
347 temp = I915_READ(MIPI_CTRL(port));
348 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
349 I915_WRITE(MIPI_CTRL(port), temp |
350 intel_dsi->escape_clk_div <<
351 ESCAPE_CLOCK_DIVIDER_SHIFT);
354 static void glk_dsi_program_esc_clock(struct drm_device *dev,
355 const struct intel_crtc_state *config)
357 struct drm_i915_private *dev_priv = to_i915(dev);
366 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
368 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
370 ddr_clk = dsi_rate / 2;
372 /* Variable divider value */
373 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
375 /* Calculate TXESC1 divider */
376 if (div1_value <= 10)
377 txesc1_div = div1_value;
378 else if ((div1_value > 10) && (div1_value <= 20))
379 txesc1_div = DIV_ROUND_UP(div1_value, 2);
380 else if ((div1_value > 20) && (div1_value <= 30))
381 txesc1_div = DIV_ROUND_UP(div1_value, 4);
382 else if ((div1_value > 30) && (div1_value <= 40))
383 txesc1_div = DIV_ROUND_UP(div1_value, 6);
384 else if ((div1_value > 40) && (div1_value <= 50))
385 txesc1_div = DIV_ROUND_UP(div1_value, 8);
389 /* Calculate TXESC2 divider */
390 div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
393 txesc2_div = div2_value;
397 I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);
398 I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);
401 /* Program BXT Mipi clocks and dividers */
402 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
403 const struct intel_crtc_state *config)
405 struct drm_i915_private *dev_priv = to_i915(dev);
413 u32 mipi_8by3_divider;
415 /* Clear old configurations */
416 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
417 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
418 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
419 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
420 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
422 /* Get the current DSI rate(actual) */
423 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
424 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
427 * tx clock should be <= 20MHz and the div value must be
428 * subtracted by 1 as per bspec
430 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
432 * rx clock should be <= 150MHz and the div value must be
433 * subtracted by 1 as per bspec
435 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
438 * rx divider value needs to be updated in the
439 * two differnt bit fields in the register hence splitting the
440 * rx divider value accordingly
442 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
443 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
445 mipi_8by3_divider = 0x2;
447 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
448 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
449 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
450 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
452 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
455 int bxt_dsi_pll_compute(struct intel_encoder *encoder,
456 struct intel_crtc_state *config)
458 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
459 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
460 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
463 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
464 intel_dsi->lane_count);
467 * From clock diagram, to get PLL ratio divider, divide double of DSI
468 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
469 * round 'up' the result
471 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
473 if (IS_BROXTON(dev_priv)) {
474 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
475 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
477 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
478 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
481 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
482 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
485 DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
488 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
489 * Spec says both have to be programmed, even if one is not getting
490 * used. Configure MIPI_CLOCK_CTL dividers in modeset
492 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
494 /* As per recommendation from hardware team,
495 * Prog PVD ratio =1 if dsi ratio <= 50
497 if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
498 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
503 void bxt_dsi_pll_enable(struct intel_encoder *encoder,
504 const struct intel_crtc_state *config)
506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
507 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
513 /* Configure PLL vales */
514 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
515 POSTING_READ(BXT_DSI_PLL_CTL);
517 /* Program TX, RX, Dphy clocks */
518 if (IS_BROXTON(dev_priv)) {
519 for_each_dsi_port(port, intel_dsi->ports)
520 bxt_dsi_program_clocks(encoder->base.dev, port, config);
522 glk_dsi_program_esc_clock(encoder->base.dev, config);
526 val = I915_READ(BXT_DSI_PLL_ENABLE);
527 val |= BXT_DSI_PLL_DO_ENABLE;
528 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
530 /* Timeout and fail if PLL not locked */
531 if (intel_wait_for_register(&dev_priv->uncore,
536 DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
540 DRM_DEBUG_KMS("DSI PLL locked\n");
543 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
546 struct drm_device *dev = encoder->base.dev;
547 struct drm_i915_private *dev_priv = to_i915(dev);
549 /* Clear old configurations */
550 if (IS_BROXTON(dev_priv)) {
551 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
552 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
553 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
554 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
555 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
556 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
558 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
559 tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
560 I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
562 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
563 tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
564 I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
566 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);