1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX drm driver - LVDS display bridge
5 * Copyright (C) 2012 Sascha Hauer, Pengutronix
9 #include <linux/component.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/regmap.h>
16 #include <linux/videodev2.h>
18 #include <video/of_display_timing.h>
19 #include <video/of_videomode.h>
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_fb_helper.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
26 #include <drm/drm_print.h>
27 #include <drm/drm_probe_helper.h>
31 #define DRIVER_NAME "imx-ldb"
33 #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
34 #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
35 #define LDB_CH0_MODE_EN_MASK (3 << 0)
36 #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
37 #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
38 #define LDB_CH1_MODE_EN_MASK (3 << 2)
39 #define LDB_SPLIT_MODE_EN (1 << 4)
40 #define LDB_DATA_WIDTH_CH0_24 (1 << 5)
41 #define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
42 #define LDB_DATA_WIDTH_CH1_24 (1 << 7)
43 #define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
44 #define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
45 #define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
46 #define LDB_BGREF_RMODE_INT (1 << 15)
50 struct imx_ldb_channel {
52 struct drm_connector connector;
53 struct drm_encoder encoder;
55 /* Defines what is connected to the ldb, only one at a time */
56 struct drm_panel *panel;
57 struct drm_bridge *bridge;
59 struct device_node *child;
60 struct i2c_adapter *ddc;
64 struct drm_display_mode mode;
70 static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
72 return container_of(c, struct imx_ldb_channel, connector);
75 static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
77 return container_of(e, struct imx_ldb_channel, encoder);
87 struct regmap *regmap;
89 struct imx_ldb_channel channel[2];
90 struct clk *clk[2]; /* our own clock */
91 struct clk *clk_sel[4]; /* parent of display clock */
92 struct clk *clk_parent[4]; /* original parent of clk_sel */
93 struct clk *clk_pll[2]; /* upstream clock we can adjust */
95 const struct bus_mux *lvds_mux;
98 static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
101 struct imx_ldb *ldb = imx_ldb_ch->ldb;
102 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
104 switch (bus_format) {
105 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
107 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
108 if (imx_ldb_ch->chno == 0 || dual)
109 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
110 if (imx_ldb_ch->chno == 1 || dual)
111 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
113 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
114 if (imx_ldb_ch->chno == 0 || dual)
115 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
116 LDB_BIT_MAP_CH0_JEIDA;
117 if (imx_ldb_ch->chno == 1 || dual)
118 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
119 LDB_BIT_MAP_CH1_JEIDA;
124 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
126 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
129 if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs &&
130 imx_ldb_ch->panel->funcs->get_modes) {
131 num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel);
136 if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
137 imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
139 if (imx_ldb_ch->edid) {
140 drm_connector_update_edid_property(connector,
142 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
145 if (imx_ldb_ch->mode_valid) {
146 struct drm_display_mode *mode;
148 mode = drm_mode_create(connector->dev);
151 drm_mode_copy(mode, &imx_ldb_ch->mode);
152 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
153 drm_mode_probed_add(connector, mode);
160 static struct drm_encoder *imx_ldb_connector_best_encoder(
161 struct drm_connector *connector)
163 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
165 return &imx_ldb_ch->encoder;
168 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
169 unsigned long serial_clk, unsigned long di_clk)
173 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
174 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
175 clk_set_rate(ldb->clk_pll[chno], serial_clk);
177 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
178 clk_get_rate(ldb->clk_pll[chno]));
180 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
181 clk_get_rate(ldb->clk[chno]),
183 clk_set_rate(ldb->clk[chno], di_clk);
185 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
186 clk_get_rate(ldb->clk[chno]));
188 /* set display clock mux to LDB input clock */
189 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
192 "unable to set di%d parent clock to ldb_di%d\n", mux,
196 static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
198 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
199 struct imx_ldb *ldb = imx_ldb_ch->ldb;
200 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
201 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
203 drm_panel_prepare(imx_ldb_ch->panel);
206 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
207 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
209 clk_prepare_enable(ldb->clk[0]);
210 clk_prepare_enable(ldb->clk[1]);
212 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
215 if (imx_ldb_ch == &ldb->channel[0] || dual) {
216 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
217 if (mux == 0 || ldb->lvds_mux)
218 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
220 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
222 if (imx_ldb_ch == &ldb->channel[1] || dual) {
223 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
224 if (mux == 1 || ldb->lvds_mux)
225 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
227 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
231 const struct bus_mux *lvds_mux = NULL;
233 if (imx_ldb_ch == &ldb->channel[0])
234 lvds_mux = &ldb->lvds_mux[0];
235 else if (imx_ldb_ch == &ldb->channel[1])
236 lvds_mux = &ldb->lvds_mux[1];
238 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
239 mux << lvds_mux->shift);
242 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
244 drm_panel_enable(imx_ldb_ch->panel);
248 imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
249 struct drm_crtc_state *crtc_state,
250 struct drm_connector_state *connector_state)
252 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
253 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
254 struct imx_ldb *ldb = imx_ldb_ch->ldb;
255 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
256 unsigned long serial_clk;
257 unsigned long di_clk = mode->clock * 1000;
258 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
259 u32 bus_format = imx_ldb_ch->bus_format;
261 if (mode->clock > 170000) {
263 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
265 if (mode->clock > 85000 && !dual) {
267 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
271 serial_clk = 3500UL * mode->clock;
272 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
273 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
275 serial_clk = 7000UL * mode->clock;
276 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
280 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
281 if (imx_ldb_ch == &ldb->channel[0] || dual) {
282 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
283 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
284 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
285 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
287 if (imx_ldb_ch == &ldb->channel[1] || dual) {
288 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
289 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
290 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
291 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
295 struct drm_connector *connector = connector_state->connector;
296 struct drm_display_info *di = &connector->display_info;
298 if (di->num_bus_formats)
299 bus_format = di->bus_formats[0];
301 imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
304 static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
306 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
307 struct imx_ldb *ldb = imx_ldb_ch->ldb;
310 drm_panel_disable(imx_ldb_ch->panel);
312 if (imx_ldb_ch == &ldb->channel[0])
313 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
314 else if (imx_ldb_ch == &ldb->channel[1])
315 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
317 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
319 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
320 clk_disable_unprepare(ldb->clk[0]);
321 clk_disable_unprepare(ldb->clk[1]);
325 const struct bus_mux *lvds_mux = NULL;
327 if (imx_ldb_ch == &ldb->channel[0])
328 lvds_mux = &ldb->lvds_mux[0];
329 else if (imx_ldb_ch == &ldb->channel[1])
330 lvds_mux = &ldb->lvds_mux[1];
332 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
333 mux &= lvds_mux->mask;
334 mux >>= lvds_mux->shift;
336 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
339 /* set display clock mux back to original input clock */
340 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
343 "unable to set di%d parent clock to original parent\n",
346 drm_panel_unprepare(imx_ldb_ch->panel);
349 static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
350 struct drm_crtc_state *crtc_state,
351 struct drm_connector_state *conn_state)
353 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
354 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
355 struct drm_display_info *di = &conn_state->connector->display_info;
356 u32 bus_format = imx_ldb_ch->bus_format;
358 /* Bus format description in DT overrides connector display info. */
359 if (!bus_format && di->num_bus_formats) {
360 bus_format = di->bus_formats[0];
361 imx_crtc_state->bus_flags = di->bus_flags;
363 bus_format = imx_ldb_ch->bus_format;
364 imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
366 switch (bus_format) {
367 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
368 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
370 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
371 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
372 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
378 imx_crtc_state->di_hsync_pin = 2;
379 imx_crtc_state->di_vsync_pin = 3;
385 static const struct drm_connector_funcs imx_ldb_connector_funcs = {
386 .fill_modes = drm_helper_probe_single_connector_modes,
387 .destroy = imx_drm_connector_destroy,
388 .reset = drm_atomic_helper_connector_reset,
389 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
390 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
393 static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
394 .get_modes = imx_ldb_connector_get_modes,
395 .best_encoder = imx_ldb_connector_best_encoder,
398 static const struct drm_encoder_funcs imx_ldb_encoder_funcs = {
399 .destroy = imx_drm_encoder_destroy,
402 static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
403 .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
404 .enable = imx_ldb_encoder_enable,
405 .disable = imx_ldb_encoder_disable,
406 .atomic_check = imx_ldb_encoder_atomic_check,
409 static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
413 snprintf(clkname, sizeof(clkname), "di%d", chno);
414 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
415 if (IS_ERR(ldb->clk[chno]))
416 return PTR_ERR(ldb->clk[chno]);
418 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
419 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
421 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
424 static int imx_ldb_register(struct drm_device *drm,
425 struct imx_ldb_channel *imx_ldb_ch)
427 struct imx_ldb *ldb = imx_ldb_ch->ldb;
428 struct drm_encoder *encoder = &imx_ldb_ch->encoder;
431 ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
435 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
439 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
440 ret = imx_ldb_get_clk(ldb, 1);
445 drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
446 drm_encoder_init(drm, encoder, &imx_ldb_encoder_funcs,
447 DRM_MODE_ENCODER_LVDS, NULL);
449 if (imx_ldb_ch->bridge) {
450 ret = drm_bridge_attach(&imx_ldb_ch->encoder,
451 imx_ldb_ch->bridge, NULL);
453 DRM_ERROR("Failed to initialize bridge with drm\n");
458 * We want to add the connector whenever there is no bridge
459 * that brings its own, not only when there is a panel. For
460 * historical reasons, the ldb driver can also work without
463 drm_connector_helper_add(&imx_ldb_ch->connector,
464 &imx_ldb_connector_helper_funcs);
465 drm_connector_init_with_ddc(drm, &imx_ldb_ch->connector,
466 &imx_ldb_connector_funcs,
467 DRM_MODE_CONNECTOR_LVDS,
469 drm_connector_attach_encoder(&imx_ldb_ch->connector, encoder);
472 if (imx_ldb_ch->panel) {
473 ret = drm_panel_attach(imx_ldb_ch->panel,
474 &imx_ldb_ch->connector);
487 struct imx_ldb_bit_mapping {
490 const char * const mapping;
493 static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
494 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
495 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
496 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
499 static u32 of_get_bus_format(struct device *dev, struct device_node *np)
505 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
509 of_property_read_u32(np, "fsl,data-width", &datawidth);
511 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
512 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
513 datawidth == imx_ldb_bit_mappings[i].datawidth)
514 return imx_ldb_bit_mappings[i].bus_format;
517 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
522 static struct bus_mux imx6q_lvds_mux[2] = {
526 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
530 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
535 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
536 * of_match_device will walk through this list and take the first entry
537 * matching any of its compatible values. Therefore, the more generic
538 * entries (in this case fsl,imx53-ldb) need to be ordered last.
540 static const struct of_device_id imx_ldb_dt_ids[] = {
541 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
542 { .compatible = "fsl,imx53-ldb", .data = NULL, },
545 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
547 static int imx_ldb_panel_ddc(struct device *dev,
548 struct imx_ldb_channel *channel, struct device_node *child)
550 struct device_node *ddc_node;
554 ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
556 channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
557 of_node_put(ddc_node);
559 dev_warn(dev, "failed to get ddc i2c adapter\n");
560 return -EPROBE_DEFER;
565 /* if no DDC available, fallback to hardcoded EDID */
566 dev_dbg(dev, "no ddc available\n");
568 edidp = of_get_property(child, "edid",
571 channel->edid = kmemdup(edidp,
574 } else if (!channel->panel) {
575 /* fallback to display-timings node */
576 ret = of_get_drm_display_mode(child,
581 channel->mode_valid = 1;
587 static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
589 struct drm_device *drm = data;
590 struct device_node *np = dev->of_node;
591 const struct of_device_id *of_id =
592 of_match_device(imx_ldb_dt_ids, dev);
593 struct device_node *child;
594 struct imx_ldb *imx_ldb;
599 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
603 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
604 if (IS_ERR(imx_ldb->regmap)) {
605 dev_err(dev, "failed to get parent regmap\n");
606 return PTR_ERR(imx_ldb->regmap);
609 /* disable LDB by resetting the control register to POR default */
610 regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
615 imx_ldb->lvds_mux = of_id->data;
617 dual = of_property_read_bool(np, "fsl,dual-channel");
619 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
622 * There are three different possible clock mux configurations:
623 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
624 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
625 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
626 * Map them all to di0_sel...di3_sel.
628 for (i = 0; i < 4; i++) {
631 sprintf(clkname, "di%d_sel", i);
632 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
633 if (IS_ERR(imx_ldb->clk_sel[i])) {
634 ret = PTR_ERR(imx_ldb->clk_sel[i]);
635 imx_ldb->clk_sel[i] = NULL;
639 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
644 for_each_child_of_node(np, child) {
645 struct imx_ldb_channel *channel;
648 ret = of_property_read_u32(child, "reg", &i);
649 if (ret || i < 0 || i > 1) {
654 if (!of_device_is_available(child))
658 dev_warn(dev, "dual-channel mode, ignoring second output\n");
662 channel = &imx_ldb->channel[i];
663 channel->ldb = imx_ldb;
667 * The output port is port@4 with an external 4-port mux or
668 * port@2 with the internal 2-port mux.
670 ret = drm_of_find_panel_or_bridge(child,
671 imx_ldb->lvds_mux ? 4 : 2, 0,
672 &channel->panel, &channel->bridge);
673 if (ret && ret != -ENODEV)
676 /* panel ddc only if there is no bridge */
677 if (!channel->bridge) {
678 ret = imx_ldb_panel_ddc(dev, channel, child);
683 bus_format = of_get_bus_format(dev, child);
684 if (bus_format == -EINVAL) {
686 * If no bus format was specified in the device tree,
687 * we can still get it from the connected panel later.
689 if (channel->panel && channel->panel->funcs &&
690 channel->panel->funcs->get_modes)
693 if (bus_format < 0) {
694 dev_err(dev, "could not determine data mapping: %d\n",
699 channel->bus_format = bus_format;
700 channel->child = child;
702 ret = imx_ldb_register(drm, channel);
704 channel->child = NULL;
709 dev_set_drvdata(dev, imx_ldb);
718 static void imx_ldb_unbind(struct device *dev, struct device *master,
721 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
724 for (i = 0; i < 2; i++) {
725 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
728 drm_panel_detach(channel->panel);
730 kfree(channel->edid);
731 i2c_put_adapter(channel->ddc);
735 static const struct component_ops imx_ldb_ops = {
736 .bind = imx_ldb_bind,
737 .unbind = imx_ldb_unbind,
740 static int imx_ldb_probe(struct platform_device *pdev)
742 return component_add(&pdev->dev, &imx_ldb_ops);
745 static int imx_ldb_remove(struct platform_device *pdev)
747 component_del(&pdev->dev, &imx_ldb_ops);
751 static struct platform_driver imx_ldb_driver = {
752 .probe = imx_ldb_probe,
753 .remove = imx_ldb_remove,
755 .of_match_table = imx_ldb_dt_ids,
760 module_platform_driver(imx_ldb_driver);
762 MODULE_DESCRIPTION("i.MX LVDS driver");
763 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
764 MODULE_LICENSE("GPL");
765 MODULE_ALIAS("platform:" DRIVER_NAME);