1 // SPDX-License-Identifier: GPL-2.0
3 // Ingenic JZ47xx KMS driver
5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
8 #include <linux/dma-mapping.h>
9 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
14 #include <drm/drm_atomic.h>
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_bridge.h>
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_drv.h>
20 #include <drm/drm_gem_cma_helper.h>
21 #include <drm/drm_fb_cma_helper.h>
22 #include <drm/drm_fb_helper.h>
23 #include <drm/drm_fourcc.h>
24 #include <drm/drm_gem_framebuffer_helper.h>
25 #include <drm/drm_irq.h>
26 #include <drm/drm_of.h>
27 #include <drm/drm_panel.h>
28 #include <drm/drm_plane.h>
29 #include <drm/drm_plane_helper.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/drm_vblank.h>
33 #define JZ_REG_LCD_CFG 0x00
34 #define JZ_REG_LCD_VSYNC 0x04
35 #define JZ_REG_LCD_HSYNC 0x08
36 #define JZ_REG_LCD_VAT 0x0C
37 #define JZ_REG_LCD_DAH 0x10
38 #define JZ_REG_LCD_DAV 0x14
39 #define JZ_REG_LCD_PS 0x18
40 #define JZ_REG_LCD_CLS 0x1C
41 #define JZ_REG_LCD_SPL 0x20
42 #define JZ_REG_LCD_REV 0x24
43 #define JZ_REG_LCD_CTRL 0x30
44 #define JZ_REG_LCD_STATE 0x34
45 #define JZ_REG_LCD_IID 0x38
46 #define JZ_REG_LCD_DA0 0x40
47 #define JZ_REG_LCD_SA0 0x44
48 #define JZ_REG_LCD_FID0 0x48
49 #define JZ_REG_LCD_CMD0 0x4C
50 #define JZ_REG_LCD_DA1 0x50
51 #define JZ_REG_LCD_SA1 0x54
52 #define JZ_REG_LCD_FID1 0x58
53 #define JZ_REG_LCD_CMD1 0x5C
55 #define JZ_LCD_CFG_SLCD BIT(31)
56 #define JZ_LCD_CFG_PS_DISABLE BIT(23)
57 #define JZ_LCD_CFG_CLS_DISABLE BIT(22)
58 #define JZ_LCD_CFG_SPL_DISABLE BIT(21)
59 #define JZ_LCD_CFG_REV_DISABLE BIT(20)
60 #define JZ_LCD_CFG_HSYNCM BIT(19)
61 #define JZ_LCD_CFG_PCLKM BIT(18)
62 #define JZ_LCD_CFG_INV BIT(17)
63 #define JZ_LCD_CFG_SYNC_DIR BIT(16)
64 #define JZ_LCD_CFG_PS_POLARITY BIT(15)
65 #define JZ_LCD_CFG_CLS_POLARITY BIT(14)
66 #define JZ_LCD_CFG_SPL_POLARITY BIT(13)
67 #define JZ_LCD_CFG_REV_POLARITY BIT(12)
68 #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
69 #define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
70 #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
71 #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
72 #define JZ_LCD_CFG_18_BIT BIT(7)
73 #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
75 #define JZ_LCD_CFG_MODE_GENERIC_16BIT 0
76 #define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7)
77 #define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6)
79 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1
80 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2
81 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3
83 #define JZ_LCD_CFG_MODE_TV_OUT_P 4
84 #define JZ_LCD_CFG_MODE_TV_OUT_I 6
86 #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8
87 #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9
88 #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10
89 #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11
91 #define JZ_LCD_CFG_MODE_8BIT_SERIAL 12
92 #define JZ_LCD_CFG_MODE_LCM 13
94 #define JZ_LCD_VSYNC_VPS_OFFSET 16
95 #define JZ_LCD_VSYNC_VPE_OFFSET 0
97 #define JZ_LCD_HSYNC_HPS_OFFSET 16
98 #define JZ_LCD_HSYNC_HPE_OFFSET 0
100 #define JZ_LCD_VAT_HT_OFFSET 16
101 #define JZ_LCD_VAT_VT_OFFSET 0
103 #define JZ_LCD_DAH_HDS_OFFSET 16
104 #define JZ_LCD_DAH_HDE_OFFSET 0
106 #define JZ_LCD_DAV_VDS_OFFSET 16
107 #define JZ_LCD_DAV_VDE_OFFSET 0
109 #define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
110 #define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
111 #define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
112 #define JZ_LCD_CTRL_RGB555 BIT(27)
113 #define JZ_LCD_CTRL_OFUP BIT(26)
114 #define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
115 #define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
116 #define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
117 #define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
118 #define JZ_LCD_CTRL_EOF_IRQ BIT(13)
119 #define JZ_LCD_CTRL_SOF_IRQ BIT(12)
120 #define JZ_LCD_CTRL_OFU_IRQ BIT(11)
121 #define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
122 #define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
123 #define JZ_LCD_CTRL_DD_IRQ BIT(8)
124 #define JZ_LCD_CTRL_QDD_IRQ BIT(7)
125 #define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
126 #define JZ_LCD_CTRL_LSB_FISRT BIT(5)
127 #define JZ_LCD_CTRL_DISABLE BIT(4)
128 #define JZ_LCD_CTRL_ENABLE BIT(3)
129 #define JZ_LCD_CTRL_BPP_1 0x0
130 #define JZ_LCD_CTRL_BPP_2 0x1
131 #define JZ_LCD_CTRL_BPP_4 0x2
132 #define JZ_LCD_CTRL_BPP_8 0x3
133 #define JZ_LCD_CTRL_BPP_15_16 0x4
134 #define JZ_LCD_CTRL_BPP_18_24 0x5
135 #define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | (0x7 << 0))
137 #define JZ_LCD_CMD_SOF_IRQ BIT(31)
138 #define JZ_LCD_CMD_EOF_IRQ BIT(30)
139 #define JZ_LCD_CMD_ENABLE_PAL BIT(28)
141 #define JZ_LCD_SYNC_MASK 0x3ff
143 #define JZ_LCD_STATE_EOF_IRQ BIT(5)
144 #define JZ_LCD_STATE_SOF_IRQ BIT(4)
145 #define JZ_LCD_STATE_DISABLED BIT(0)
147 struct ingenic_dma_hwdesc {
159 struct drm_device drm;
160 struct drm_plane primary;
161 struct drm_crtc crtc;
162 struct drm_encoder encoder;
166 struct clk *lcd_clk, *pix_clk;
168 struct ingenic_dma_hwdesc *dma_hwdesc;
169 dma_addr_t dma_hwdesc_phys;
174 static const u32 ingenic_drm_primary_formats[] = {
180 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
185 case JZ_REG_LCD_FID0:
186 case JZ_REG_LCD_CMD0:
188 case JZ_REG_LCD_FID1:
189 case JZ_REG_LCD_CMD1:
196 static const struct regmap_config ingenic_drm_regmap_config = {
201 .max_register = JZ_REG_LCD_CMD1,
202 .writeable_reg = ingenic_drm_writeable_reg,
205 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
207 return container_of(drm, struct ingenic_drm, drm);
210 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
212 return container_of(crtc, struct ingenic_drm, crtc);
215 static inline struct ingenic_drm *
216 drm_encoder_get_priv(struct drm_encoder *encoder)
218 return container_of(encoder, struct ingenic_drm, encoder);
221 static inline struct ingenic_drm *drm_plane_get_priv(struct drm_plane *plane)
223 return container_of(plane, struct ingenic_drm, primary);
226 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
227 struct drm_crtc_state *state)
229 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
231 regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
233 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
234 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
237 drm_crtc_vblank_on(crtc);
240 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
241 struct drm_crtc_state *state)
243 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
246 drm_crtc_vblank_off(crtc);
248 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
249 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
251 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
252 var & JZ_LCD_STATE_DISABLED,
256 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
257 struct drm_display_mode *mode)
259 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
261 vpe = mode->vsync_end - mode->vsync_start;
262 vds = mode->vtotal - mode->vsync_start;
263 vde = vds + mode->vdisplay;
264 vt = vde + mode->vsync_start - mode->vdisplay;
266 hpe = mode->hsync_end - mode->hsync_start;
267 hds = mode->htotal - mode->hsync_start;
268 hde = hds + mode->hdisplay;
269 ht = hde + mode->hsync_start - mode->hdisplay;
271 regmap_write(priv->map, JZ_REG_LCD_VSYNC,
272 0 << JZ_LCD_VSYNC_VPS_OFFSET |
273 vpe << JZ_LCD_VSYNC_VPE_OFFSET);
275 regmap_write(priv->map, JZ_REG_LCD_HSYNC,
276 0 << JZ_LCD_HSYNC_HPS_OFFSET |
277 hpe << JZ_LCD_HSYNC_HPE_OFFSET);
279 regmap_write(priv->map, JZ_REG_LCD_VAT,
280 ht << JZ_LCD_VAT_HT_OFFSET |
281 vt << JZ_LCD_VAT_VT_OFFSET);
283 regmap_write(priv->map, JZ_REG_LCD_DAH,
284 hds << JZ_LCD_DAH_HDS_OFFSET |
285 hde << JZ_LCD_DAH_HDE_OFFSET);
286 regmap_write(priv->map, JZ_REG_LCD_DAV,
287 vds << JZ_LCD_DAV_VDS_OFFSET |
288 vde << JZ_LCD_DAV_VDE_OFFSET);
290 if (priv->panel_is_sharp) {
291 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
292 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
293 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
294 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
298 static void ingenic_drm_crtc_update_ctrl(struct ingenic_drm *priv,
299 const struct drm_format_info *finfo)
301 unsigned int ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
303 switch (finfo->format) {
304 case DRM_FORMAT_XRGB1555:
305 ctrl |= JZ_LCD_CTRL_RGB555;
307 case DRM_FORMAT_RGB565:
308 ctrl |= JZ_LCD_CTRL_BPP_15_16;
310 case DRM_FORMAT_XRGB8888:
311 ctrl |= JZ_LCD_CTRL_BPP_18_24;
315 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
316 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16 |
317 JZ_LCD_CTRL_BPP_MASK, ctrl);
320 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
321 struct drm_crtc_state *state)
323 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
326 if (!drm_atomic_crtc_needs_modeset(state))
329 rate = clk_round_rate(priv->pix_clk,
330 state->adjusted_mode.clock * 1000);
337 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
338 struct drm_crtc_state *oldstate)
340 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
341 struct drm_crtc_state *state = crtc->state;
342 struct drm_pending_vblank_event *event = state->event;
343 struct drm_framebuffer *drm_fb = crtc->primary->state->fb;
344 const struct drm_format_info *finfo;
346 if (drm_atomic_crtc_needs_modeset(state)) {
347 finfo = drm_format_info(drm_fb->format->format);
349 ingenic_drm_crtc_update_timings(priv, &state->mode);
350 ingenic_drm_crtc_update_ctrl(priv, finfo);
352 clk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000);
354 regmap_write(priv->map, JZ_REG_LCD_DA0, priv->dma_hwdesc->next);
360 spin_lock_irq(&crtc->dev->event_lock);
361 if (drm_crtc_vblank_get(crtc) == 0)
362 drm_crtc_arm_vblank_event(crtc, event);
364 drm_crtc_send_vblank_event(crtc, event);
365 spin_unlock_irq(&crtc->dev->event_lock);
369 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
370 struct drm_plane_state *oldstate)
372 struct ingenic_drm *priv = drm_plane_get_priv(plane);
373 struct drm_plane_state *state = plane->state;
374 unsigned int width, height, cpp;
377 if (state && state->fb) {
378 addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
379 width = state->src_w >> 16;
380 height = state->src_h >> 16;
381 cpp = state->fb->format->cpp[plane->index];
383 priv->dma_hwdesc->addr = addr;
384 priv->dma_hwdesc->cmd = width * height * cpp / 4;
385 priv->dma_hwdesc->cmd |= JZ_LCD_CMD_EOF_IRQ;
389 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
390 struct drm_crtc_state *crtc_state,
391 struct drm_connector_state *conn_state)
393 struct ingenic_drm *priv = drm_encoder_get_priv(encoder);
394 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
395 struct drm_connector *conn = conn_state->connector;
396 struct drm_display_info *info = &conn->display_info;
399 priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
401 if (priv->panel_is_sharp) {
402 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
404 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
405 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
408 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
409 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
410 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
411 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
412 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
413 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
414 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
415 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
417 if (!priv->panel_is_sharp) {
418 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) {
419 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
420 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
422 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
424 switch (*info->bus_formats) {
425 case MEDIA_BUS_FMT_RGB565_1X16:
426 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
428 case MEDIA_BUS_FMT_RGB666_1X18:
429 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
431 case MEDIA_BUS_FMT_RGB888_1X24:
432 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
434 case MEDIA_BUS_FMT_RGB888_3X8:
435 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
443 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
446 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
447 struct drm_crtc_state *crtc_state,
448 struct drm_connector_state *conn_state)
450 struct drm_display_info *info = &conn_state->connector->display_info;
452 if (info->num_bus_formats != 1)
455 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
458 switch (*info->bus_formats) {
459 case MEDIA_BUS_FMT_RGB565_1X16:
460 case MEDIA_BUS_FMT_RGB666_1X18:
461 case MEDIA_BUS_FMT_RGB888_1X24:
462 case MEDIA_BUS_FMT_RGB888_3X8:
469 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
471 struct ingenic_drm *priv = arg;
474 regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
476 regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
477 JZ_LCD_STATE_EOF_IRQ, 0);
479 if (state & JZ_LCD_STATE_EOF_IRQ)
480 drm_crtc_handle_vblank(&priv->crtc);
485 static void ingenic_drm_release(struct drm_device *drm)
487 struct ingenic_drm *priv = drm_device_get_priv(drm);
489 drm_mode_config_cleanup(drm);
494 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
496 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
498 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
499 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
504 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
506 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
508 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
511 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
513 static struct drm_driver ingenic_drm_driver_data = {
514 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
515 .name = "ingenic-drm",
516 .desc = "DRM module for Ingenic SoCs",
522 .fops = &ingenic_drm_fops,
524 .dumb_create = drm_gem_cma_dumb_create,
525 .gem_free_object_unlocked = drm_gem_cma_free_object,
526 .gem_vm_ops = &drm_gem_cma_vm_ops,
528 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
529 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
530 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
531 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
532 .gem_prime_vmap = drm_gem_cma_prime_vmap,
533 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
534 .gem_prime_mmap = drm_gem_cma_prime_mmap,
536 .irq_handler = ingenic_drm_irq_handler,
537 .release = ingenic_drm_release,
540 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = {
541 .update_plane = drm_atomic_helper_update_plane,
542 .disable_plane = drm_atomic_helper_disable_plane,
543 .reset = drm_atomic_helper_plane_reset,
544 .destroy = drm_plane_cleanup,
546 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
547 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
550 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = {
551 .set_config = drm_atomic_helper_set_config,
552 .page_flip = drm_atomic_helper_page_flip,
553 .reset = drm_atomic_helper_crtc_reset,
554 .destroy = drm_crtc_cleanup,
556 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
557 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
559 .enable_vblank = ingenic_drm_enable_vblank,
560 .disable_vblank = ingenic_drm_disable_vblank,
562 .gamma_set = drm_atomic_helper_legacy_gamma_set,
565 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {
566 .atomic_update = ingenic_drm_plane_atomic_update,
567 .prepare_fb = drm_gem_fb_prepare_fb,
570 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = {
571 .atomic_enable = ingenic_drm_crtc_atomic_enable,
572 .atomic_disable = ingenic_drm_crtc_atomic_disable,
573 .atomic_flush = ingenic_drm_crtc_atomic_flush,
574 .atomic_check = ingenic_drm_crtc_atomic_check,
577 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = {
578 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set,
579 .atomic_check = ingenic_drm_encoder_atomic_check,
582 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = {
583 .fb_create = drm_gem_fb_create,
584 .output_poll_changed = drm_fb_helper_output_poll_changed,
585 .atomic_check = drm_atomic_helper_check,
586 .atomic_commit = drm_atomic_helper_commit,
589 static const struct drm_encoder_funcs ingenic_drm_encoder_funcs = {
590 .destroy = drm_encoder_cleanup,
593 static void ingenic_drm_free_dma_hwdesc(void *d)
595 struct ingenic_drm *priv = d;
597 dma_free_coherent(priv->dev, sizeof(*priv->dma_hwdesc),
598 priv->dma_hwdesc, priv->dma_hwdesc_phys);
601 static int ingenic_drm_probe(struct platform_device *pdev)
603 const struct jz_soc_info *soc_info;
604 struct device *dev = &pdev->dev;
605 struct ingenic_drm *priv;
606 struct clk *parent_clk;
607 struct drm_bridge *bridge;
608 struct drm_panel *panel;
609 struct drm_device *drm;
614 soc_info = of_device_get_match_data(dev);
616 dev_err(dev, "Missing platform data\n");
620 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
626 drm->dev_private = priv;
628 platform_set_drvdata(pdev, priv);
630 ret = devm_drm_dev_init(dev, drm, &ingenic_drm_driver_data);
636 drm_mode_config_init(drm);
637 drm->mode_config.min_width = 0;
638 drm->mode_config.min_height = 0;
639 drm->mode_config.max_width = 800;
640 drm->mode_config.max_height = 600;
641 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
643 base = devm_platform_ioremap_resource(pdev, 0);
645 dev_err(dev, "Failed to get memory resource");
646 return PTR_ERR(base);
649 priv->map = devm_regmap_init_mmio(dev, base,
650 &ingenic_drm_regmap_config);
651 if (IS_ERR(priv->map)) {
652 dev_err(dev, "Failed to create regmap");
653 return PTR_ERR(priv->map);
656 irq = platform_get_irq(pdev, 0);
658 dev_err(dev, "Failed to get platform irq");
662 if (soc_info->needs_dev_clk) {
663 priv->lcd_clk = devm_clk_get(dev, "lcd");
664 if (IS_ERR(priv->lcd_clk)) {
665 dev_err(dev, "Failed to get lcd clock");
666 return PTR_ERR(priv->lcd_clk);
670 priv->pix_clk = devm_clk_get(dev, "lcd_pclk");
671 if (IS_ERR(priv->pix_clk)) {
672 dev_err(dev, "Failed to get pixel clock");
673 return PTR_ERR(priv->pix_clk);
676 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, &panel, &bridge);
678 if (ret != -EPROBE_DEFER)
679 dev_err(dev, "Failed to get panel handle");
684 bridge = devm_drm_panel_bridge_add_typed(dev, panel,
685 DRM_MODE_CONNECTOR_DPI);
687 priv->dma_hwdesc = dma_alloc_coherent(dev, sizeof(*priv->dma_hwdesc),
688 &priv->dma_hwdesc_phys,
690 if (!priv->dma_hwdesc)
693 ret = devm_add_action_or_reset(dev, ingenic_drm_free_dma_hwdesc, priv);
697 priv->dma_hwdesc->next = priv->dma_hwdesc_phys;
698 priv->dma_hwdesc->id = 0xdeafbead;
700 drm_plane_helper_add(&priv->primary, &ingenic_drm_plane_helper_funcs);
702 ret = drm_universal_plane_init(drm, &priv->primary,
703 0, &ingenic_drm_primary_plane_funcs,
704 ingenic_drm_primary_formats,
705 ARRAY_SIZE(ingenic_drm_primary_formats),
706 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
708 dev_err(dev, "Failed to register primary plane: %i", ret);
712 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs);
714 ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->primary,
715 NULL, &ingenic_drm_crtc_funcs, NULL);
717 dev_err(dev, "Failed to init CRTC: %i", ret);
721 priv->encoder.possible_crtcs = 1;
723 drm_encoder_helper_add(&priv->encoder,
724 &ingenic_drm_encoder_helper_funcs);
726 ret = drm_encoder_init(drm, &priv->encoder, &ingenic_drm_encoder_funcs,
727 DRM_MODE_ENCODER_DPI, NULL);
729 dev_err(dev, "Failed to init encoder: %i", ret);
733 ret = drm_bridge_attach(&priv->encoder, bridge, NULL);
735 dev_err(dev, "Unable to attach bridge");
739 ret = drm_irq_install(drm, irq);
741 dev_err(dev, "Unable to install IRQ handler");
745 ret = drm_vblank_init(drm, 1);
747 dev_err(dev, "Failed calling drm_vblank_init()");
751 drm_mode_config_reset(drm);
753 ret = clk_prepare_enable(priv->pix_clk);
755 dev_err(dev, "Unable to start pixel clock");
760 parent_clk = clk_get_parent(priv->lcd_clk);
761 parent_rate = clk_get_rate(parent_clk);
763 /* LCD Device clock must be 3x the pixel clock for STN panels,
764 * or 1.5x the pixel clock for TFT panels. To avoid having to
765 * check for the LCD device clock everytime we do a mode change,
766 * we set the LCD device clock to the highest rate possible.
768 ret = clk_set_rate(priv->lcd_clk, parent_rate);
770 dev_err(dev, "Unable to set LCD clock rate");
771 goto err_pixclk_disable;
774 ret = clk_prepare_enable(priv->lcd_clk);
776 dev_err(dev, "Unable to start lcd clock");
777 goto err_pixclk_disable;
781 ret = drm_dev_register(drm, 0);
783 dev_err(dev, "Failed to register DRM driver");
784 goto err_devclk_disable;
787 ret = drm_fbdev_generic_setup(drm, 32);
789 dev_warn(dev, "Unable to start fbdev emulation: %i", ret);
795 clk_disable_unprepare(priv->lcd_clk);
797 clk_disable_unprepare(priv->pix_clk);
801 static int ingenic_drm_remove(struct platform_device *pdev)
803 struct ingenic_drm *priv = platform_get_drvdata(pdev);
806 clk_disable_unprepare(priv->lcd_clk);
807 clk_disable_unprepare(priv->pix_clk);
809 drm_dev_unregister(&priv->drm);
810 drm_atomic_helper_shutdown(&priv->drm);
815 static const struct jz_soc_info jz4740_soc_info = {
816 .needs_dev_clk = true,
819 static const struct jz_soc_info jz4725b_soc_info = {
820 .needs_dev_clk = false,
823 static const struct of_device_id ingenic_drm_of_match[] = {
824 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info },
825 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info },
829 static struct platform_driver ingenic_drm_driver = {
831 .name = "ingenic-drm",
832 .of_match_table = of_match_ptr(ingenic_drm_of_match),
834 .probe = ingenic_drm_probe,
835 .remove = ingenic_drm_remove,
837 module_platform_driver(ingenic_drm_driver);
839 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
840 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n");
841 MODULE_LICENSE("GPL v2");