drivers/gpu/drm/ingenic/ingenic-drm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Ingenic JZ47xx KMS driver
   4 //
   5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
   6
   7 #include <linux/clk.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/regmap.h>
  13
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_bridge.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_drv.h>
  20 #include <drm/drm_gem_cma_helper.h>
  21 #include <drm/drm_fb_cma_helper.h>
  22 #include <drm/drm_fb_helper.h>
  23 #include <drm/drm_fourcc.h>
  24 #include <drm/drm_gem_framebuffer_helper.h>
  25 #include <drm/drm_irq.h>
  26 #include <drm/drm_of.h>
  27 #include <drm/drm_panel.h>
  28 #include <drm/drm_plane.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include <drm/drm_probe_helper.h>
  31 #include <drm/drm_vblank.h>
  32
  33 #define JZ_REG_LCD_CFG                          0x00
  34 #define JZ_REG_LCD_VSYNC                        0x04
  35 #define JZ_REG_LCD_HSYNC                        0x08
  36 #define JZ_REG_LCD_VAT                          0x0C
  37 #define JZ_REG_LCD_DAH                          0x10
  38 #define JZ_REG_LCD_DAV                          0x14
  39 #define JZ_REG_LCD_PS                           0x18
  40 #define JZ_REG_LCD_CLS                          0x1C
  41 #define JZ_REG_LCD_SPL                          0x20
  42 #define JZ_REG_LCD_REV                          0x24
  43 #define JZ_REG_LCD_CTRL                         0x30
  44 #define JZ_REG_LCD_STATE                        0x34
  45 #define JZ_REG_LCD_IID                          0x38
  46 #define JZ_REG_LCD_DA0                          0x40
  47 #define JZ_REG_LCD_SA0                          0x44
  48 #define JZ_REG_LCD_FID0                         0x48
  49 #define JZ_REG_LCD_CMD0                         0x4C
  50 #define JZ_REG_LCD_DA1                          0x50
  51 #define JZ_REG_LCD_SA1                          0x54
  52 #define JZ_REG_LCD_FID1                         0x58
  53 #define JZ_REG_LCD_CMD1                         0x5C
  54
  55 #define JZ_LCD_CFG_SLCD                         BIT(31)
  56 #define JZ_LCD_CFG_PS_DISABLE                   BIT(23)
  57 #define JZ_LCD_CFG_CLS_DISABLE                  BIT(22)
  58 #define JZ_LCD_CFG_SPL_DISABLE                  BIT(21)
  59 #define JZ_LCD_CFG_REV_DISABLE                  BIT(20)
  60 #define JZ_LCD_CFG_HSYNCM                       BIT(19)
  61 #define JZ_LCD_CFG_PCLKM                        BIT(18)
  62 #define JZ_LCD_CFG_INV                          BIT(17)
  63 #define JZ_LCD_CFG_SYNC_DIR                     BIT(16)
  64 #define JZ_LCD_CFG_PS_POLARITY                  BIT(15)
  65 #define JZ_LCD_CFG_CLS_POLARITY                 BIT(14)
  66 #define JZ_LCD_CFG_SPL_POLARITY                 BIT(13)
  67 #define JZ_LCD_CFG_REV_POLARITY                 BIT(12)
  68 #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW             BIT(11)
  69 #define JZ_LCD_CFG_PCLK_FALLING_EDGE            BIT(10)
  70 #define JZ_LCD_CFG_DE_ACTIVE_LOW                BIT(9)
  71 #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW             BIT(8)
  72 #define JZ_LCD_CFG_18_BIT                       BIT(7)
  73 #define JZ_LCD_CFG_PDW                          (BIT(5) | BIT(4))
  74
  75 #define JZ_LCD_CFG_MODE_GENERIC_16BIT           0
  76 #define JZ_LCD_CFG_MODE_GENERIC_18BIT           BIT(7)
  77 #define JZ_LCD_CFG_MODE_GENERIC_24BIT           BIT(6)
  78
  79 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1           1
  80 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2           2
  81 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3           3
  82
  83 #define JZ_LCD_CFG_MODE_TV_OUT_P                4
  84 #define JZ_LCD_CFG_MODE_TV_OUT_I                6
  85
  86 #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN        8
  87 #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN   9
  88 #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN          10
  89 #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN     11
  90
  91 #define JZ_LCD_CFG_MODE_8BIT_SERIAL             12
  92 #define JZ_LCD_CFG_MODE_LCM                     13
  93
  94 #define JZ_LCD_VSYNC_VPS_OFFSET                 16
  95 #define JZ_LCD_VSYNC_VPE_OFFSET                 0
  96
  97 #define JZ_LCD_HSYNC_HPS_OFFSET                 16
  98 #define JZ_LCD_HSYNC_HPE_OFFSET                 0
  99
 100 #define JZ_LCD_VAT_HT_OFFSET                    16
 101 #define JZ_LCD_VAT_VT_OFFSET                    0
 102
 103 #define JZ_LCD_DAH_HDS_OFFSET                   16
 104 #define JZ_LCD_DAH_HDE_OFFSET                   0
 105
 106 #define JZ_LCD_DAV_VDS_OFFSET                   16
 107 #define JZ_LCD_DAV_VDE_OFFSET                   0
 108
 109 #define JZ_LCD_CTRL_BURST_4                     (0x0 << 28)
 110 #define JZ_LCD_CTRL_BURST_8                     (0x1 << 28)
 111 #define JZ_LCD_CTRL_BURST_16                    (0x2 << 28)
 112 #define JZ_LCD_CTRL_RGB555                      BIT(27)
 113 #define JZ_LCD_CTRL_OFUP                        BIT(26)
 114 #define JZ_LCD_CTRL_FRC_GRAYSCALE_16            (0x0 << 24)
 115 #define JZ_LCD_CTRL_FRC_GRAYSCALE_4             (0x1 << 24)
 116 #define JZ_LCD_CTRL_FRC_GRAYSCALE_2             (0x2 << 24)
 117 #define JZ_LCD_CTRL_PDD_MASK                    (0xff << 16)
 118 #define JZ_LCD_CTRL_EOF_IRQ                     BIT(13)
 119 #define JZ_LCD_CTRL_SOF_IRQ                     BIT(12)
 120 #define JZ_LCD_CTRL_OFU_IRQ                     BIT(11)
 121 #define JZ_LCD_CTRL_IFU0_IRQ                    BIT(10)
 122 #define JZ_LCD_CTRL_IFU1_IRQ                    BIT(9)
 123 #define JZ_LCD_CTRL_DD_IRQ                      BIT(8)
 124 #define JZ_LCD_CTRL_QDD_IRQ                     BIT(7)
 125 #define JZ_LCD_CTRL_REVERSE_ENDIAN              BIT(6)
 126 #define JZ_LCD_CTRL_LSB_FISRT                   BIT(5)
 127 #define JZ_LCD_CTRL_DISABLE                     BIT(4)
 128 #define JZ_LCD_CTRL_ENABLE                      BIT(3)
 129 #define JZ_LCD_CTRL_BPP_1                       0x0
 130 #define JZ_LCD_CTRL_BPP_2                       0x1
 131 #define JZ_LCD_CTRL_BPP_4                       0x2
 132 #define JZ_LCD_CTRL_BPP_8                       0x3
 133 #define JZ_LCD_CTRL_BPP_15_16                   0x4
 134 #define JZ_LCD_CTRL_BPP_18_24                   0x5
 135 #define JZ_LCD_CTRL_BPP_MASK                    (JZ_LCD_CTRL_RGB555 | (0x7 << 0))
 136
 137 #define JZ_LCD_CMD_SOF_IRQ                      BIT(31)
 138 #define JZ_LCD_CMD_EOF_IRQ                      BIT(30)
 139 #define JZ_LCD_CMD_ENABLE_PAL                   BIT(28)
 140
 141 #define JZ_LCD_SYNC_MASK                        0x3ff
 142
 143 #define JZ_LCD_STATE_EOF_IRQ                    BIT(5)
 144 #define JZ_LCD_STATE_SOF_IRQ                    BIT(4)
 145 #define JZ_LCD_STATE_DISABLED                   BIT(0)
 146
 147 struct ingenic_dma_hwdesc {
 148         u32 next;
 149         u32 addr;
 150         u32 id;
 151         u32 cmd;
 152 } __packed;
 153
 154 struct jz_soc_info {
 155         bool needs_dev_clk;
 156 };
 157
 158 struct ingenic_drm {
 159         struct drm_device drm;
 160         struct drm_plane primary;
 161         struct drm_crtc crtc;
 162         struct drm_encoder encoder;
 163
 164         struct device *dev;
 165         struct regmap *map;
 166         struct clk *lcd_clk, *pix_clk;
 167
 168         struct ingenic_dma_hwdesc *dma_hwdesc;
 169         dma_addr_t dma_hwdesc_phys;
 170
 171         bool panel_is_sharp;
 172 };
 173
 174 static const u32 ingenic_drm_primary_formats[] = {
 175         DRM_FORMAT_XRGB1555,
 176         DRM_FORMAT_RGB565,
 177         DRM_FORMAT_XRGB8888,
 178 };
 179
 180 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
 181 {
 182         switch (reg) {
 183         case JZ_REG_LCD_IID:
 184         case JZ_REG_LCD_SA0:
 185         case JZ_REG_LCD_FID0:
 186         case JZ_REG_LCD_CMD0:
 187         case JZ_REG_LCD_SA1:
 188         case JZ_REG_LCD_FID1:
 189         case JZ_REG_LCD_CMD1:
 190                 return false;
 191         default:
 192                 return true;
 193         }
 194 }
 195
 196 static const struct regmap_config ingenic_drm_regmap_config = {
 197         .reg_bits = 32,
 198         .val_bits = 32,
 199         .reg_stride = 4,
 200
 201         .max_register = JZ_REG_LCD_CMD1,
 202         .writeable_reg = ingenic_drm_writeable_reg,
 203 };
 204
 205 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
 206 {
 207         return container_of(drm, struct ingenic_drm, drm);
 208 }
 209
 210 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
 211 {
 212         return container_of(crtc, struct ingenic_drm, crtc);
 213 }
 214
 215 static inline struct ingenic_drm *
 216 drm_encoder_get_priv(struct drm_encoder *encoder)
 217 {
 218         return container_of(encoder, struct ingenic_drm, encoder);
 219 }
 220
 221 static inline struct ingenic_drm *drm_plane_get_priv(struct drm_plane *plane)
 222 {
 223         return container_of(plane, struct ingenic_drm, primary);
 224 }
 225
 226 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 227                                            struct drm_crtc_state *state)
 228 {
 229         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 230
 231         regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
 232
 233         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 234                            JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
 235                            JZ_LCD_CTRL_ENABLE);
 236
 237         drm_crtc_vblank_on(crtc);
 238 }
 239
 240 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 241                                             struct drm_crtc_state *state)
 242 {
 243         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 244         unsigned int var;
 245
 246         drm_crtc_vblank_off(crtc);
 247
 248         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 249                            JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
 250
 251         regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
 252                                  var & JZ_LCD_STATE_DISABLED,
 253                                  1000, 0);
 254 }
 255
 256 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
 257                                             struct drm_display_mode *mode)
 258 {
 259         unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
 260
 261         vpe = mode->vsync_end - mode->vsync_start;
 262         vds = mode->vtotal - mode->vsync_start;
 263         vde = vds + mode->vdisplay;
 264         vt = vde + mode->vsync_start - mode->vdisplay;
 265
 266         hpe = mode->hsync_end - mode->hsync_start;
 267         hds = mode->htotal - mode->hsync_start;
 268         hde = hds + mode->hdisplay;
 269         ht = hde + mode->hsync_start - mode->hdisplay;
 270
 271         regmap_write(priv->map, JZ_REG_LCD_VSYNC,
 272                      0 << JZ_LCD_VSYNC_VPS_OFFSET |
 273                      vpe << JZ_LCD_VSYNC_VPE_OFFSET);
 274
 275         regmap_write(priv->map, JZ_REG_LCD_HSYNC,
 276                      0 << JZ_LCD_HSYNC_HPS_OFFSET |
 277                      hpe << JZ_LCD_HSYNC_HPE_OFFSET);
 278
 279         regmap_write(priv->map, JZ_REG_LCD_VAT,
 280                      ht << JZ_LCD_VAT_HT_OFFSET |
 281                      vt << JZ_LCD_VAT_VT_OFFSET);
 282
 283         regmap_write(priv->map, JZ_REG_LCD_DAH,
 284                      hds << JZ_LCD_DAH_HDS_OFFSET |
 285                      hde << JZ_LCD_DAH_HDE_OFFSET);
 286         regmap_write(priv->map, JZ_REG_LCD_DAV,
 287                      vds << JZ_LCD_DAV_VDS_OFFSET |
 288                      vde << JZ_LCD_DAV_VDE_OFFSET);
 289
 290         if (priv->panel_is_sharp) {
 291                 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
 292                 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
 293                 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
 294                 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
 295         }
 296 }
 297
 298 static void ingenic_drm_crtc_update_ctrl(struct ingenic_drm *priv,
 299                                          const struct drm_format_info *finfo)
 300 {
 301         unsigned int ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
 302
 303         switch (finfo->format) {
 304         case DRM_FORMAT_XRGB1555:
 305                 ctrl |= JZ_LCD_CTRL_RGB555;
 306                 /* fall-through */
 307         case DRM_FORMAT_RGB565:
 308                 ctrl |= JZ_LCD_CTRL_BPP_15_16;
 309                 break;
 310         case DRM_FORMAT_XRGB8888:
 311                 ctrl |= JZ_LCD_CTRL_BPP_18_24;
 312                 break;
 313         }
 314
 315         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 316                            JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16 |
 317                            JZ_LCD_CTRL_BPP_MASK, ctrl);
 318 }
 319
 320 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
 321                                          struct drm_crtc_state *state)
 322 {
 323         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 324         long rate;
 325
 326         if (!drm_atomic_crtc_needs_modeset(state))
 327                 return 0;
 328
 329         rate = clk_round_rate(priv->pix_clk,
 330                               state->adjusted_mode.clock * 1000);
 331         if (rate < 0)
 332                 return rate;
 333
 334         return 0;
 335 }
 336
 337 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 338                                           struct drm_crtc_state *oldstate)
 339 {
 340         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 341         struct drm_crtc_state *state = crtc->state;
 342         struct drm_pending_vblank_event *event = state->event;
 343         struct drm_framebuffer *drm_fb = crtc->primary->state->fb;
 344         const struct drm_format_info *finfo;
 345
 346         if (drm_atomic_crtc_needs_modeset(state)) {
 347                 finfo = drm_format_info(drm_fb->format->format);
 348
 349                 ingenic_drm_crtc_update_timings(priv, &state->mode);
 350                 ingenic_drm_crtc_update_ctrl(priv, finfo);
 351
 352                 clk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000);
 353
 354                 regmap_write(priv->map, JZ_REG_LCD_DA0, priv->dma_hwdesc->next);
 355         }
 356
 357         if (event) {
 358                 state->event = NULL;
 359
 360                 spin_lock_irq(&crtc->dev->event_lock);
 361                 if (drm_crtc_vblank_get(crtc) == 0)
 362                         drm_crtc_arm_vblank_event(crtc, event);
 363                 else
 364                         drm_crtc_send_vblank_event(crtc, event);
 365                 spin_unlock_irq(&crtc->dev->event_lock);
 366         }
 367 }
 368
 369 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
 370                                             struct drm_plane_state *oldstate)
 371 {
 372         struct ingenic_drm *priv = drm_plane_get_priv(plane);
 373         struct drm_plane_state *state = plane->state;
 374         unsigned int width, height, cpp;
 375
 376         width = state->crtc->state->adjusted_mode.hdisplay;
 377         height = state->crtc->state->adjusted_mode.vdisplay;
 378         cpp = state->fb->format->cpp[plane->index];
 379
 380         priv->dma_hwdesc->addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
 381         priv->dma_hwdesc->cmd = width * height * cpp / 4;
 382         priv->dma_hwdesc->cmd |= JZ_LCD_CMD_EOF_IRQ;
 383 }
 384
 385 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
 386                                                 struct drm_crtc_state *crtc_state,
 387                                                 struct drm_connector_state *conn_state)
 388 {
 389         struct ingenic_drm *priv = drm_encoder_get_priv(encoder);
 390         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 391         struct drm_connector *conn = conn_state->connector;
 392         struct drm_display_info *info = &conn->display_info;
 393         unsigned int cfg;
 394
 395         priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
 396
 397         if (priv->panel_is_sharp) {
 398                 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
 399         } else {
 400                 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
 401                     | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
 402         }
 403
 404         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 405                 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
 406         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 407                 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
 408         if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
 409                 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
 410         if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
 411                 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
 412
 413         if (!priv->panel_is_sharp) {
 414                 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) {
 415                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 416                                 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
 417                         else
 418                                 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
 419                 } else {
 420                         switch (*info->bus_formats) {
 421                         case MEDIA_BUS_FMT_RGB565_1X16:
 422                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
 423                                 break;
 424                         case MEDIA_BUS_FMT_RGB666_1X18:
 425                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
 426                                 break;
 427                         case MEDIA_BUS_FMT_RGB888_1X24:
 428                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
 429                                 break;
 430                         case MEDIA_BUS_FMT_RGB888_3X8:
 431                                 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
 432                                 break;
 433                         default:
 434                                 break;
 435                         }
 436                 }
 437         }
 438
 439         regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
 440 }
 441
 442 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
 443                                             struct drm_crtc_state *crtc_state,
 444                                             struct drm_connector_state *conn_state)
 445 {
 446         struct drm_display_info *info = &conn_state->connector->display_info;
 447
 448         if (info->num_bus_formats != 1)
 449                 return -EINVAL;
 450
 451         if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
 452                 return 0;
 453
 454         switch (*info->bus_formats) {
 455         case MEDIA_BUS_FMT_RGB565_1X16:
 456         case MEDIA_BUS_FMT_RGB666_1X18:
 457         case MEDIA_BUS_FMT_RGB888_1X24:
 458         case MEDIA_BUS_FMT_RGB888_3X8:
 459                 return 0;
 460         default:
 461                 return -EINVAL;
 462         }
 463 }
 464
 465 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
 466 {
 467         struct ingenic_drm *priv = arg;
 468         unsigned int state;
 469
 470         regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
 471
 472         regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
 473                            JZ_LCD_STATE_EOF_IRQ, 0);
 474
 475         if (state & JZ_LCD_STATE_EOF_IRQ)
 476                 drm_crtc_handle_vblank(&priv->crtc);
 477
 478         return IRQ_HANDLED;
 479 }
 480
 481 static void ingenic_drm_release(struct drm_device *drm)
 482 {
 483         struct ingenic_drm *priv = drm_device_get_priv(drm);
 484
 485         drm_mode_config_cleanup(drm);
 486         drm_dev_fini(drm);
 487         kfree(priv);
 488 }
 489
 490 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
 491 {
 492         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 493
 494         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 495                            JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
 496
 497         return 0;
 498 }
 499
 500 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
 501 {
 502         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 503
 504         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
 505 }
 506
 507 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
 508
 509 static struct drm_driver ingenic_drm_driver_data = {
 510         .driver_features        = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
 511         .name                   = "ingenic-drm",
 512         .desc                   = "DRM module for Ingenic SoCs",
 513         .date                   = "20190422",
 514         .major                  = 1,
 515         .minor                  = 0,
 516         .patchlevel             = 0,
 517
 518         .fops                   = &ingenic_drm_fops,
 519
 520         .dumb_create            = drm_gem_cma_dumb_create,
 521         .gem_free_object_unlocked = drm_gem_cma_free_object,
 522         .gem_vm_ops             = &drm_gem_cma_vm_ops,
 523
 524         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
 525         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
 526         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 527         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 528         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
 529         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
 530         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
 531
 532         .irq_handler            = ingenic_drm_irq_handler,
 533         .release                = ingenic_drm_release,
 534 };
 535
 536 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = {
 537         .update_plane           = drm_atomic_helper_update_plane,
 538         .disable_plane          = drm_atomic_helper_disable_plane,
 539         .reset                  = drm_atomic_helper_plane_reset,
 540         .destroy                = drm_plane_cleanup,
 541
 542         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 543         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 544 };
 545
 546 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = {
 547         .set_config             = drm_atomic_helper_set_config,
 548         .page_flip              = drm_atomic_helper_page_flip,
 549         .reset                  = drm_atomic_helper_crtc_reset,
 550         .destroy                = drm_crtc_cleanup,
 551
 552         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 553         .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
 554
 555         .enable_vblank          = ingenic_drm_enable_vblank,
 556         .disable_vblank         = ingenic_drm_disable_vblank,
 557
 558         .gamma_set              = drm_atomic_helper_legacy_gamma_set,
 559 };
 560
 561 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {
 562         .atomic_update          = ingenic_drm_plane_atomic_update,
 563         .prepare_fb             = drm_gem_fb_prepare_fb,
 564 };
 565
 566 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = {
 567         .atomic_enable          = ingenic_drm_crtc_atomic_enable,
 568         .atomic_disable         = ingenic_drm_crtc_atomic_disable,
 569         .atomic_flush           = ingenic_drm_crtc_atomic_flush,
 570         .atomic_check           = ingenic_drm_crtc_atomic_check,
 571 };
 572
 573 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = {
 574         .atomic_mode_set        = ingenic_drm_encoder_atomic_mode_set,
 575         .atomic_check           = ingenic_drm_encoder_atomic_check,
 576 };
 577
 578 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = {
 579         .fb_create              = drm_gem_fb_create,
 580         .output_poll_changed    = drm_fb_helper_output_poll_changed,
 581         .atomic_check           = drm_atomic_helper_check,
 582         .atomic_commit          = drm_atomic_helper_commit,
 583 };
 584
 585 static const struct drm_encoder_funcs ingenic_drm_encoder_funcs = {
 586         .destroy                = drm_encoder_cleanup,
 587 };
 588
 589 static void ingenic_drm_free_dma_hwdesc(void *d)
 590 {
 591         struct ingenic_drm *priv = d;
 592
 593         dma_free_coherent(priv->dev, sizeof(*priv->dma_hwdesc),
 594                           priv->dma_hwdesc, priv->dma_hwdesc_phys);
 595 }
 596
 597 static int ingenic_drm_probe(struct platform_device *pdev)
 598 {
 599         const struct jz_soc_info *soc_info;
 600         struct device *dev = &pdev->dev;
 601         struct ingenic_drm *priv;
 602         struct clk *parent_clk;
 603         struct drm_bridge *bridge;
 604         struct drm_panel *panel;
 605         struct drm_device *drm;
 606         void __iomem *base;
 607         long parent_rate;
 608         int ret, irq;
 609
 610         soc_info = of_device_get_match_data(dev);
 611         if (!soc_info) {
 612                 dev_err(dev, "Missing platform data\n");
 613                 return -EINVAL;
 614         }
 615
 616         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 617         if (!priv)
 618                 return -ENOMEM;
 619
 620         priv->dev = dev;
 621         drm = &priv->drm;
 622         drm->dev_private = priv;
 623
 624         platform_set_drvdata(pdev, priv);
 625
 626         ret = devm_drm_dev_init(dev, drm, &ingenic_drm_driver_data);
 627         if (ret) {
 628                 kfree(priv);
 629                 return ret;
 630         }
 631
 632         drm_mode_config_init(drm);
 633         drm->mode_config.min_width = 0;
 634         drm->mode_config.min_height = 0;
 635         drm->mode_config.max_width = 800;
 636         drm->mode_config.max_height = 600;
 637         drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
 638
 639         base = devm_platform_ioremap_resource(pdev, 0);
 640         if (IS_ERR(base)) {
 641                 dev_err(dev, "Failed to get memory resource");
 642                 return PTR_ERR(base);
 643         }
 644
 645         priv->map = devm_regmap_init_mmio(dev, base,
 646                                           &ingenic_drm_regmap_config);
 647         if (IS_ERR(priv->map)) {
 648                 dev_err(dev, "Failed to create regmap");
 649                 return PTR_ERR(priv->map);
 650         }
 651
 652         irq = platform_get_irq(pdev, 0);
 653         if (irq < 0) {
 654                 dev_err(dev, "Failed to get platform irq");
 655                 return irq;
 656         }
 657
 658         if (soc_info->needs_dev_clk) {
 659                 priv->lcd_clk = devm_clk_get(dev, "lcd");
 660                 if (IS_ERR(priv->lcd_clk)) {
 661                         dev_err(dev, "Failed to get lcd clock");
 662                         return PTR_ERR(priv->lcd_clk);
 663                 }
 664         }
 665
 666         priv->pix_clk = devm_clk_get(dev, "lcd_pclk");
 667         if (IS_ERR(priv->pix_clk)) {
 668                 dev_err(dev, "Failed to get pixel clock");
 669                 return PTR_ERR(priv->pix_clk);
 670         }
 671
 672         ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, &panel, &bridge);
 673         if (ret) {
 674                 if (ret != -EPROBE_DEFER)
 675                         dev_err(dev, "Failed to get panel handle");
 676                 return ret;
 677         }
 678
 679         if (panel)
 680                 bridge = devm_drm_panel_bridge_add(dev, panel,
 681                                                    DRM_MODE_CONNECTOR_DPI);
 682
 683         priv->dma_hwdesc = dma_alloc_coherent(dev, sizeof(*priv->dma_hwdesc),
 684                                               &priv->dma_hwdesc_phys,
 685                                               GFP_KERNEL);
 686         if (!priv->dma_hwdesc)
 687                 return -ENOMEM;
 688
 689         ret = devm_add_action_or_reset(dev, ingenic_drm_free_dma_hwdesc, priv);
 690         if (ret)
 691                 return ret;
 692
 693         priv->dma_hwdesc->next = priv->dma_hwdesc_phys;
 694         priv->dma_hwdesc->id = 0xdeafbead;
 695
 696         drm_plane_helper_add(&priv->primary, &ingenic_drm_plane_helper_funcs);
 697
 698         ret = drm_universal_plane_init(drm, &priv->primary,
 699                                        0, &ingenic_drm_primary_plane_funcs,
 700                                        ingenic_drm_primary_formats,
 701                                        ARRAY_SIZE(ingenic_drm_primary_formats),
 702                                        NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
 703         if (ret) {
 704                 dev_err(dev, "Failed to register primary plane: %i", ret);
 705                 return ret;
 706         }
 707
 708         drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs);
 709
 710         ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->primary,
 711                                         NULL, &ingenic_drm_crtc_funcs, NULL);
 712         if (ret) {
 713                 dev_err(dev, "Failed to init CRTC: %i", ret);
 714                 return ret;
 715         }
 716
 717         priv->encoder.possible_crtcs = 1;
 718
 719         drm_encoder_helper_add(&priv->encoder,
 720                                &ingenic_drm_encoder_helper_funcs);
 721
 722         ret = drm_encoder_init(drm, &priv->encoder, &ingenic_drm_encoder_funcs,
 723                                DRM_MODE_ENCODER_DPI, NULL);
 724         if (ret) {
 725                 dev_err(dev, "Failed to init encoder: %i", ret);
 726                 return ret;
 727         }
 728
 729         ret = drm_bridge_attach(&priv->encoder, bridge, NULL);
 730         if (ret) {
 731                 dev_err(dev, "Unable to attach bridge");
 732                 return ret;
 733         }
 734
 735         ret = drm_irq_install(drm, irq);
 736         if (ret) {
 737                 dev_err(dev, "Unable to install IRQ handler");
 738                 return ret;
 739         }
 740
 741         ret = drm_vblank_init(drm, 1);
 742         if (ret) {
 743                 dev_err(dev, "Failed calling drm_vblank_init()");
 744                 return ret;
 745         }
 746
 747         drm_mode_config_reset(drm);
 748
 749         ret = clk_prepare_enable(priv->pix_clk);
 750         if (ret) {
 751                 dev_err(dev, "Unable to start pixel clock");
 752                 return ret;
 753         }
 754
 755         if (priv->lcd_clk) {
 756                 parent_clk = clk_get_parent(priv->lcd_clk);
 757                 parent_rate = clk_get_rate(parent_clk);
 758
 759                 /* LCD Device clock must be 3x the pixel clock for STN panels,
 760                  * or 1.5x the pixel clock for TFT panels. To avoid having to
 761                  * check for the LCD device clock everytime we do a mode change,
 762                  * we set the LCD device clock to the highest rate possible.
 763                  */
 764                 ret = clk_set_rate(priv->lcd_clk, parent_rate);
 765                 if (ret) {
 766                         dev_err(dev, "Unable to set LCD clock rate");
 767                         goto err_pixclk_disable;
 768                 }
 769
 770                 ret = clk_prepare_enable(priv->lcd_clk);
 771                 if (ret) {
 772                         dev_err(dev, "Unable to start lcd clock");
 773                         goto err_pixclk_disable;
 774                 }
 775         }
 776
 777         ret = drm_dev_register(drm, 0);
 778         if (ret) {
 779                 dev_err(dev, "Failed to register DRM driver");
 780                 goto err_devclk_disable;
 781         }
 782
 783         ret = drm_fbdev_generic_setup(drm, 32);
 784         if (ret)
 785                 dev_warn(dev, "Unable to start fbdev emulation: %i", ret);
 786
 787         return 0;
 788
 789 err_devclk_disable:
 790         if (priv->lcd_clk)
 791                 clk_disable_unprepare(priv->lcd_clk);
 792 err_pixclk_disable:
 793         clk_disable_unprepare(priv->pix_clk);
 794         return ret;
 795 }
 796
 797 static int ingenic_drm_remove(struct platform_device *pdev)
 798 {
 799         struct ingenic_drm *priv = platform_get_drvdata(pdev);
 800
 801         if (priv->lcd_clk)
 802                 clk_disable_unprepare(priv->lcd_clk);
 803         clk_disable_unprepare(priv->pix_clk);
 804
 805         drm_dev_unregister(&priv->drm);
 806         drm_atomic_helper_shutdown(&priv->drm);
 807
 808         return 0;
 809 }
 810
 811 static const struct jz_soc_info jz4740_soc_info = {
 812         .needs_dev_clk = true,
 813 };
 814
 815 static const struct jz_soc_info jz4725b_soc_info = {
 816         .needs_dev_clk = false,
 817 };
 818
 819 static const struct of_device_id ingenic_drm_of_match[] = {
 820         { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info },
 821         { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info },
 822         { /* sentinel */ },
 823 };
 824
 825 static struct platform_driver ingenic_drm_driver = {
 826         .driver = {
 827                 .name = "ingenic-drm",
 828                 .of_match_table = of_match_ptr(ingenic_drm_of_match),
 829         },
 830         .probe = ingenic_drm_probe,
 831         .remove = ingenic_drm_remove,
 832 };
 833 module_platform_driver(ingenic_drm_driver);
 834
 835 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
 836 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n");
 837 MODULE_LICENSE("GPL v2");