2 * Copyright (c) 2015 MediaTek Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_crtc_helper.h>
17 #include <drm/drm_mipi_dsi.h>
18 #include <drm/drm_panel.h>
19 #include <linux/clk.h>
20 #include <linux/component.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_graph.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26 #include <video/videomode.h>
28 #include "mtk_drm_ddp_comp.h"
30 #define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
31 #define DSI_HOST_FIFO_DEPTH 64
33 #define DSI_START 0x00
35 #define DSI_CON_CTRL 0x10
36 #define DSI_RESET BIT(0)
39 #define DSI_MODE_CTRL 0x14
42 #define SYNC_PULSE_MODE 1
43 #define SYNC_EVENT_MODE 2
45 #define FRM_MODE BIT(16)
46 #define MIX_MODE BIT(17)
48 #define DSI_TXRX_CTRL 0x18
49 #define VC_NUM (2 << 0)
50 #define LANE_NUM (0xf << 2)
51 #define DIS_EOT BIT(6)
52 #define NULL_EN BIT(7)
53 #define TE_FREERUN BIT(8)
54 #define EXT_TE_EN BIT(9)
55 #define EXT_TE_EDGE BIT(10)
56 #define MAX_RTN_SIZE (0xf << 12)
57 #define HSTX_CKLP_EN BIT(16)
59 #define DSI_PSCTRL 0x1c
60 #define DSI_PS_WC 0x3fff
61 #define DSI_PS_SEL (3 << 16)
62 #define PACKED_PS_16BIT_RGB565 (0 << 16)
63 #define LOOSELY_PS_18BIT_RGB666 (1 << 16)
64 #define PACKED_PS_18BIT_RGB666 (2 << 16)
65 #define PACKED_PS_24BIT_RGB888 (3 << 16)
67 #define DSI_VSA_NL 0x20
68 #define DSI_VBP_NL 0x24
69 #define DSI_VFP_NL 0x28
70 #define DSI_VACT_NL 0x2C
71 #define DSI_HSA_WC 0x50
72 #define DSI_HBP_WC 0x54
73 #define DSI_HFP_WC 0x58
75 #define DSI_HSTX_CKL_WC 0x64
77 #define DSI_PHY_LCCON 0x104
78 #define LC_HS_TX_EN BIT(0)
79 #define LC_ULPM_EN BIT(1)
80 #define LC_WAKEUP_EN BIT(2)
82 #define DSI_PHY_LD0CON 0x108
83 #define LD0_HS_TX_EN BIT(0)
84 #define LD0_ULPM_EN BIT(1)
85 #define LD0_WAKEUP_EN BIT(2)
87 #define DSI_PHY_TIMECON0 0x110
88 #define LPX (0xff << 0)
89 #define HS_PRPR (0xff << 8)
90 #define HS_ZERO (0xff << 16)
91 #define HS_TRAIL (0xff << 24)
93 #define DSI_PHY_TIMECON1 0x114
94 #define TA_GO (0xff << 0)
95 #define TA_SURE (0xff << 8)
96 #define TA_GET (0xff << 16)
97 #define DA_HS_EXIT (0xff << 24)
99 #define DSI_PHY_TIMECON2 0x118
100 #define CONT_DET (0xff << 0)
101 #define CLK_ZERO (0xff << 16)
102 #define CLK_TRAIL (0xff << 24)
104 #define DSI_PHY_TIMECON3 0x11c
105 #define CLK_HS_PRPR (0xff << 0)
106 #define CLK_HS_POST (0xff << 8)
107 #define CLK_HS_EXIT (0xff << 16)
109 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
114 struct mtk_ddp_comp ddp_comp;
116 struct mipi_dsi_host host;
117 struct drm_encoder encoder;
118 struct drm_connector conn;
119 struct drm_panel *panel;
120 struct drm_bridge *bridge;
125 struct clk *engine_clk;
126 struct clk *digital_clk;
131 unsigned long mode_flags;
132 enum mipi_dsi_pixel_format format;
139 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
141 return container_of(e, struct mtk_dsi, encoder);
144 static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
146 return container_of(c, struct mtk_dsi, conn);
149 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
151 return container_of(h, struct mtk_dsi, host);
154 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
156 u32 temp = readl(dsi->regs + offset);
158 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
161 static void dsi_phy_timconfig(struct mtk_dsi *dsi)
163 u32 timcon0, timcon1, timcon2, timcon3;
164 unsigned int ui, cycle_time;
167 ui = 1000 / dsi->data_rate + 0x01;
168 cycle_time = 8000 / dsi->data_rate + 0x01;
171 timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
172 timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
174 timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
175 (NS_TO_CYCLE(0x150, cycle_time) << 16);
176 timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
177 NS_TO_CYCLE(0x40, cycle_time);
179 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
180 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
181 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
182 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
185 static void mtk_dsi_enable(struct mtk_dsi *dsi)
187 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
190 static void mtk_dsi_disable(struct mtk_dsi *dsi)
192 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
195 static void mtk_dsi_reset(struct mtk_dsi *dsi)
197 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
198 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
201 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
203 struct device *dev = dsi->dev;
206 if (++dsi->refcount != 1)
210 * data_rate = (pixel_clock / 1000) * pixel_dipth * mipi_ratio;
211 * pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
212 * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
213 * we set mipi_ratio is 1.05.
215 dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10);
217 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 1000000);
219 dev_err(dev, "Failed to set data rate: %d\n", ret);
223 phy_power_on(dsi->phy);
225 ret = clk_prepare_enable(dsi->engine_clk);
227 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
228 goto err_phy_power_off;
231 ret = clk_prepare_enable(dsi->digital_clk);
233 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
234 goto err_disable_engine_clk;
239 dsi_phy_timconfig(dsi);
243 err_disable_engine_clk:
244 clk_disable_unprepare(dsi->engine_clk);
246 phy_power_off(dsi->phy);
252 static void dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
254 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
255 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
258 static void dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
260 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
261 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
262 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
265 static void dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
267 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
268 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
271 static void dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
273 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
274 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
275 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
278 static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
282 tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
283 return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
286 static void dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
288 if (enter && !dsi_clk_hs_state(dsi))
289 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
290 else if (!enter && dsi_clk_hs_state(dsi))
291 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
294 static void dsi_set_mode(struct mtk_dsi *dsi)
296 u32 vid_mode = CMD_MODE;
298 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
299 vid_mode = SYNC_PULSE_MODE;
301 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
302 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
303 vid_mode = BURST_MODE;
306 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
309 static void dsi_ps_control_vact(struct mtk_dsi *dsi)
311 struct videomode *vm = &dsi->vm;
312 u32 dsi_buf_bpp, ps_wc;
315 if (dsi->format == MIPI_DSI_FMT_RGB565)
320 ps_wc = vm->hactive * dsi_buf_bpp;
323 switch (dsi->format) {
324 case MIPI_DSI_FMT_RGB888:
325 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
327 case MIPI_DSI_FMT_RGB666:
328 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
330 case MIPI_DSI_FMT_RGB666_PACKED:
331 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
333 case MIPI_DSI_FMT_RGB565:
334 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
338 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
339 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
340 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
343 static void dsi_rxtx_control(struct mtk_dsi *dsi)
347 switch (dsi->lanes) {
365 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
368 static void dsi_ps_control(struct mtk_dsi *dsi)
370 unsigned int dsi_tmp_buf_bpp;
373 switch (dsi->format) {
374 case MIPI_DSI_FMT_RGB888:
375 tmp_reg = PACKED_PS_24BIT_RGB888;
378 case MIPI_DSI_FMT_RGB666:
379 tmp_reg = LOOSELY_PS_18BIT_RGB666;
382 case MIPI_DSI_FMT_RGB666_PACKED:
383 tmp_reg = PACKED_PS_18BIT_RGB666;
386 case MIPI_DSI_FMT_RGB565:
387 tmp_reg = PACKED_PS_16BIT_RGB565;
391 tmp_reg = PACKED_PS_24BIT_RGB888;
396 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
397 writel(tmp_reg, dsi->regs + DSI_PSCTRL);
400 static void dsi_config_vdo_timing(struct mtk_dsi *dsi)
402 unsigned int horizontal_sync_active_byte;
403 unsigned int horizontal_backporch_byte;
404 unsigned int horizontal_frontporch_byte;
405 unsigned int dsi_tmp_buf_bpp;
407 struct videomode *vm = &dsi->vm;
409 if (dsi->format == MIPI_DSI_FMT_RGB565)
414 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
415 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
416 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
417 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
419 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
421 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
422 horizontal_backporch_byte =
423 (vm->hback_porch * dsi_tmp_buf_bpp - 10);
425 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
426 dsi_tmp_buf_bpp - 10);
428 horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
430 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
431 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
432 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
437 static void mtk_dsi_start(struct mtk_dsi *dsi)
439 writel(0, dsi->regs + DSI_START);
440 writel(1, dsi->regs + DSI_START);
443 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
445 if (WARN_ON(dsi->refcount == 0))
448 if (--dsi->refcount != 0)
451 dsi_lane0_ulp_mode_enter(dsi);
452 dsi_clk_ulp_mode_enter(dsi);
454 mtk_dsi_disable(dsi);
456 clk_disable_unprepare(dsi->engine_clk);
457 clk_disable_unprepare(dsi->digital_clk);
459 phy_power_off(dsi->phy);
462 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
470 if (drm_panel_prepare(dsi->panel)) {
471 DRM_ERROR("failed to setup the panel\n");
476 ret = mtk_dsi_poweron(dsi);
478 DRM_ERROR("failed to power on dsi\n");
482 dsi_rxtx_control(dsi);
484 dsi_clk_ulp_mode_leave(dsi);
485 dsi_lane0_ulp_mode_leave(dsi);
486 dsi_clk_hs_mode(dsi, 0);
489 dsi_ps_control_vact(dsi);
490 dsi_config_vdo_timing(dsi);
493 dsi_clk_hs_mode(dsi, 1);
500 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
506 if (drm_panel_disable(dsi->panel)) {
507 DRM_ERROR("failed to disable the panel\n");
512 mtk_dsi_poweroff(dsi);
514 dsi->enabled = false;
517 static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
519 drm_encoder_cleanup(encoder);
522 static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
523 .destroy = mtk_dsi_encoder_destroy,
526 static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
527 const struct drm_display_mode *mode,
528 struct drm_display_mode *adjusted_mode)
533 static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
534 struct drm_display_mode *mode,
535 struct drm_display_mode *adjusted)
537 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
539 dsi->vm.pixelclock = adjusted->clock;
540 dsi->vm.hactive = adjusted->hdisplay;
541 dsi->vm.hback_porch = adjusted->htotal - adjusted->hsync_end;
542 dsi->vm.hfront_porch = adjusted->hsync_start - adjusted->hdisplay;
543 dsi->vm.hsync_len = adjusted->hsync_end - adjusted->hsync_start;
545 dsi->vm.vactive = adjusted->vdisplay;
546 dsi->vm.vback_porch = adjusted->vtotal - adjusted->vsync_end;
547 dsi->vm.vfront_porch = adjusted->vsync_start - adjusted->vdisplay;
548 dsi->vm.vsync_len = adjusted->vsync_end - adjusted->vsync_start;
551 static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
553 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
555 mtk_output_dsi_disable(dsi);
558 static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
560 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
562 mtk_output_dsi_enable(dsi);
565 static enum drm_connector_status mtk_dsi_connector_detect(
566 struct drm_connector *connector, bool force)
568 return connector_status_connected;
571 static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
573 struct mtk_dsi *dsi = connector_to_dsi(connector);
575 return drm_panel_get_modes(dsi->panel);
578 static struct drm_encoder *mtk_dsi_connector_best_encoder(
579 struct drm_connector *connector)
581 struct mtk_dsi *dsi = connector_to_dsi(connector);
583 return &dsi->encoder;
586 static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
587 .mode_fixup = mtk_dsi_encoder_mode_fixup,
588 .mode_set = mtk_dsi_encoder_mode_set,
589 .disable = mtk_dsi_encoder_disable,
590 .enable = mtk_dsi_encoder_enable,
593 static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
594 .dpms = drm_atomic_helper_connector_dpms,
595 .detect = mtk_dsi_connector_detect,
596 .fill_modes = drm_helper_probe_single_connector_modes,
597 .destroy = drm_connector_cleanup,
598 .reset = drm_atomic_helper_connector_reset,
599 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
600 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
603 static const struct drm_connector_helper_funcs
604 mtk_dsi_connector_helper_funcs = {
605 .get_modes = mtk_dsi_connector_get_modes,
606 .best_encoder = mtk_dsi_connector_best_encoder,
609 static int mtk_drm_attach_bridge(struct drm_bridge *bridge,
610 struct drm_encoder *encoder)
617 encoder->bridge = bridge;
618 bridge->encoder = encoder;
619 ret = drm_bridge_attach(encoder->dev, bridge);
621 DRM_ERROR("Failed to attach bridge to drm\n");
622 encoder->bridge = NULL;
623 bridge->encoder = NULL;
629 static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
633 ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
634 DRM_MODE_CONNECTOR_DSI);
636 DRM_ERROR("Failed to connector init to drm\n");
640 drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
642 dsi->conn.dpms = DRM_MODE_DPMS_OFF;
643 drm_mode_connector_attach_encoder(&dsi->conn, &dsi->encoder);
646 ret = drm_panel_attach(dsi->panel, &dsi->conn);
648 DRM_ERROR("Failed to attach panel to drm\n");
649 goto err_connector_cleanup;
655 err_connector_cleanup:
656 drm_connector_cleanup(&dsi->conn);
660 static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
664 ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
665 DRM_MODE_ENCODER_DSI, NULL);
667 DRM_ERROR("Failed to encoder init to drm\n");
670 drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
673 * Currently display data paths are statically assigned to a crtc each.
674 * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
676 dsi->encoder.possible_crtcs = 1;
678 /* If there's a bridge, attach to it and let it create the connector */
679 ret = mtk_drm_attach_bridge(dsi->bridge, &dsi->encoder);
681 /* Otherwise create our own connector and attach to a panel */
682 ret = mtk_dsi_create_connector(drm, dsi);
684 goto err_encoder_cleanup;
690 drm_encoder_cleanup(&dsi->encoder);
694 static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
696 drm_encoder_cleanup(&dsi->encoder);
697 /* Skip connector cleanup if creation was delegated to the bridge */
699 drm_connector_cleanup(&dsi->conn);
702 static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
704 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
706 mtk_dsi_poweron(dsi);
709 static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
711 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
713 mtk_dsi_poweroff(dsi);
716 static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
717 .start = mtk_dsi_ddp_start,
718 .stop = mtk_dsi_ddp_stop,
721 static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
722 struct mipi_dsi_device *device)
724 struct mtk_dsi *dsi = host_to_dsi(host);
726 dsi->lanes = device->lanes;
727 dsi->format = device->format;
728 dsi->mode_flags = device->mode_flags;
731 drm_helper_hpd_irq_event(dsi->conn.dev);
736 static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
737 struct mipi_dsi_device *device)
739 struct mtk_dsi *dsi = host_to_dsi(host);
742 drm_helper_hpd_irq_event(dsi->conn.dev);
747 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
748 .attach = mtk_dsi_host_attach,
749 .detach = mtk_dsi_host_detach,
752 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
755 struct drm_device *drm = data;
756 struct mtk_dsi *dsi = dev_get_drvdata(dev);
758 ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
760 dev_err(dev, "Failed to register component %s: %d\n",
761 dev->of_node->full_name, ret);
765 ret = mipi_dsi_host_register(&dsi->host);
767 dev_err(dev, "failed to register DSI host: %d\n", ret);
768 goto err_ddp_comp_unregister;
771 ret = mtk_dsi_create_conn_enc(drm, dsi);
773 DRM_ERROR("Encoder create failed with %d\n", ret);
780 mipi_dsi_host_unregister(&dsi->host);
781 err_ddp_comp_unregister:
782 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
786 static void mtk_dsi_unbind(struct device *dev, struct device *master,
789 struct drm_device *drm = data;
790 struct mtk_dsi *dsi = dev_get_drvdata(dev);
792 mtk_dsi_destroy_conn_enc(dsi);
793 mipi_dsi_host_unregister(&dsi->host);
794 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
797 static const struct component_ops mtk_dsi_component_ops = {
798 .bind = mtk_dsi_bind,
799 .unbind = mtk_dsi_unbind,
802 static int mtk_dsi_probe(struct platform_device *pdev)
805 struct device *dev = &pdev->dev;
806 struct device_node *remote_node, *endpoint;
807 struct resource *regs;
811 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
815 dsi->host.ops = &mtk_dsi_ops;
818 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
820 remote_node = of_graph_get_remote_port_parent(endpoint);
822 dev_err(dev, "No panel connected\n");
826 dsi->bridge = of_drm_find_bridge(remote_node);
827 dsi->panel = of_drm_find_panel(remote_node);
828 of_node_put(remote_node);
829 if (!dsi->bridge && !dsi->panel) {
830 dev_info(dev, "Waiting for bridge or panel driver\n");
831 return -EPROBE_DEFER;
835 dsi->engine_clk = devm_clk_get(dev, "engine");
836 if (IS_ERR(dsi->engine_clk)) {
837 ret = PTR_ERR(dsi->engine_clk);
838 dev_err(dev, "Failed to get engine clock: %d\n", ret);
842 dsi->digital_clk = devm_clk_get(dev, "digital");
843 if (IS_ERR(dsi->digital_clk)) {
844 ret = PTR_ERR(dsi->digital_clk);
845 dev_err(dev, "Failed to get digital clock: %d\n", ret);
849 dsi->hs_clk = devm_clk_get(dev, "hs");
850 if (IS_ERR(dsi->hs_clk)) {
851 ret = PTR_ERR(dsi->hs_clk);
852 dev_err(dev, "Failed to get hs clock: %d\n", ret);
856 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
857 dsi->regs = devm_ioremap_resource(dev, regs);
858 if (IS_ERR(dsi->regs)) {
859 ret = PTR_ERR(dsi->regs);
860 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
864 dsi->phy = devm_phy_get(dev, "dphy");
865 if (IS_ERR(dsi->phy)) {
866 ret = PTR_ERR(dsi->phy);
867 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
871 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
873 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
877 ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
880 dev_err(dev, "Failed to initialize component: %d\n", ret);
884 platform_set_drvdata(pdev, dsi);
886 return component_add(&pdev->dev, &mtk_dsi_component_ops);
889 static int mtk_dsi_remove(struct platform_device *pdev)
891 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
893 mtk_output_dsi_disable(dsi);
894 component_del(&pdev->dev, &mtk_dsi_component_ops);
899 static const struct of_device_id mtk_dsi_of_match[] = {
900 { .compatible = "mediatek,mt8173-dsi" },
904 struct platform_driver mtk_dsi_driver = {
905 .probe = mtk_dsi_probe,
906 .remove = mtk_dsi_remove,
909 .of_match_table = mtk_dsi_of_match,