drivers/gpu/drm/meson/meson_vclk.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2016 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   6  */
   7
   8 #include <linux/export.h>
   9
  10 #include <drm/drm_print.h>
  11
  12 #include "meson_drv.h"
  13 #include "meson_vclk.h"
  14
  15 /**
  16  * DOC: Video Clocks
  17  *
  18  * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
  19  * We handle the following encodings :
  20  *
  21  * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
  22  * - HDMI Pixel Clocks generation
  23  *
  24  * What is missing :
  25  *
  26  * - Genenate Pixel clocks for 2K/4K 10bit formats
  27  *
  28  * Clock generator scheme :
  29  *
  30  * .. code::
  31  *
  32  *    __________   _________            _____
  33  *   |          | |         |          |     |--ENCI
  34  *   | HDMI PLL |-| PLL_DIV |--- VCLK--|     |--ENCL
  35  *   |__________| |_________| \        | MUX |--ENCP
  36  *                             --VCLK2-|     |--VDAC
  37  *                                     |_____|--HDMI-TX
  38  *
  39  * Final clocks can take input for either VCLK or VCLK2, but
  40  * VCLK is the preferred path for HDMI clocking and VCLK2 is the
  41  * preferred path for CVBS VDAC clocking.
  42  *
  43  * VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
  44  *
  45  * The PLL_DIV can achieve an additional fractional dividing like
  46  * 1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.
  47  */
  48
  49 /* HHI Registers */
  50 #define HHI_VID_PLL_CLK_DIV     0x1a0 /* 0x68 offset in data sheet */
  51 #define VID_PLL_EN              BIT(19)
  52 #define VID_PLL_BYPASS          BIT(18)
  53 #define VID_PLL_PRESET          BIT(15)
  54 #define HHI_VIID_CLK_DIV        0x128 /* 0x4a offset in data sheet */
  55 #define VCLK2_DIV_MASK          0xff
  56 #define VCLK2_DIV_EN            BIT(16)
  57 #define VCLK2_DIV_RESET         BIT(17)
  58 #define CTS_VDAC_SEL_MASK       (0xf << 28)
  59 #define CTS_VDAC_SEL_SHIFT      28
  60 #define HHI_VIID_CLK_CNTL       0x12c /* 0x4b offset in data sheet */
  61 #define VCLK2_EN                BIT(19)
  62 #define VCLK2_SEL_MASK          (0x7 << 16)
  63 #define VCLK2_SEL_SHIFT         16
  64 #define VCLK2_SOFT_RESET        BIT(15)
  65 #define VCLK2_DIV1_EN           BIT(0)
  66 #define HHI_VID_CLK_DIV         0x164 /* 0x59 offset in data sheet */
  67 #define VCLK_DIV_MASK           0xff
  68 #define VCLK_DIV_EN             BIT(16)
  69 #define VCLK_DIV_RESET          BIT(17)
  70 #define CTS_ENCP_SEL_MASK       (0xf << 24)
  71 #define CTS_ENCP_SEL_SHIFT      24
  72 #define CTS_ENCI_SEL_MASK       (0xf << 28)
  73 #define CTS_ENCI_SEL_SHIFT      28
  74 #define HHI_VID_CLK_CNTL        0x17c /* 0x5f offset in data sheet */
  75 #define VCLK_EN                 BIT(19)
  76 #define VCLK_SEL_MASK           (0x7 << 16)
  77 #define VCLK_SEL_SHIFT          16
  78 #define VCLK_SOFT_RESET         BIT(15)
  79 #define VCLK_DIV1_EN            BIT(0)
  80 #define VCLK_DIV2_EN            BIT(1)
  81 #define VCLK_DIV4_EN            BIT(2)
  82 #define VCLK_DIV6_EN            BIT(3)
  83 #define VCLK_DIV12_EN           BIT(4)
  84 #define HHI_VID_CLK_CNTL2       0x194 /* 0x65 offset in data sheet */
  85 #define CTS_ENCI_EN             BIT(0)
  86 #define CTS_ENCP_EN             BIT(2)
  87 #define CTS_VDAC_EN             BIT(4)
  88 #define HDMI_TX_PIXEL_EN        BIT(5)
  89 #define HHI_HDMI_CLK_CNTL       0x1cc /* 0x73 offset in data sheet */
  90 #define HDMI_TX_PIXEL_SEL_MASK  (0xf << 16)
  91 #define HDMI_TX_PIXEL_SEL_SHIFT 16
  92 #define CTS_HDMI_SYS_SEL_MASK   (0x7 << 9)
  93 #define CTS_HDMI_SYS_DIV_MASK   (0x7f)
  94 #define CTS_HDMI_SYS_EN         BIT(8)
  95
  96 #define HHI_VDAC_CNTL0          0x2F4 /* 0xbd offset in data sheet */
  97 #define HHI_VDAC_CNTL1          0x2F8 /* 0xbe offset in data sheet */
  98
  99 #define HHI_HDMI_PLL_CNTL       0x320 /* 0xc8 offset in data sheet */
 100 #define HHI_HDMI_PLL_CNTL2      0x324 /* 0xc9 offset in data sheet */
 101 #define HHI_HDMI_PLL_CNTL3      0x328 /* 0xca offset in data sheet */
 102 #define HHI_HDMI_PLL_CNTL4      0x32C /* 0xcb offset in data sheet */
 103 #define HHI_HDMI_PLL_CNTL5      0x330 /* 0xcc offset in data sheet */
 104 #define HHI_HDMI_PLL_CNTL6      0x334 /* 0xcd offset in data sheet */
 105 #define HHI_HDMI_PLL_CNTL7      0x338 /* 0xce offset in data sheet */
 106
 107 #define HDMI_PLL_RESET          BIT(28)
 108 #define HDMI_PLL_RESET_G12A     BIT(29)
 109 #define HDMI_PLL_LOCK           BIT(31)
 110 #define HDMI_PLL_LOCK_G12A      (3 << 30)
 111
 112 #define FREQ_1000_1001(_freq)   DIV_ROUND_CLOSEST(_freq * 1000, 1001)
 113
 114 /* VID PLL Dividers */
 115 enum {
 116         VID_PLL_DIV_1 = 0,
 117         VID_PLL_DIV_2,
 118         VID_PLL_DIV_2p5,
 119         VID_PLL_DIV_3,
 120         VID_PLL_DIV_3p5,
 121         VID_PLL_DIV_3p75,
 122         VID_PLL_DIV_4,
 123         VID_PLL_DIV_5,
 124         VID_PLL_DIV_6,
 125         VID_PLL_DIV_6p25,
 126         VID_PLL_DIV_7,
 127         VID_PLL_DIV_7p5,
 128         VID_PLL_DIV_12,
 129         VID_PLL_DIV_14,
 130         VID_PLL_DIV_15,
 131 };
 132
 133 void meson_vid_pll_set(struct meson_drm *priv, unsigned int div)
 134 {
 135         unsigned int shift_val = 0;
 136         unsigned int shift_sel = 0;
 137
 138         /* Disable vid_pll output clock */
 139         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
 140         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
 141
 142         switch (div) {
 143         case VID_PLL_DIV_2:
 144                 shift_val = 0x0aaa;
 145                 shift_sel = 0;
 146                 break;
 147         case VID_PLL_DIV_2p5:
 148                 shift_val = 0x5294;
 149                 shift_sel = 2;
 150                 break;
 151         case VID_PLL_DIV_3:
 152                 shift_val = 0x0db6;
 153                 shift_sel = 0;
 154                 break;
 155         case VID_PLL_DIV_3p5:
 156                 shift_val = 0x36cc;
 157                 shift_sel = 1;
 158                 break;
 159         case VID_PLL_DIV_3p75:
 160                 shift_val = 0x6666;
 161                 shift_sel = 2;
 162                 break;
 163         case VID_PLL_DIV_4:
 164                 shift_val = 0x0ccc;
 165                 shift_sel = 0;
 166                 break;
 167         case VID_PLL_DIV_5:
 168                 shift_val = 0x739c;
 169                 shift_sel = 2;
 170                 break;
 171         case VID_PLL_DIV_6:
 172                 shift_val = 0x0e38;
 173                 shift_sel = 0;
 174                 break;
 175         case VID_PLL_DIV_6p25:
 176                 shift_val = 0x0000;
 177                 shift_sel = 3;
 178                 break;
 179         case VID_PLL_DIV_7:
 180                 shift_val = 0x3c78;
 181                 shift_sel = 1;
 182                 break;
 183         case VID_PLL_DIV_7p5:
 184                 shift_val = 0x78f0;
 185                 shift_sel = 2;
 186                 break;
 187         case VID_PLL_DIV_12:
 188                 shift_val = 0x0fc0;
 189                 shift_sel = 0;
 190                 break;
 191         case VID_PLL_DIV_14:
 192                 shift_val = 0x3f80;
 193                 shift_sel = 1;
 194                 break;
 195         case VID_PLL_DIV_15:
 196                 shift_val = 0x7f80;
 197                 shift_sel = 2;
 198                 break;
 199         }
 200
 201         if (div == VID_PLL_DIV_1)
 202                 /* Enable vid_pll bypass to HDMI pll */
 203                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 204                                    VID_PLL_BYPASS, VID_PLL_BYPASS);
 205         else {
 206                 /* Disable Bypass */
 207                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 208                                    VID_PLL_BYPASS, 0);
 209                 /* Clear sel */
 210                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 211                                    3 << 16, 0);
 212                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 213                                    VID_PLL_PRESET, 0);
 214                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 215                                    0x7fff, 0);
 216
 217                 /* Setup sel and val */
 218                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 219                                    3 << 16, shift_sel << 16);
 220                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 221                                    VID_PLL_PRESET, VID_PLL_PRESET);
 222                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 223                                    0x7fff, shift_val);
 224
 225                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 226                                    VID_PLL_PRESET, 0);
 227         }
 228
 229         /* Enable the vid_pll output clock */
 230         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 231                                 VID_PLL_EN, VID_PLL_EN);
 232 }
 233
 234 /*
 235  * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
 236  *
 237  * TOFIX: Refactor into table to also handle HDMI frequency and paths
 238  */
 239 static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
 240 {
 241         unsigned int val;
 242
 243         /* Setup PLL to output 1.485GHz */
 244         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 245                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
 246                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);
 247                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 248                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 249                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 250                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 251                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
 252
 253                 /* Poll for lock bit */
 254                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 255                                          (val & HDMI_PLL_LOCK), 10, 0);
 256         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 257                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
 258                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
 259                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
 260                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844);
 261                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
 262                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 263                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 264
 265                 /* Reset PLL */
 266                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 267                                         HDMI_PLL_RESET, HDMI_PLL_RESET);
 268                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 269                                         HDMI_PLL_RESET, 0);
 270
 271                 /* Poll for lock bit */
 272                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 273                                          (val & HDMI_PLL_LOCK), 10, 0);
 274         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
 275                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
 276                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000);
 277                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
 278                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
 279                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
 280                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
 281                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x56540000);
 282                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7);
 283                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
 284
 285                 /* Poll for lock bit */
 286                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 287                         ((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
 288                         10, 0);
 289         }
 290
 291         /* Disable VCLK2 */
 292         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
 293
 294         /* Setup vid_pll to /1 */
 295         meson_vid_pll_set(priv, VID_PLL_DIV_1);
 296
 297         /* Setup the VCLK2 divider value to achieve 27MHz */
 298         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 299                                 VCLK2_DIV_MASK, (55 - 1));
 300
 301         /* select vid_pll for vclk2 */
 302         if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 303                 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 304                                         VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
 305         else
 306                 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 307                                         VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
 308
 309         /* enable vclk2 gate */
 310         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
 311
 312         /* select vclk_div1 for enci */
 313         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 314                                 CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
 315         /* select vclk_div1 for vdac */
 316         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 317                                 CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
 318
 319         /* release vclk2_div_reset and enable vclk2_div */
 320         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 321                                 VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
 322
 323         /* enable vclk2_div1 gate */
 324         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 325                                 VCLK2_DIV1_EN, VCLK2_DIV1_EN);
 326
 327         /* reset vclk2 */
 328         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 329                                 VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
 330         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 331                                 VCLK2_SOFT_RESET, 0);
 332
 333         /* enable enci_clk */
 334         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 335                                 CTS_ENCI_EN, CTS_ENCI_EN);
 336         /* enable vdac_clk */
 337         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 338                                 CTS_VDAC_EN, CTS_VDAC_EN);
 339 }
 340
 341 enum {
 342 /* PLL  O1 O2 O3 VP DV     EN TX */
 343 /* 4320 /4 /4 /1 /5 /1  => /2 /2 */
 344         MESON_VCLK_HDMI_ENCI_54000 = 0,
 345 /* 4320 /4 /4 /1 /5 /1  => /1 /2 */
 346         MESON_VCLK_HDMI_DDR_54000,
 347 /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
 348         MESON_VCLK_HDMI_DDR_148500,
 349 /* 2970 /2 /2 /2 /5 /1  => /1 /1 */
 350         MESON_VCLK_HDMI_74250,
 351 /* 2970 /1 /2 /2 /5 /1  => /1 /1 */
 352         MESON_VCLK_HDMI_148500,
 353 /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
 354         MESON_VCLK_HDMI_297000,
 355 /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
 356         MESON_VCLK_HDMI_594000
 357 };
 358
 359 struct meson_vclk_params {
 360         unsigned int pixel_freq;
 361         unsigned int pll_base_freq;
 362         unsigned int pll_od1;
 363         unsigned int pll_od2;
 364         unsigned int pll_od3;
 365         unsigned int vid_pll_div;
 366         unsigned int vclk_div;
 367 } params[] = {
 368         [MESON_VCLK_HDMI_ENCI_54000] = {
 369                 .pixel_freq = 54000,
 370                 .pll_base_freq = 4320000,
 371                 .pll_od1 = 4,
 372                 .pll_od2 = 4,
 373                 .pll_od3 = 1,
 374                 .vid_pll_div = VID_PLL_DIV_5,
 375                 .vclk_div = 1,
 376         },
 377         [MESON_VCLK_HDMI_DDR_54000] = {
 378                 .pixel_freq = 54000,
 379                 .pll_base_freq = 4320000,
 380                 .pll_od1 = 4,
 381                 .pll_od2 = 4,
 382                 .pll_od3 = 1,
 383                 .vid_pll_div = VID_PLL_DIV_5,
 384                 .vclk_div = 1,
 385         },
 386         [MESON_VCLK_HDMI_DDR_148500] = {
 387                 .pixel_freq = 148500,
 388                 .pll_base_freq = 2970000,
 389                 .pll_od1 = 4,
 390                 .pll_od2 = 1,
 391                 .pll_od3 = 1,
 392                 .vid_pll_div = VID_PLL_DIV_5,
 393                 .vclk_div = 1,
 394         },
 395         [MESON_VCLK_HDMI_74250] = {
 396                 .pixel_freq = 74250,
 397                 .pll_base_freq = 2970000,
 398                 .pll_od1 = 2,
 399                 .pll_od2 = 2,
 400                 .pll_od3 = 2,
 401                 .vid_pll_div = VID_PLL_DIV_5,
 402                 .vclk_div = 1,
 403         },
 404         [MESON_VCLK_HDMI_148500] = {
 405                 .pixel_freq = 148500,
 406                 .pll_base_freq = 2970000,
 407                 .pll_od1 = 1,
 408                 .pll_od2 = 2,
 409                 .pll_od3 = 2,
 410                 .vid_pll_div = VID_PLL_DIV_5,
 411                 .vclk_div = 1,
 412         },
 413         [MESON_VCLK_HDMI_297000] = {
 414                 .pixel_freq = 297000,
 415                 .pll_base_freq = 5940000,
 416                 .pll_od1 = 2,
 417                 .pll_od2 = 1,
 418                 .pll_od3 = 1,
 419                 .vid_pll_div = VID_PLL_DIV_5,
 420                 .vclk_div = 2,
 421         },
 422         [MESON_VCLK_HDMI_594000] = {
 423                 .pixel_freq = 594000,
 424                 .pll_base_freq = 5940000,
 425                 .pll_od1 = 1,
 426                 .pll_od2 = 1,
 427                 .pll_od3 = 2,
 428                 .vid_pll_div = VID_PLL_DIV_5,
 429                 .vclk_div = 1,
 430         },
 431         { /* sentinel */ },
 432 };
 433
 434 static inline unsigned int pll_od_to_reg(unsigned int od)
 435 {
 436         switch (od) {
 437         case 1:
 438                 return 0;
 439         case 2:
 440                 return 1;
 441         case 4:
 442                 return 2;
 443         case 8:
 444                 return 3;
 445         }
 446
 447         /* Invalid */
 448         return 0;
 449 }
 450
 451 void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
 452                                unsigned int frac, unsigned int od1,
 453                                unsigned int od2, unsigned int od3)
 454 {
 455         unsigned int val;
 456
 457         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 458                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m);
 459                 if (frac)
 460                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
 461                                      0x00004000 | frac);
 462                 else
 463                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
 464                                      0x00000000);
 465                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 466                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 467                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 468                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 469
 470                 /* Enable and unreset */
 471                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 472                                    0x7 << 28, 0x4 << 28);
 473
 474                 /* Poll for lock bit */
 475                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 476                                          val, (val & HDMI_PLL_LOCK), 10, 0);
 477         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 478                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
 479                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m);
 480                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
 481                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 482                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 483                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 484                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 485
 486                 /* Reset PLL */
 487                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 488                                 HDMI_PLL_RESET, HDMI_PLL_RESET);
 489                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 490                                 HDMI_PLL_RESET, 0);
 491
 492                 /* Poll for lock bit */
 493                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 494                                 (val & HDMI_PLL_LOCK), 10, 0);
 495         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
 496                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
 497
 498                 /* Enable and reset */
 499                 /* TODO: add specific macro for g12a here */
 500                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 501                                    0x3 << 28, 0x3 << 28);
 502
 503                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac);
 504                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
 505
 506                 /* G12A HDMI PLL Needs specific parameters for 5.4GHz */
 507                 if (m >= 0xf7) {
 508                         if (frac < 0x10000) {
 509                                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
 510                                                         0x6a685c00);
 511                                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
 512                                                         0x11551293);
 513                         } else {
 514                                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
 515                                                         0xea68dc00);
 516                                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
 517                                                         0x65771290);
 518                         }
 519                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
 520                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000);
 521                 } else {
 522                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00);
 523                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290);
 524                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000);
 525                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000);
 526                 }
 527
 528                 do {
 529                         /* Reset PLL */
 530                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 531                                         HDMI_PLL_RESET_G12A, HDMI_PLL_RESET_G12A);
 532
 533                         /* UN-Reset PLL */
 534                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 535                                         HDMI_PLL_RESET_G12A, 0);
 536
 537                         /* Poll for lock bits */
 538                         if (!regmap_read_poll_timeout(priv->hhi,
 539                                                       HHI_HDMI_PLL_CNTL, val,
 540                                                       ((val & HDMI_PLL_LOCK_G12A)
 541                                                         == HDMI_PLL_LOCK_G12A),
 542                                                       10, 100))
 543                                 break;
 544                 } while(1);
 545         }
 546
 547         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 548                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 549                                 3 << 16, pll_od_to_reg(od1) << 16);
 550         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 551                  meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 552                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 553                                 3 << 21, pll_od_to_reg(od1) << 21);
 554         else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 555                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 556                                 3 << 16, pll_od_to_reg(od1) << 16);
 557
 558         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 559                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 560                                 3 << 22, pll_od_to_reg(od2) << 22);
 561         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 562                  meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 563                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 564                                 3 << 23, pll_od_to_reg(od2) << 23);
 565         else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 566                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 567                                 3 << 18, pll_od_to_reg(od2) << 18);
 568
 569         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 570                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 571                                 3 << 18, pll_od_to_reg(od3) << 18);
 572         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 573                  meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 574                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 575                                 3 << 19, pll_od_to_reg(od3) << 19);
 576         else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 577                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 578                                 3 << 20, pll_od_to_reg(od3) << 20);
 579 }
 580
 581 #define XTAL_FREQ 24000
 582
 583 static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv,
 584                                          unsigned int pll_freq)
 585 {
 586         /* The GXBB PLL has a /2 pre-multiplier */
 587         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 588                 pll_freq /= 2;
 589
 590         return pll_freq / XTAL_FREQ;
 591 }
 592
 593 #define HDMI_FRAC_MAX_GXBB      4096
 594 #define HDMI_FRAC_MAX_GXL       1024
 595 #define HDMI_FRAC_MAX_G12A      131072
 596
 597 static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv,
 598                                             unsigned int m,
 599                                             unsigned int pll_freq)
 600 {
 601         unsigned int parent_freq = XTAL_FREQ;
 602         unsigned int frac_max = HDMI_FRAC_MAX_GXL;
 603         unsigned int frac_m;
 604         unsigned int frac;
 605
 606         /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
 607         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 608                 frac_max = HDMI_FRAC_MAX_GXBB;
 609                 parent_freq *= 2;
 610         }
 611
 612         if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 613                 frac_max = HDMI_FRAC_MAX_G12A;
 614
 615         /* We can have a perfect match !*/
 616         if (pll_freq / m == parent_freq &&
 617             pll_freq % m == 0)
 618                 return 0;
 619
 620         frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq);
 621         frac_m = m * frac_max;
 622         if (frac_m > frac)
 623                 return frac_max;
 624         frac -= frac_m;
 625
 626         return min((u16)frac, (u16)(frac_max - 1));
 627 }
 628
 629 static bool meson_hdmi_pll_validate_params(struct meson_drm *priv,
 630                                            unsigned int m,
 631                                            unsigned int frac)
 632 {
 633         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 634                 /* Empiric supported min/max dividers */
 635                 if (m < 53 || m > 123)
 636                         return false;
 637                 if (frac >= HDMI_FRAC_MAX_GXBB)
 638                         return false;
 639         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 640                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu") ||
 641                    meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
 642                 /* Empiric supported min/max dividers */
 643                 if (m < 106 || m > 247)
 644                         return false;
 645                 if (frac >= HDMI_FRAC_MAX_GXL)
 646                         return false;
 647         }
 648
 649         return true;
 650 }
 651
 652 static bool meson_hdmi_pll_find_params(struct meson_drm *priv,
 653                                        unsigned int freq,
 654                                        unsigned int *m,
 655                                        unsigned int *frac,
 656                                        unsigned int *od)
 657 {
 658         /* Cycle from /16 to /2 */
 659         for (*od = 16 ; *od > 1 ; *od >>= 1) {
 660                 *m = meson_hdmi_pll_get_m(priv, freq * *od);
 661                 if (!*m)
 662                         continue;
 663                 *frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
 664
 665                 DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d\n",
 666                                  freq, *m, *frac, *od);
 667
 668                 if (meson_hdmi_pll_validate_params(priv, *m, *frac))
 669                         return true;
 670         }
 671
 672         return false;
 673 }
 674
 675 /* pll_freq is the frequency after the OD dividers */
 676 enum drm_mode_status
 677 meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq)
 678 {
 679         unsigned int od, m, frac;
 680
 681         /* In DMT mode, path after PLL is always /10 */
 682         freq *= 10;
 683
 684         if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
 685                 return MODE_OK;
 686
 687         return MODE_CLOCK_RANGE;
 688 }
 689 EXPORT_SYMBOL_GPL(meson_vclk_dmt_supported_freq);
 690
 691 /* pll_freq is the frequency after the OD dividers */
 692 static void meson_hdmi_pll_generic_set(struct meson_drm *priv,
 693                                        unsigned int pll_freq)
 694 {
 695         unsigned int od, m, frac, od1, od2, od3;
 696
 697         if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
 698                 od3 = 1;
 699                 if (od < 4) {
 700                         od1 = 2;
 701                         od2 = 1;
 702                 } else {
 703                         od2 = od / 4;
 704                         od1 = od / od2;
 705                 }
 706
 707                 DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d/%d/%d\n",
 708                                  pll_freq, m, frac, od1, od2, od3);
 709
 710                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 711
 712                 return;
 713         }
 714
 715         DRM_ERROR("Fatal, unable to find parameters for PLL freq %d\n",
 716                   pll_freq);
 717 }
 718
 719 enum drm_mode_status
 720 meson_vclk_vic_supported_freq(unsigned int freq)
 721 {
 722         int i;
 723
 724         DRM_DEBUG_DRIVER("freq = %d\n", freq);
 725
 726         for (i = 0 ; params[i].pixel_freq ; ++i) {
 727                 DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n",
 728                                  i, params[i].pixel_freq,
 729                                  FREQ_1000_1001(params[i].pixel_freq));
 730                 /* Match strict frequency */
 731                 if (freq == params[i].pixel_freq)
 732                         return MODE_OK;
 733                 /* Match 1000/1001 variant */
 734                 if (freq == FREQ_1000_1001(params[i].pixel_freq))
 735                         return MODE_OK;
 736         }
 737
 738         return MODE_CLOCK_RANGE;
 739 }
 740 EXPORT_SYMBOL_GPL(meson_vclk_vic_supported_freq);
 741
 742 static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
 743                            unsigned int od1, unsigned int od2, unsigned int od3,
 744                            unsigned int vid_pll_div, unsigned int vclk_div,
 745                            unsigned int hdmi_tx_div, unsigned int venc_div,
 746                            bool hdmi_use_enci, bool vic_alternate_clock)
 747 {
 748         unsigned int m = 0, frac = 0;
 749
 750         /* Set HDMI-TX sys clock */
 751         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 752                            CTS_HDMI_SYS_SEL_MASK, 0);
 753         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 754                            CTS_HDMI_SYS_DIV_MASK, 0);
 755         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 756                            CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
 757
 758         /* Set HDMI PLL rate */
 759         if (!od1 && !od2 && !od3) {
 760                 meson_hdmi_pll_generic_set(priv, pll_base_freq);
 761         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 762                 switch (pll_base_freq) {
 763                 case 2970000:
 764                         m = 0x3d;
 765                         frac = vic_alternate_clock ? 0xd02 : 0xe00;
 766                         break;
 767                 case 4320000:
 768                         m = vic_alternate_clock ? 0x59 : 0x5a;
 769                         frac = vic_alternate_clock ? 0xe8f : 0;
 770                         break;
 771                 case 5940000:
 772                         m = 0x7b;
 773                         frac = vic_alternate_clock ? 0xa05 : 0xc00;
 774                         break;
 775                 }
 776
 777                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 778         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 779                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
 780                 switch (pll_base_freq) {
 781                 case 2970000:
 782                         m = 0x7b;
 783                         frac = vic_alternate_clock ? 0x281 : 0x300;
 784                         break;
 785                 case 4320000:
 786                         m = vic_alternate_clock ? 0xb3 : 0xb4;
 787                         frac = vic_alternate_clock ? 0x347 : 0;
 788                         break;
 789                 case 5940000:
 790                         m = 0xf7;
 791                         frac = vic_alternate_clock ? 0x102 : 0x200;
 792                         break;
 793                 }
 794
 795                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 796         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
 797                 switch (pll_base_freq) {
 798                 case 2970000:
 799                         m = 0x7b;
 800                         frac = vic_alternate_clock ? 0x140b4 : 0x18000;
 801                         break;
 802                 case 4320000:
 803                         m = vic_alternate_clock ? 0xb3 : 0xb4;
 804                         frac = vic_alternate_clock ? 0x1a3ee : 0;
 805                         break;
 806                 case 5940000:
 807                         m = 0xf7;
 808                         frac = vic_alternate_clock ? 0x8148 : 0x10000;
 809                         break;
 810                 }
 811
 812                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 813         }
 814
 815         /* Setup vid_pll divider */
 816         meson_vid_pll_set(priv, vid_pll_div);
 817
 818         /* Set VCLK div */
 819         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 820                            VCLK_SEL_MASK, 0);
 821         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 822                            VCLK_DIV_MASK, vclk_div - 1);
 823
 824         /* Set HDMI-TX source */
 825         switch (hdmi_tx_div) {
 826         case 1:
 827                 /* enable vclk_div1 gate */
 828                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 829                                    VCLK_DIV1_EN, VCLK_DIV1_EN);
 830
 831                 /* select vclk_div1 for HDMI-TX */
 832                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 833                                    HDMI_TX_PIXEL_SEL_MASK, 0);
 834                 break;
 835         case 2:
 836                 /* enable vclk_div2 gate */
 837                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 838                                    VCLK_DIV2_EN, VCLK_DIV2_EN);
 839
 840                 /* select vclk_div2 for HDMI-TX */
 841                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 842                         HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT);
 843                 break;
 844         case 4:
 845                 /* enable vclk_div4 gate */
 846                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 847                                    VCLK_DIV4_EN, VCLK_DIV4_EN);
 848
 849                 /* select vclk_div4 for HDMI-TX */
 850                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 851                         HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT);
 852                 break;
 853         case 6:
 854                 /* enable vclk_div6 gate */
 855                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 856                                    VCLK_DIV6_EN, VCLK_DIV6_EN);
 857
 858                 /* select vclk_div6 for HDMI-TX */
 859                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 860                         HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT);
 861                 break;
 862         case 12:
 863                 /* enable vclk_div12 gate */
 864                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 865                                    VCLK_DIV12_EN, VCLK_DIV12_EN);
 866
 867                 /* select vclk_div12 for HDMI-TX */
 868                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 869                         HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT);
 870                 break;
 871         }
 872         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 873                                    HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
 874
 875         /* Set ENCI/ENCP Source */
 876         switch (venc_div) {
 877         case 1:
 878                 /* enable vclk_div1 gate */
 879                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 880                                    VCLK_DIV1_EN, VCLK_DIV1_EN);
 881
 882                 if (hdmi_use_enci)
 883                         /* select vclk_div1 for enci */
 884                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 885                                            CTS_ENCI_SEL_MASK, 0);
 886                 else
 887                         /* select vclk_div1 for encp */
 888                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 889                                            CTS_ENCP_SEL_MASK, 0);
 890                 break;
 891         case 2:
 892                 /* enable vclk_div2 gate */
 893                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 894                                    VCLK_DIV2_EN, VCLK_DIV2_EN);
 895
 896                 if (hdmi_use_enci)
 897                         /* select vclk_div2 for enci */
 898                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 899                                 CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT);
 900                 else
 901                         /* select vclk_div2 for encp */
 902                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 903                                 CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT);
 904                 break;
 905         case 4:
 906                 /* enable vclk_div4 gate */
 907                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 908                                    VCLK_DIV4_EN, VCLK_DIV4_EN);
 909
 910                 if (hdmi_use_enci)
 911                         /* select vclk_div4 for enci */
 912                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 913                                 CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT);
 914                 else
 915                         /* select vclk_div4 for encp */
 916                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 917                                 CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT);
 918                 break;
 919         case 6:
 920                 /* enable vclk_div6 gate */
 921                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 922                                    VCLK_DIV6_EN, VCLK_DIV6_EN);
 923
 924                 if (hdmi_use_enci)
 925                         /* select vclk_div6 for enci */
 926                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 927                                 CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT);
 928                 else
 929                         /* select vclk_div6 for encp */
 930                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 931                                 CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT);
 932                 break;
 933         case 12:
 934                 /* enable vclk_div12 gate */
 935                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 936                                    VCLK_DIV12_EN, VCLK_DIV12_EN);
 937
 938                 if (hdmi_use_enci)
 939                         /* select vclk_div12 for enci */
 940                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 941                                 CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT);
 942                 else
 943                         /* select vclk_div12 for encp */
 944                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 945                                 CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT);
 946                 break;
 947         }
 948
 949         if (hdmi_use_enci)
 950                 /* Enable ENCI clock gate */
 951                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 952                                    CTS_ENCI_EN, CTS_ENCI_EN);
 953         else
 954                 /* Enable ENCP clock gate */
 955                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 956                                    CTS_ENCP_EN, CTS_ENCP_EN);
 957
 958         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
 959 }
 960
 961 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
 962                       unsigned int vclk_freq, unsigned int venc_freq,
 963                       unsigned int dac_freq, bool hdmi_use_enci)
 964 {
 965         bool vic_alternate_clock = false;
 966         unsigned int freq;
 967         unsigned int hdmi_tx_div;
 968         unsigned int venc_div;
 969
 970         if (target == MESON_VCLK_TARGET_CVBS) {
 971                 meson_venci_cvbs_clock_config(priv);
 972                 return;
 973         } else if (target == MESON_VCLK_TARGET_DMT) {
 974                 /*
 975                  * The DMT clock path is fixed after the PLL:
 976                  * - automatic PLL freq + OD management
 977                  * - vid_pll_div = VID_PLL_DIV_5
 978                  * - vclk_div = 2
 979                  * - hdmi_tx_div = 1
 980                  * - venc_div = 1
 981                  * - encp encoder
 982                  */
 983                 meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
 984                                VID_PLL_DIV_5, 2, 1, 1, false, false);
 985                 return;
 986         }
 987
 988         hdmi_tx_div = vclk_freq / dac_freq;
 989
 990         if (hdmi_tx_div == 0) {
 991                 pr_err("Fatal Error, invalid HDMI-TX freq %d\n",
 992                        dac_freq);
 993                 return;
 994         }
 995
 996         venc_div = vclk_freq / venc_freq;
 997
 998         if (venc_div == 0) {
 999                 pr_err("Fatal Error, invalid HDMI venc freq %d\n",
1000                        venc_freq);
1001                 return;
1002         }
1003
1004         for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
1005                 if (vclk_freq == params[freq].pixel_freq ||
1006                     vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) {
1007                         if (vclk_freq != params[freq].pixel_freq)
1008                                 vic_alternate_clock = true;
1009                         else
1010                                 vic_alternate_clock = false;
1011
1012                         if (freq == MESON_VCLK_HDMI_ENCI_54000 &&
1013                             !hdmi_use_enci)
1014                                 continue;
1015
1016                         if (freq == MESON_VCLK_HDMI_DDR_54000 &&
1017                             hdmi_use_enci)
1018                                 continue;
1019
1020                         if (freq == MESON_VCLK_HDMI_DDR_148500 &&
1021                             dac_freq == vclk_freq)
1022                                 continue;
1023
1024                         if (freq == MESON_VCLK_HDMI_148500 &&
1025                             dac_freq != vclk_freq)
1026                                 continue;
1027                         break;
1028                 }
1029         }
1030
1031         if (!params[freq].pixel_freq) {
1032                 pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq);
1033                 return;
1034         }
1035
1036         meson_vclk_set(priv, params[freq].pll_base_freq,
1037                        params[freq].pll_od1, params[freq].pll_od2,
1038                        params[freq].pll_od3, params[freq].vid_pll_div,
1039                        params[freq].vclk_div, hdmi_tx_div, venc_div,
1040                        hdmi_use_enci, vic_alternate_clock);
1041 }
1042 EXPORT_SYMBOL_GPL(meson_vclk_setup);