drivers/gpu/drm/msm/adreno/a6xx.xml.h

   1 #ifndef A6XX_XML
   2 #define A6XX_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
  12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
  13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
  14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
  15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42585 bytes, from 2018-10-04 19:06:37)
  16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
  17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
  18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-10-04 19:06:37)
  19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 139581 bytes, from 2018-10-04 19:06:42)
  20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
  21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
  22
  23 Copyright (C) 2013-2018 by the following authors:
  24 - Rob Clark <robdclark@gmail.com> (robclark)
  25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  26
  27 Permission is hereby granted, free of charge, to any person obtaining
  28 a copy of this software and associated documentation files (the
  29 "Software"), to deal in the Software without restriction, including
  30 without limitation the rights to use, copy, modify, merge, publish,
  31 distribute, sublicense, and/or sell copies of the Software, and to
  32 permit persons to whom the Software is furnished to do so, subject to
  33 the following conditions:
  34
  35 The above copyright notice and this permission notice (including the
  36 next paragraph) shall be included in all copies or substantial
  37 portions of the Software.
  38
  39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  46 */
  47
  48
  49 enum a6xx_color_fmt {
  50         RB6_A8_UNORM = 2,
  51         RB6_R8_UNORM = 3,
  52         RB6_R8_SNORM = 4,
  53         RB6_R8_UINT = 5,
  54         RB6_R8_SINT = 6,
  55         RB6_R4G4B4A4_UNORM = 8,
  56         RB6_R5G5B5A1_UNORM = 10,
  57         RB6_R5G6B5_UNORM = 14,
  58         RB6_R8G8_UNORM = 15,
  59         RB6_R8G8_SNORM = 16,
  60         RB6_R8G8_UINT = 17,
  61         RB6_R8G8_SINT = 18,
  62         RB6_R16_UNORM = 21,
  63         RB6_R16_SNORM = 22,
  64         RB6_R16_FLOAT = 23,
  65         RB6_R16_UINT = 24,
  66         RB6_R16_SINT = 25,
  67         RB6_R8G8B8A8_UNORM = 48,
  68         RB6_R8G8B8_UNORM = 49,
  69         RB6_R8G8B8A8_SNORM = 50,
  70         RB6_R8G8B8A8_UINT = 51,
  71         RB6_R8G8B8A8_SINT = 52,
  72         RB6_R10G10B10A2_UNORM = 55,
  73         RB6_R10G10B10A2_UINT = 58,
  74         RB6_R11G11B10_FLOAT = 66,
  75         RB6_R16G16_UNORM = 67,
  76         RB6_R16G16_SNORM = 68,
  77         RB6_R16G16_FLOAT = 69,
  78         RB6_R16G16_UINT = 70,
  79         RB6_R16G16_SINT = 71,
  80         RB6_R32_FLOAT = 74,
  81         RB6_R32_UINT = 75,
  82         RB6_R32_SINT = 76,
  83         RB6_R16G16B16A16_UNORM = 96,
  84         RB6_R16G16B16A16_SNORM = 97,
  85         RB6_R16G16B16A16_FLOAT = 98,
  86         RB6_R16G16B16A16_UINT = 99,
  87         RB6_R16G16B16A16_SINT = 100,
  88         RB6_R32G32_FLOAT = 103,
  89         RB6_R32G32_UINT = 104,
  90         RB6_R32G32_SINT = 105,
  91         RB6_R32G32B32A32_FLOAT = 130,
  92         RB6_R32G32B32A32_UINT = 131,
  93         RB6_R32G32B32A32_SINT = 132,
  94         RB6_X8Z24_UNORM = 160,
  95 };
  96
  97 enum a6xx_tile_mode {
  98         TILE6_LINEAR = 0,
  99         TILE6_2 = 2,
 100         TILE6_3 = 3,
 101 };
 102
 103 enum a6xx_vtx_fmt {
 104         VFMT6_8_UNORM = 3,
 105         VFMT6_8_SNORM = 4,
 106         VFMT6_8_UINT = 5,
 107         VFMT6_8_SINT = 6,
 108         VFMT6_8_8_UNORM = 15,
 109         VFMT6_8_8_SNORM = 16,
 110         VFMT6_8_8_UINT = 17,
 111         VFMT6_8_8_SINT = 18,
 112         VFMT6_16_UNORM = 21,
 113         VFMT6_16_SNORM = 22,
 114         VFMT6_16_FLOAT = 23,
 115         VFMT6_16_UINT = 24,
 116         VFMT6_16_SINT = 25,
 117         VFMT6_8_8_8_UNORM = 33,
 118         VFMT6_8_8_8_SNORM = 34,
 119         VFMT6_8_8_8_UINT = 35,
 120         VFMT6_8_8_8_SINT = 36,
 121         VFMT6_8_8_8_8_UNORM = 48,
 122         VFMT6_8_8_8_8_SNORM = 50,
 123         VFMT6_8_8_8_8_UINT = 51,
 124         VFMT6_8_8_8_8_SINT = 52,
 125         VFMT6_10_10_10_2_UNORM = 54,
 126         VFMT6_10_10_10_2_SNORM = 57,
 127         VFMT6_10_10_10_2_UINT = 58,
 128         VFMT6_10_10_10_2_SINT = 59,
 129         VFMT6_11_11_10_FLOAT = 66,
 130         VFMT6_16_16_UNORM = 67,
 131         VFMT6_16_16_SNORM = 68,
 132         VFMT6_16_16_FLOAT = 69,
 133         VFMT6_16_16_UINT = 70,
 134         VFMT6_16_16_SINT = 71,
 135         VFMT6_32_UNORM = 72,
 136         VFMT6_32_SNORM = 73,
 137         VFMT6_32_FLOAT = 74,
 138         VFMT6_32_UINT = 75,
 139         VFMT6_32_SINT = 76,
 140         VFMT6_32_FIXED = 77,
 141         VFMT6_16_16_16_UNORM = 88,
 142         VFMT6_16_16_16_SNORM = 89,
 143         VFMT6_16_16_16_FLOAT = 90,
 144         VFMT6_16_16_16_UINT = 91,
 145         VFMT6_16_16_16_SINT = 92,
 146         VFMT6_16_16_16_16_UNORM = 96,
 147         VFMT6_16_16_16_16_SNORM = 97,
 148         VFMT6_16_16_16_16_FLOAT = 98,
 149         VFMT6_16_16_16_16_UINT = 99,
 150         VFMT6_16_16_16_16_SINT = 100,
 151         VFMT6_32_32_UNORM = 101,
 152         VFMT6_32_32_SNORM = 102,
 153         VFMT6_32_32_FLOAT = 103,
 154         VFMT6_32_32_UINT = 104,
 155         VFMT6_32_32_SINT = 105,
 156         VFMT6_32_32_FIXED = 106,
 157         VFMT6_32_32_32_UNORM = 112,
 158         VFMT6_32_32_32_SNORM = 113,
 159         VFMT6_32_32_32_UINT = 114,
 160         VFMT6_32_32_32_SINT = 115,
 161         VFMT6_32_32_32_FLOAT = 116,
 162         VFMT6_32_32_32_FIXED = 117,
 163         VFMT6_32_32_32_32_UNORM = 128,
 164         VFMT6_32_32_32_32_SNORM = 129,
 165         VFMT6_32_32_32_32_FLOAT = 130,
 166         VFMT6_32_32_32_32_UINT = 131,
 167         VFMT6_32_32_32_32_SINT = 132,
 168         VFMT6_32_32_32_32_FIXED = 133,
 169 };
 170
 171 enum a6xx_tex_fmt {
 172         TFMT6_A8_UNORM = 2,
 173         TFMT6_8_UNORM = 3,
 174         TFMT6_8_SNORM = 4,
 175         TFMT6_8_UINT = 5,
 176         TFMT6_8_SINT = 6,
 177         TFMT6_4_4_4_4_UNORM = 8,
 178         TFMT6_5_5_5_1_UNORM = 10,
 179         TFMT6_5_6_5_UNORM = 14,
 180         TFMT6_8_8_UNORM = 15,
 181         TFMT6_8_8_SNORM = 16,
 182         TFMT6_8_8_UINT = 17,
 183         TFMT6_8_8_SINT = 18,
 184         TFMT6_L8_A8_UNORM = 19,
 185         TFMT6_16_UNORM = 21,
 186         TFMT6_16_SNORM = 22,
 187         TFMT6_16_FLOAT = 23,
 188         TFMT6_16_UINT = 24,
 189         TFMT6_16_SINT = 25,
 190         TFMT6_8_8_8_8_UNORM = 48,
 191         TFMT6_8_8_8_UNORM = 49,
 192         TFMT6_8_8_8_8_SNORM = 50,
 193         TFMT6_8_8_8_8_UINT = 51,
 194         TFMT6_8_8_8_8_SINT = 52,
 195         TFMT6_9_9_9_E5_FLOAT = 53,
 196         TFMT6_10_10_10_2_UNORM = 54,
 197         TFMT6_10_10_10_2_UINT = 58,
 198         TFMT6_11_11_10_FLOAT = 66,
 199         TFMT6_16_16_UNORM = 67,
 200         TFMT6_16_16_SNORM = 68,
 201         TFMT6_16_16_FLOAT = 69,
 202         TFMT6_16_16_UINT = 70,
 203         TFMT6_16_16_SINT = 71,
 204         TFMT6_32_FLOAT = 74,
 205         TFMT6_32_UINT = 75,
 206         TFMT6_32_SINT = 76,
 207         TFMT6_16_16_16_16_UNORM = 96,
 208         TFMT6_16_16_16_16_SNORM = 97,
 209         TFMT6_16_16_16_16_FLOAT = 98,
 210         TFMT6_16_16_16_16_UINT = 99,
 211         TFMT6_16_16_16_16_SINT = 100,
 212         TFMT6_32_32_FLOAT = 103,
 213         TFMT6_32_32_UINT = 104,
 214         TFMT6_32_32_SINT = 105,
 215         TFMT6_32_32_32_UINT = 114,
 216         TFMT6_32_32_32_SINT = 115,
 217         TFMT6_32_32_32_FLOAT = 116,
 218         TFMT6_32_32_32_32_FLOAT = 130,
 219         TFMT6_32_32_32_32_UINT = 131,
 220         TFMT6_32_32_32_32_SINT = 132,
 221         TFMT6_X8Z24_UNORM = 160,
 222         TFMT6_ETC2_RG11_UNORM = 171,
 223         TFMT6_ETC2_RG11_SNORM = 172,
 224         TFMT6_ETC2_R11_UNORM = 173,
 225         TFMT6_ETC2_R11_SNORM = 174,
 226         TFMT6_ETC1 = 175,
 227         TFMT6_ETC2_RGB8 = 176,
 228         TFMT6_ETC2_RGBA8 = 177,
 229         TFMT6_ETC2_RGB8A1 = 178,
 230         TFMT6_DXT1 = 179,
 231         TFMT6_DXT3 = 180,
 232         TFMT6_DXT5 = 181,
 233         TFMT6_RGTC1_UNORM = 183,
 234         TFMT6_RGTC1_SNORM = 184,
 235         TFMT6_RGTC2_UNORM = 187,
 236         TFMT6_RGTC2_SNORM = 188,
 237         TFMT6_BPTC_UFLOAT = 190,
 238         TFMT6_BPTC_FLOAT = 191,
 239         TFMT6_BPTC = 192,
 240         TFMT6_ASTC_4x4 = 193,
 241         TFMT6_ASTC_5x4 = 194,
 242         TFMT6_ASTC_5x5 = 195,
 243         TFMT6_ASTC_6x5 = 196,
 244         TFMT6_ASTC_6x6 = 197,
 245         TFMT6_ASTC_8x5 = 198,
 246         TFMT6_ASTC_8x6 = 199,
 247         TFMT6_ASTC_8x8 = 200,
 248         TFMT6_ASTC_10x5 = 201,
 249         TFMT6_ASTC_10x6 = 202,
 250         TFMT6_ASTC_10x8 = 203,
 251         TFMT6_ASTC_10x10 = 204,
 252         TFMT6_ASTC_12x10 = 205,
 253         TFMT6_ASTC_12x12 = 206,
 254 };
 255
 256 enum a6xx_tex_fetchsize {
 257         TFETCH6_1_BYTE = 0,
 258         TFETCH6_2_BYTE = 1,
 259         TFETCH6_4_BYTE = 2,
 260         TFETCH6_8_BYTE = 3,
 261         TFETCH6_16_BYTE = 4,
 262 };
 263
 264 enum a6xx_depth_format {
 265         DEPTH6_NONE = 0,
 266         DEPTH6_16 = 1,
 267         DEPTH6_24_8 = 2,
 268         DEPTH6_32 = 4,
 269 };
 270
 271 enum a6xx_shader_id {
 272         A6XX_TP0_TMO_DATA = 9,
 273         A6XX_TP0_SMO_DATA = 10,
 274         A6XX_TP0_MIPMAP_BASE_DATA = 11,
 275         A6XX_TP1_TMO_DATA = 25,
 276         A6XX_TP1_SMO_DATA = 26,
 277         A6XX_TP1_MIPMAP_BASE_DATA = 27,
 278         A6XX_SP_INST_DATA = 41,
 279         A6XX_SP_LB_0_DATA = 42,
 280         A6XX_SP_LB_1_DATA = 43,
 281         A6XX_SP_LB_2_DATA = 44,
 282         A6XX_SP_LB_3_DATA = 45,
 283         A6XX_SP_LB_4_DATA = 46,
 284         A6XX_SP_LB_5_DATA = 47,
 285         A6XX_SP_CB_BINDLESS_DATA = 48,
 286         A6XX_SP_CB_LEGACY_DATA = 49,
 287         A6XX_SP_UAV_DATA = 50,
 288         A6XX_SP_INST_TAG = 51,
 289         A6XX_SP_CB_BINDLESS_TAG = 52,
 290         A6XX_SP_TMO_UMO_TAG = 53,
 291         A6XX_SP_SMO_TAG = 54,
 292         A6XX_SP_STATE_DATA = 55,
 293         A6XX_HLSQ_CHUNK_CVS_RAM = 73,
 294         A6XX_HLSQ_CHUNK_CPS_RAM = 74,
 295         A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
 296         A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
 297         A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
 298         A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
 299         A6XX_HLSQ_CVS_MISC_RAM = 80,
 300         A6XX_HLSQ_CPS_MISC_RAM = 81,
 301         A6XX_HLSQ_INST_RAM = 82,
 302         A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
 303         A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
 304         A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
 305         A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
 306         A6XX_HLSQ_INST_RAM_TAG = 87,
 307         A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
 308         A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
 309         A6XX_HLSQ_PWR_REST_RAM = 90,
 310         A6XX_HLSQ_PWR_REST_TAG = 91,
 311         A6XX_HLSQ_DATAPATH_META = 96,
 312         A6XX_HLSQ_FRONTEND_META = 97,
 313         A6XX_HLSQ_INDIRECT_META = 98,
 314         A6XX_HLSQ_BACKEND_META = 99,
 315 };
 316
 317 enum a6xx_debugbus_id {
 318         A6XX_DBGBUS_CP = 1,
 319         A6XX_DBGBUS_RBBM = 2,
 320         A6XX_DBGBUS_VBIF = 3,
 321         A6XX_DBGBUS_HLSQ = 4,
 322         A6XX_DBGBUS_UCHE = 5,
 323         A6XX_DBGBUS_DPM = 6,
 324         A6XX_DBGBUS_TESS = 7,
 325         A6XX_DBGBUS_PC = 8,
 326         A6XX_DBGBUS_VFDP = 9,
 327         A6XX_DBGBUS_VPC = 10,
 328         A6XX_DBGBUS_TSE = 11,
 329         A6XX_DBGBUS_RAS = 12,
 330         A6XX_DBGBUS_VSC = 13,
 331         A6XX_DBGBUS_COM = 14,
 332         A6XX_DBGBUS_LRZ = 16,
 333         A6XX_DBGBUS_A2D = 17,
 334         A6XX_DBGBUS_CCUFCHE = 18,
 335         A6XX_DBGBUS_GMU_CX = 19,
 336         A6XX_DBGBUS_RBP = 20,
 337         A6XX_DBGBUS_DCS = 21,
 338         A6XX_DBGBUS_DBGC = 22,
 339         A6XX_DBGBUS_CX = 23,
 340         A6XX_DBGBUS_GMU_GX = 24,
 341         A6XX_DBGBUS_TPFCHE = 25,
 342         A6XX_DBGBUS_GBIF_GX = 26,
 343         A6XX_DBGBUS_GPC = 29,
 344         A6XX_DBGBUS_LARC = 30,
 345         A6XX_DBGBUS_HLSQ_SPTP = 31,
 346         A6XX_DBGBUS_RB_0 = 32,
 347         A6XX_DBGBUS_RB_1 = 33,
 348         A6XX_DBGBUS_UCHE_WRAPPER = 36,
 349         A6XX_DBGBUS_CCU_0 = 40,
 350         A6XX_DBGBUS_CCU_1 = 41,
 351         A6XX_DBGBUS_VFD_0 = 56,
 352         A6XX_DBGBUS_VFD_1 = 57,
 353         A6XX_DBGBUS_VFD_2 = 58,
 354         A6XX_DBGBUS_VFD_3 = 59,
 355         A6XX_DBGBUS_SP_0 = 64,
 356         A6XX_DBGBUS_SP_1 = 65,
 357         A6XX_DBGBUS_TPL1_0 = 72,
 358         A6XX_DBGBUS_TPL1_1 = 73,
 359         A6XX_DBGBUS_TPL1_2 = 74,
 360         A6XX_DBGBUS_TPL1_3 = 75,
 361 };
 362
 363 enum a6xx_cp_perfcounter_select {
 364         PERF_CP_ALWAYS_COUNT = 0,
 365         PERF_CP_BUSY_GFX_CORE_IDLE = 1,
 366         PERF_CP_BUSY_CYCLES = 2,
 367         PERF_CP_NUM_PREEMPTIONS = 3,
 368         PERF_CP_PREEMPTION_REACTION_DELAY = 4,
 369         PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
 370         PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
 371         PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
 372         PERF_CP_PREDICATED_DRAWS_KILLED = 8,
 373         PERF_CP_MODE_SWITCH = 9,
 374         PERF_CP_ZPASS_DONE = 10,
 375         PERF_CP_CONTEXT_DONE = 11,
 376         PERF_CP_CACHE_FLUSH = 12,
 377         PERF_CP_LONG_PREEMPTIONS = 13,
 378         PERF_CP_SQE_I_CACHE_STARVE = 14,
 379         PERF_CP_SQE_IDLE = 15,
 380         PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
 381         PERF_CP_SQE_PM4_STARVE_SDS = 17,
 382         PERF_CP_SQE_MRB_STARVE = 18,
 383         PERF_CP_SQE_RRB_STARVE = 19,
 384         PERF_CP_SQE_VSD_STARVE = 20,
 385         PERF_CP_VSD_DECODE_STARVE = 21,
 386         PERF_CP_SQE_PIPE_OUT_STALL = 22,
 387         PERF_CP_SQE_SYNC_STALL = 23,
 388         PERF_CP_SQE_PM4_WFI_STALL = 24,
 389         PERF_CP_SQE_SYS_WFI_STALL = 25,
 390         PERF_CP_SQE_T4_EXEC = 26,
 391         PERF_CP_SQE_LOAD_STATE_EXEC = 27,
 392         PERF_CP_SQE_SAVE_SDS_STATE = 28,
 393         PERF_CP_SQE_DRAW_EXEC = 29,
 394         PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
 395         PERF_CP_SQE_EXEC_PROFILED = 31,
 396         PERF_CP_MEMORY_POOL_EMPTY = 32,
 397         PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
 398         PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
 399         PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
 400         PERF_CP_AHB_STALL_SQE_GMU = 36,
 401         PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
 402         PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
 403         PERF_CP_CLUSTER0_EMPTY = 39,
 404         PERF_CP_CLUSTER1_EMPTY = 40,
 405         PERF_CP_CLUSTER2_EMPTY = 41,
 406         PERF_CP_CLUSTER3_EMPTY = 42,
 407         PERF_CP_CLUSTER4_EMPTY = 43,
 408         PERF_CP_CLUSTER5_EMPTY = 44,
 409         PERF_CP_PM4_DATA = 45,
 410         PERF_CP_PM4_HEADERS = 46,
 411         PERF_CP_VBIF_READ_BEATS = 47,
 412         PERF_CP_VBIF_WRITE_BEATS = 48,
 413         PERF_CP_SQE_INSTR_COUNTER = 49,
 414 };
 415
 416 enum a6xx_rbbm_perfcounter_select {
 417         PERF_RBBM_ALWAYS_COUNT = 0,
 418         PERF_RBBM_ALWAYS_ON = 1,
 419         PERF_RBBM_TSE_BUSY = 2,
 420         PERF_RBBM_RAS_BUSY = 3,
 421         PERF_RBBM_PC_DCALL_BUSY = 4,
 422         PERF_RBBM_PC_VSD_BUSY = 5,
 423         PERF_RBBM_STATUS_MASKED = 6,
 424         PERF_RBBM_COM_BUSY = 7,
 425         PERF_RBBM_DCOM_BUSY = 8,
 426         PERF_RBBM_VBIF_BUSY = 9,
 427         PERF_RBBM_VSC_BUSY = 10,
 428         PERF_RBBM_TESS_BUSY = 11,
 429         PERF_RBBM_UCHE_BUSY = 12,
 430         PERF_RBBM_HLSQ_BUSY = 13,
 431 };
 432
 433 enum a6xx_pc_perfcounter_select {
 434         PERF_PC_BUSY_CYCLES = 0,
 435         PERF_PC_WORKING_CYCLES = 1,
 436         PERF_PC_STALL_CYCLES_VFD = 2,
 437         PERF_PC_STALL_CYCLES_TSE = 3,
 438         PERF_PC_STALL_CYCLES_VPC = 4,
 439         PERF_PC_STALL_CYCLES_UCHE = 5,
 440         PERF_PC_STALL_CYCLES_TESS = 6,
 441         PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
 442         PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
 443         PERF_PC_PASS1_TF_STALL_CYCLES = 9,
 444         PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
 445         PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
 446         PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
 447         PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
 448         PERF_PC_STARVE_CYCLES_DI = 14,
 449         PERF_PC_VIS_STREAMS_LOADED = 15,
 450         PERF_PC_INSTANCES = 16,
 451         PERF_PC_VPC_PRIMITIVES = 17,
 452         PERF_PC_DEAD_PRIM = 18,
 453         PERF_PC_LIVE_PRIM = 19,
 454         PERF_PC_VERTEX_HITS = 20,
 455         PERF_PC_IA_VERTICES = 21,
 456         PERF_PC_IA_PRIMITIVES = 22,
 457         PERF_PC_GS_PRIMITIVES = 23,
 458         PERF_PC_HS_INVOCATIONS = 24,
 459         PERF_PC_DS_INVOCATIONS = 25,
 460         PERF_PC_VS_INVOCATIONS = 26,
 461         PERF_PC_GS_INVOCATIONS = 27,
 462         PERF_PC_DS_PRIMITIVES = 28,
 463         PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
 464         PERF_PC_3D_DRAWCALLS = 30,
 465         PERF_PC_2D_DRAWCALLS = 31,
 466         PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
 467         PERF_TESS_BUSY_CYCLES = 33,
 468         PERF_TESS_WORKING_CYCLES = 34,
 469         PERF_TESS_STALL_CYCLES_PC = 35,
 470         PERF_TESS_STARVE_CYCLES_PC = 36,
 471         PERF_PC_TSE_TRANSACTION = 37,
 472         PERF_PC_TSE_VERTEX = 38,
 473         PERF_PC_TESS_PC_UV_TRANS = 39,
 474         PERF_PC_TESS_PC_UV_PATCHES = 40,
 475         PERF_PC_TESS_FACTOR_TRANS = 41,
 476 };
 477
 478 enum a6xx_vfd_perfcounter_select {
 479         PERF_VFD_BUSY_CYCLES = 0,
 480         PERF_VFD_STALL_CYCLES_UCHE = 1,
 481         PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
 482         PERF_VFD_STALL_CYCLES_SP_INFO = 3,
 483         PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
 484         PERF_VFD_STARVE_CYCLES_UCHE = 5,
 485         PERF_VFD_RBUFFER_FULL = 6,
 486         PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
 487         PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
 488         PERF_VFD_NUM_ATTRIBUTES = 9,
 489         PERF_VFD_UPPER_SHADER_FIBERS = 10,
 490         PERF_VFD_LOWER_SHADER_FIBERS = 11,
 491         PERF_VFD_MODE_0_FIBERS = 12,
 492         PERF_VFD_MODE_1_FIBERS = 13,
 493         PERF_VFD_MODE_2_FIBERS = 14,
 494         PERF_VFD_MODE_3_FIBERS = 15,
 495         PERF_VFD_MODE_4_FIBERS = 16,
 496         PERF_VFD_TOTAL_VERTICES = 17,
 497         PERF_VFDP_STALL_CYCLES_VFD = 18,
 498         PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
 499         PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
 500         PERF_VFDP_STARVE_CYCLES_PC = 21,
 501         PERF_VFDP_VS_STAGE_WAVES = 22,
 502 };
 503
 504 enum a6xx_hslq_perfcounter_select {
 505         PERF_HLSQ_BUSY_CYCLES = 0,
 506         PERF_HLSQ_STALL_CYCLES_UCHE = 1,
 507         PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
 508         PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
 509         PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
 510         PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
 511         PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
 512         PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
 513         PERF_HLSQ_QUADS = 8,
 514         PERF_HLSQ_CS_INVOCATIONS = 9,
 515         PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
 516         PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
 517         PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
 518         PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
 519         PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
 520         PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
 521         PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
 522         PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
 523         PERF_HLSQ_STALL_CYCLES_VPC = 18,
 524         PERF_HLSQ_PIXELS = 19,
 525         PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
 526 };
 527
 528 enum a6xx_vpc_perfcounter_select {
 529         PERF_VPC_BUSY_CYCLES = 0,
 530         PERF_VPC_WORKING_CYCLES = 1,
 531         PERF_VPC_STALL_CYCLES_UCHE = 2,
 532         PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
 533         PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
 534         PERF_VPC_STALL_CYCLES_PC = 5,
 535         PERF_VPC_STALL_CYCLES_SP_LM = 6,
 536         PERF_VPC_STARVE_CYCLES_SP = 7,
 537         PERF_VPC_STARVE_CYCLES_LRZ = 8,
 538         PERF_VPC_PC_PRIMITIVES = 9,
 539         PERF_VPC_SP_COMPONENTS = 10,
 540         PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
 541         PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
 542         PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
 543         PERF_VPC_LM_TRANSACTION = 14,
 544         PERF_VPC_STREAMOUT_TRANSACTION = 15,
 545         PERF_VPC_VS_BUSY_CYCLES = 16,
 546         PERF_VPC_PS_BUSY_CYCLES = 17,
 547         PERF_VPC_VS_WORKING_CYCLES = 18,
 548         PERF_VPC_PS_WORKING_CYCLES = 19,
 549         PERF_VPC_STARVE_CYCLES_RB = 20,
 550         PERF_VPC_NUM_VPCRAM_READ_POS = 21,
 551         PERF_VPC_WIT_FULL_CYCLES = 22,
 552         PERF_VPC_VPCRAM_FULL_CYCLES = 23,
 553         PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
 554         PERF_VPC_NUM_VPCRAM_WRITE = 25,
 555         PERF_VPC_NUM_VPCRAM_READ_SO = 26,
 556         PERF_VPC_NUM_ATTR_REQ_LM = 27,
 557 };
 558
 559 enum a6xx_tse_perfcounter_select {
 560         PERF_TSE_BUSY_CYCLES = 0,
 561         PERF_TSE_CLIPPING_CYCLES = 1,
 562         PERF_TSE_STALL_CYCLES_RAS = 2,
 563         PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
 564         PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
 565         PERF_TSE_STARVE_CYCLES_PC = 5,
 566         PERF_TSE_INPUT_PRIM = 6,
 567         PERF_TSE_INPUT_NULL_PRIM = 7,
 568         PERF_TSE_TRIVAL_REJ_PRIM = 8,
 569         PERF_TSE_CLIPPED_PRIM = 9,
 570         PERF_TSE_ZERO_AREA_PRIM = 10,
 571         PERF_TSE_FACENESS_CULLED_PRIM = 11,
 572         PERF_TSE_ZERO_PIXEL_PRIM = 12,
 573         PERF_TSE_OUTPUT_NULL_PRIM = 13,
 574         PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
 575         PERF_TSE_CINVOCATION = 15,
 576         PERF_TSE_CPRIMITIVES = 16,
 577         PERF_TSE_2D_INPUT_PRIM = 17,
 578         PERF_TSE_2D_ALIVE_CYCLES = 18,
 579         PERF_TSE_CLIP_PLANES = 19,
 580 };
 581
 582 enum a6xx_ras_perfcounter_select {
 583         PERF_RAS_BUSY_CYCLES = 0,
 584         PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
 585         PERF_RAS_STALL_CYCLES_LRZ = 2,
 586         PERF_RAS_STARVE_CYCLES_TSE = 3,
 587         PERF_RAS_SUPER_TILES = 4,
 588         PERF_RAS_8X4_TILES = 5,
 589         PERF_RAS_MASKGEN_ACTIVE = 6,
 590         PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
 591         PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
 592         PERF_RAS_PRIM_KILLED_INVISILBE = 9,
 593         PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
 594         PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
 595         PERF_RAS_BLOCKS = 12,
 596 };
 597
 598 enum a6xx_uche_perfcounter_select {
 599         PERF_UCHE_BUSY_CYCLES = 0,
 600         PERF_UCHE_STALL_CYCLES_ARBITER = 1,
 601         PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
 602         PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
 603         PERF_UCHE_VBIF_READ_BEATS_TP = 4,
 604         PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
 605         PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
 606         PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
 607         PERF_UCHE_VBIF_READ_BEATS_SP = 8,
 608         PERF_UCHE_READ_REQUESTS_TP = 9,
 609         PERF_UCHE_READ_REQUESTS_VFD = 10,
 610         PERF_UCHE_READ_REQUESTS_HLSQ = 11,
 611         PERF_UCHE_READ_REQUESTS_LRZ = 12,
 612         PERF_UCHE_READ_REQUESTS_SP = 13,
 613         PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
 614         PERF_UCHE_WRITE_REQUESTS_SP = 15,
 615         PERF_UCHE_WRITE_REQUESTS_VPC = 16,
 616         PERF_UCHE_WRITE_REQUESTS_VSC = 17,
 617         PERF_UCHE_EVICTS = 18,
 618         PERF_UCHE_BANK_REQ0 = 19,
 619         PERF_UCHE_BANK_REQ1 = 20,
 620         PERF_UCHE_BANK_REQ2 = 21,
 621         PERF_UCHE_BANK_REQ3 = 22,
 622         PERF_UCHE_BANK_REQ4 = 23,
 623         PERF_UCHE_BANK_REQ5 = 24,
 624         PERF_UCHE_BANK_REQ6 = 25,
 625         PERF_UCHE_BANK_REQ7 = 26,
 626         PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
 627         PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
 628         PERF_UCHE_GMEM_READ_BEATS = 29,
 629         PERF_UCHE_TPH_REF_FULL = 30,
 630         PERF_UCHE_TPH_VICTIM_FULL = 31,
 631         PERF_UCHE_TPH_EXT_FULL = 32,
 632         PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
 633         PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
 634         PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
 635         PERF_UCHE_VBIF_READ_BEATS_PC = 36,
 636         PERF_UCHE_READ_REQUESTS_PC = 37,
 637         PERF_UCHE_RAM_READ_REQ = 38,
 638         PERF_UCHE_RAM_WRITE_REQ = 39,
 639 };
 640
 641 enum a6xx_tp_perfcounter_select {
 642         PERF_TP_BUSY_CYCLES = 0,
 643         PERF_TP_STALL_CYCLES_UCHE = 1,
 644         PERF_TP_LATENCY_CYCLES = 2,
 645         PERF_TP_LATENCY_TRANS = 3,
 646         PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
 647         PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
 648         PERF_TP_L1_CACHELINE_REQUESTS = 6,
 649         PERF_TP_L1_CACHELINE_MISSES = 7,
 650         PERF_TP_SP_TP_TRANS = 8,
 651         PERF_TP_TP_SP_TRANS = 9,
 652         PERF_TP_OUTPUT_PIXELS = 10,
 653         PERF_TP_FILTER_WORKLOAD_16BIT = 11,
 654         PERF_TP_FILTER_WORKLOAD_32BIT = 12,
 655         PERF_TP_QUADS_RECEIVED = 13,
 656         PERF_TP_QUADS_OFFSET = 14,
 657         PERF_TP_QUADS_SHADOW = 15,
 658         PERF_TP_QUADS_ARRAY = 16,
 659         PERF_TP_QUADS_GRADIENT = 17,
 660         PERF_TP_QUADS_1D = 18,
 661         PERF_TP_QUADS_2D = 19,
 662         PERF_TP_QUADS_BUFFER = 20,
 663         PERF_TP_QUADS_3D = 21,
 664         PERF_TP_QUADS_CUBE = 22,
 665         PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
 666         PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
 667         PERF_TP_OUTPUT_PIXELS_POINT = 25,
 668         PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
 669         PERF_TP_OUTPUT_PIXELS_MIP = 27,
 670         PERF_TP_OUTPUT_PIXELS_ANISO = 28,
 671         PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
 672         PERF_TP_FLAG_CACHE_REQUESTS = 30,
 673         PERF_TP_FLAG_CACHE_MISSES = 31,
 674         PERF_TP_L1_5_L2_REQUESTS = 32,
 675         PERF_TP_2D_OUTPUT_PIXELS = 33,
 676         PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
 677         PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
 678         PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
 679         PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
 680         PERF_TP_TPA2TPC_TRANS = 38,
 681         PERF_TP_L1_MISSES_ASTC_1TILE = 39,
 682         PERF_TP_L1_MISSES_ASTC_2TILE = 40,
 683         PERF_TP_L1_MISSES_ASTC_4TILE = 41,
 684         PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
 685         PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
 686         PERF_TP_L1_BANK_CONFLICT = 44,
 687         PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
 688         PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
 689         PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
 690         PERF_TP_FRONTEND_WORKING_CYCLES = 48,
 691         PERF_TP_L1_TAG_WORKING_CYCLES = 49,
 692         PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
 693         PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
 694         PERF_TP_BACKEND_WORKING_CYCLES = 52,
 695         PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
 696         PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
 697         PERF_TP_STARVE_CYCLES_SP = 55,
 698         PERF_TP_STARVE_CYCLES_UCHE = 56,
 699 };
 700
 701 enum a6xx_sp_perfcounter_select {
 702         PERF_SP_BUSY_CYCLES = 0,
 703         PERF_SP_ALU_WORKING_CYCLES = 1,
 704         PERF_SP_EFU_WORKING_CYCLES = 2,
 705         PERF_SP_STALL_CYCLES_VPC = 3,
 706         PERF_SP_STALL_CYCLES_TP = 4,
 707         PERF_SP_STALL_CYCLES_UCHE = 5,
 708         PERF_SP_STALL_CYCLES_RB = 6,
 709         PERF_SP_NON_EXECUTION_CYCLES = 7,
 710         PERF_SP_WAVE_CONTEXTS = 8,
 711         PERF_SP_WAVE_CONTEXT_CYCLES = 9,
 712         PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
 713         PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
 714         PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
 715         PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
 716         PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
 717         PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
 718         PERF_SP_WAVE_CTRL_CYCLES = 16,
 719         PERF_SP_WAVE_LOAD_CYCLES = 17,
 720         PERF_SP_WAVE_EMIT_CYCLES = 18,
 721         PERF_SP_WAVE_NOP_CYCLES = 19,
 722         PERF_SP_WAVE_WAIT_CYCLES = 20,
 723         PERF_SP_WAVE_FETCH_CYCLES = 21,
 724         PERF_SP_WAVE_IDLE_CYCLES = 22,
 725         PERF_SP_WAVE_END_CYCLES = 23,
 726         PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
 727         PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
 728         PERF_SP_WAVE_JOIN_CYCLES = 26,
 729         PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
 730         PERF_SP_LM_STORE_INSTRUCTIONS = 28,
 731         PERF_SP_LM_ATOMICS = 29,
 732         PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
 733         PERF_SP_GM_STORE_INSTRUCTIONS = 31,
 734         PERF_SP_GM_ATOMICS = 32,
 735         PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
 736         PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
 737         PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
 738         PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
 739         PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
 740         PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
 741         PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
 742         PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
 743         PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
 744         PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
 745         PERF_SP_VS_INSTRUCTIONS = 43,
 746         PERF_SP_FS_INSTRUCTIONS = 44,
 747         PERF_SP_ADDR_LOCK_COUNT = 45,
 748         PERF_SP_UCHE_READ_TRANS = 46,
 749         PERF_SP_UCHE_WRITE_TRANS = 47,
 750         PERF_SP_EXPORT_VPC_TRANS = 48,
 751         PERF_SP_EXPORT_RB_TRANS = 49,
 752         PERF_SP_PIXELS_KILLED = 50,
 753         PERF_SP_ICL1_REQUESTS = 51,
 754         PERF_SP_ICL1_MISSES = 52,
 755         PERF_SP_HS_INSTRUCTIONS = 53,
 756         PERF_SP_DS_INSTRUCTIONS = 54,
 757         PERF_SP_GS_INSTRUCTIONS = 55,
 758         PERF_SP_CS_INSTRUCTIONS = 56,
 759         PERF_SP_GPR_READ = 57,
 760         PERF_SP_GPR_WRITE = 58,
 761         PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
 762         PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
 763         PERF_SP_LM_BANK_CONFLICTS = 61,
 764         PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
 765         PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
 766         PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
 767         PERF_SP_LM_WORKING_CYCLES = 65,
 768         PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
 769         PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
 770         PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
 771         PERF_SP_STARVE_CYCLES_HLSQ = 69,
 772         PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
 773         PERF_SP_WORKING_EU = 71,
 774         PERF_SP_ANY_EU_WORKING = 72,
 775         PERF_SP_WORKING_EU_FS_STAGE = 73,
 776         PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
 777         PERF_SP_WORKING_EU_VS_STAGE = 75,
 778         PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
 779         PERF_SP_WORKING_EU_CS_STAGE = 77,
 780         PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
 781         PERF_SP_GPR_READ_PREFETCH = 79,
 782         PERF_SP_GPR_READ_CONFLICT = 80,
 783         PERF_SP_GPR_WRITE_CONFLICT = 81,
 784         PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
 785         PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
 786         PERF_SP_EXECUTABLE_WAVES = 84,
 787 };
 788
 789 enum a6xx_rb_perfcounter_select {
 790         PERF_RB_BUSY_CYCLES = 0,
 791         PERF_RB_STALL_CYCLES_HLSQ = 1,
 792         PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
 793         PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
 794         PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
 795         PERF_RB_STARVE_CYCLES_SP = 5,
 796         PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
 797         PERF_RB_STARVE_CYCLES_CCU = 7,
 798         PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
 799         PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
 800         PERF_RB_Z_WORKLOAD = 10,
 801         PERF_RB_HLSQ_ACTIVE = 11,
 802         PERF_RB_Z_READ = 12,
 803         PERF_RB_Z_WRITE = 13,
 804         PERF_RB_C_READ = 14,
 805         PERF_RB_C_WRITE = 15,
 806         PERF_RB_TOTAL_PASS = 16,
 807         PERF_RB_Z_PASS = 17,
 808         PERF_RB_Z_FAIL = 18,
 809         PERF_RB_S_FAIL = 19,
 810         PERF_RB_BLENDED_FXP_COMPONENTS = 20,
 811         PERF_RB_BLENDED_FP16_COMPONENTS = 21,
 812         PERF_RB_PS_INVOCATIONS = 22,
 813         PERF_RB_2D_ALIVE_CYCLES = 23,
 814         PERF_RB_2D_STALL_CYCLES_A2D = 24,
 815         PERF_RB_2D_STARVE_CYCLES_SRC = 25,
 816         PERF_RB_2D_STARVE_CYCLES_SP = 26,
 817         PERF_RB_2D_STARVE_CYCLES_DST = 27,
 818         PERF_RB_2D_VALID_PIXELS = 28,
 819         PERF_RB_3D_PIXELS = 29,
 820         PERF_RB_BLENDER_WORKING_CYCLES = 30,
 821         PERF_RB_ZPROC_WORKING_CYCLES = 31,
 822         PERF_RB_CPROC_WORKING_CYCLES = 32,
 823         PERF_RB_SAMPLER_WORKING_CYCLES = 33,
 824         PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
 825         PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
 826         PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
 827         PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
 828         PERF_RB_STALL_CYCLES_VPC = 38,
 829         PERF_RB_2D_INPUT_TRANS = 39,
 830         PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
 831         PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
 832         PERF_RB_BLENDED_FP32_COMPONENTS = 42,
 833         PERF_RB_COLOR_PIX_TILES = 43,
 834         PERF_RB_STALL_CYCLES_CCU = 44,
 835         PERF_RB_EARLY_Z_ARB3_GRANT = 45,
 836         PERF_RB_LATE_Z_ARB3_GRANT = 46,
 837         PERF_RB_EARLY_Z_SKIP_GRANT = 47,
 838 };
 839
 840 enum a6xx_vsc_perfcounter_select {
 841         PERF_VSC_BUSY_CYCLES = 0,
 842         PERF_VSC_WORKING_CYCLES = 1,
 843         PERF_VSC_STALL_CYCLES_UCHE = 2,
 844         PERF_VSC_EOT_NUM = 3,
 845         PERF_VSC_INPUT_TILES = 4,
 846 };
 847
 848 enum a6xx_ccu_perfcounter_select {
 849         PERF_CCU_BUSY_CYCLES = 0,
 850         PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
 851         PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
 852         PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
 853         PERF_CCU_DEPTH_BLOCKS = 4,
 854         PERF_CCU_COLOR_BLOCKS = 5,
 855         PERF_CCU_DEPTH_BLOCK_HIT = 6,
 856         PERF_CCU_COLOR_BLOCK_HIT = 7,
 857         PERF_CCU_PARTIAL_BLOCK_READ = 8,
 858         PERF_CCU_GMEM_READ = 9,
 859         PERF_CCU_GMEM_WRITE = 10,
 860         PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
 861         PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
 862         PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
 863         PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
 864         PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
 865         PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
 866         PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
 867         PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
 868         PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
 869         PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
 870         PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
 871         PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
 872         PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
 873         PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
 874         PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
 875         PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
 876         PERF_CCU_2D_RD_REQ = 27,
 877         PERF_CCU_2D_WR_REQ = 28,
 878 };
 879
 880 enum a6xx_lrz_perfcounter_select {
 881         PERF_LRZ_BUSY_CYCLES = 0,
 882         PERF_LRZ_STARVE_CYCLES_RAS = 1,
 883         PERF_LRZ_STALL_CYCLES_RB = 2,
 884         PERF_LRZ_STALL_CYCLES_VSC = 3,
 885         PERF_LRZ_STALL_CYCLES_VPC = 4,
 886         PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
 887         PERF_LRZ_STALL_CYCLES_UCHE = 6,
 888         PERF_LRZ_LRZ_READ = 7,
 889         PERF_LRZ_LRZ_WRITE = 8,
 890         PERF_LRZ_READ_LATENCY = 9,
 891         PERF_LRZ_MERGE_CACHE_UPDATING = 10,
 892         PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
 893         PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
 894         PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
 895         PERF_LRZ_FULL_8X8_TILES = 14,
 896         PERF_LRZ_PARTIAL_8X8_TILES = 15,
 897         PERF_LRZ_TILE_KILLED = 16,
 898         PERF_LRZ_TOTAL_PIXEL = 17,
 899         PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
 900         PERF_LRZ_FULLY_COVERED_TILES = 19,
 901         PERF_LRZ_PARTIAL_COVERED_TILES = 20,
 902         PERF_LRZ_FEEDBACK_ACCEPT = 21,
 903         PERF_LRZ_FEEDBACK_DISCARD = 22,
 904         PERF_LRZ_FEEDBACK_STALL = 23,
 905         PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
 906         PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
 907         PERF_LRZ_STALL_CYCLES_VC = 26,
 908         PERF_LRZ_RAS_MASK_TRANS = 27,
 909 };
 910
 911 enum a6xx_cmp_perfcounter_select {
 912         PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
 913         PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
 914         PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
 915         PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
 916         PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
 917         PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
 918         PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
 919         PERF_CMPDECMP_VBIF_READ_DATA = 7,
 920         PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
 921         PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
 922         PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
 923         PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
 924         PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
 925         PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
 926         PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
 927         PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
 928         PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
 929         PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
 930         PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
 931         PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
 932         PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
 933         PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
 934         PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
 935         PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
 936         PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
 937         PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
 938         PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
 939         PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
 940         PERF_CMPDECMP_2D_RD_DATA = 28,
 941         PERF_CMPDECMP_2D_WR_DATA = 29,
 942         PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
 943         PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
 944         PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
 945         PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
 946         PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
 947         PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
 948         PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
 949         PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
 950         PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
 951         PERF_CMPDECMP_2D_PIXELS = 39,
 952 };
 953
 954 enum a6xx_tex_filter {
 955         A6XX_TEX_NEAREST = 0,
 956         A6XX_TEX_LINEAR = 1,
 957         A6XX_TEX_ANISO = 2,
 958 };
 959
 960 enum a6xx_tex_clamp {
 961         A6XX_TEX_REPEAT = 0,
 962         A6XX_TEX_CLAMP_TO_EDGE = 1,
 963         A6XX_TEX_MIRROR_REPEAT = 2,
 964         A6XX_TEX_CLAMP_TO_BORDER = 3,
 965         A6XX_TEX_MIRROR_CLAMP = 4,
 966 };
 967
 968 enum a6xx_tex_aniso {
 969         A6XX_TEX_ANISO_1 = 0,
 970         A6XX_TEX_ANISO_2 = 1,
 971         A6XX_TEX_ANISO_4 = 2,
 972         A6XX_TEX_ANISO_8 = 3,
 973         A6XX_TEX_ANISO_16 = 4,
 974 };
 975
 976 enum a6xx_tex_swiz {
 977         A6XX_TEX_X = 0,
 978         A6XX_TEX_Y = 1,
 979         A6XX_TEX_Z = 2,
 980         A6XX_TEX_W = 3,
 981         A6XX_TEX_ZERO = 4,
 982         A6XX_TEX_ONE = 5,
 983 };
 984
 985 enum a6xx_tex_type {
 986         A6XX_TEX_1D = 0,
 987         A6XX_TEX_2D = 1,
 988         A6XX_TEX_CUBE = 2,
 989         A6XX_TEX_3D = 3,
 990 };
 991
 992 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE                      0x00000001
 993 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR                       0x00000002
 994 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW        0x00000040
 995 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR                     0x00000080
 996 #define A6XX_RBBM_INT_0_MASK_CP_SW                              0x00000100
 997 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR                        0x00000200
 998 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS              0x00000400
 999 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS              0x00000800
1000 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS                  0x00001000
1001 #define A6XX_RBBM_INT_0_MASK_CP_IB2                             0x00002000
1002 #define A6XX_RBBM_INT_0_MASK_CP_IB1                             0x00004000
1003 #define A6XX_RBBM_INT_0_MASK_CP_RB                              0x00008000
1004 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS                      0x00020000
1005 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS                      0x00040000
1006 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS                  0x00100000
1007 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW              0x00400000
1008 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT                   0x00800000
1009 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS                    0x01000000
1010 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR                     0x02000000
1011 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0                      0x04000000
1012 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1                      0x08000000
1013 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ                       0x40000000
1014 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG                   0x80000000
1015 #define A6XX_CP_INT_CP_OPCODE_ERROR                             0x00000001
1016 #define A6XX_CP_INT_CP_UCODE_ERROR                              0x00000002
1017 #define A6XX_CP_INT_CP_HW_FAULT_ERROR                           0x00000004
1018 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR                0x00000010
1019 #define A6XX_CP_INT_CP_AHB_ERROR                                0x00000020
1020 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR                         0x00000040
1021 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR                      0x00000080
1022 #define REG_A6XX_CP_RB_BASE                                     0x00000800
1023
1024 #define REG_A6XX_CP_RB_BASE_HI                                  0x00000801
1025
1026 #define REG_A6XX_CP_RB_CNTL                                     0x00000802
1027
1028 #define REG_A6XX_CP_RB_RPTR_ADDR_LO                             0x00000804
1029
1030 #define REG_A6XX_CP_RB_RPTR_ADDR_HI                             0x00000805
1031
1032 #define REG_A6XX_CP_RB_RPTR                                     0x00000806
1033
1034 #define REG_A6XX_CP_RB_WPTR                                     0x00000807
1035
1036 #define REG_A6XX_CP_SQE_CNTL                                    0x00000808
1037
1038 #define REG_A6XX_CP_HW_FAULT                                    0x00000821
1039
1040 #define REG_A6XX_CP_INTERRUPT_STATUS                            0x00000823
1041
1042 #define REG_A6XX_CP_PROTECT_STATUS                              0x00000824
1043
1044 #define REG_A6XX_CP_SQE_INSTR_BASE_LO                           0x00000830
1045
1046 #define REG_A6XX_CP_SQE_INSTR_BASE_HI                           0x00000831
1047
1048 #define REG_A6XX_CP_MISC_CNTL                                   0x00000840
1049
1050 #define REG_A6XX_CP_ROQ_THRESHOLDS_1                            0x000008c1
1051
1052 #define REG_A6XX_CP_ROQ_THRESHOLDS_2                            0x000008c2
1053
1054 #define REG_A6XX_CP_MEM_POOL_SIZE                               0x000008c3
1055
1056 #define REG_A6XX_CP_CHICKEN_DBG                                 0x00000841
1057
1058 #define REG_A6XX_CP_ADDR_MODE_CNTL                              0x00000842
1059
1060 #define REG_A6XX_CP_DBG_ECO_CNTL                                0x00000843
1061
1062 #define REG_A6XX_CP_PROTECT_CNTL                                0x0000084f
1063
1064 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1065
1066 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1067
1068 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1069
1070 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1071 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK                     0x0003ffff
1072 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT                    0
1073 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1074 {
1075         return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1076 }
1077 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK                      0x7ffc0000
1078 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT                     18
1079 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1080 {
1081         return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
1082 }
1083 #define A6XX_CP_PROTECT_REG_READ                                0x80000000
1084
1085 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL                         0x000008a0
1086
1087 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO                 0x000008a1
1088
1089 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI                 0x000008a2
1090
1091 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO      0x000008a3
1092
1093 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI      0x000008a4
1094
1095 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO  0x000008a5
1096
1097 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI  0x000008a6
1098
1099 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO     0x000008a7
1100
1101 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI     0x000008a8
1102
1103 #define REG_A6XX_CP_PERFCTR_CP_SEL_0                            0x000008d0
1104
1105 #define REG_A6XX_CP_PERFCTR_CP_SEL_1                            0x000008d1
1106
1107 #define REG_A6XX_CP_PERFCTR_CP_SEL_2                            0x000008d2
1108
1109 #define REG_A6XX_CP_PERFCTR_CP_SEL_3                            0x000008d3
1110
1111 #define REG_A6XX_CP_PERFCTR_CP_SEL_4                            0x000008d4
1112
1113 #define REG_A6XX_CP_PERFCTR_CP_SEL_5                            0x000008d5
1114
1115 #define REG_A6XX_CP_PERFCTR_CP_SEL_6                            0x000008d6
1116
1117 #define REG_A6XX_CP_PERFCTR_CP_SEL_7                            0x000008d7
1118
1119 #define REG_A6XX_CP_PERFCTR_CP_SEL_8                            0x000008d8
1120
1121 #define REG_A6XX_CP_PERFCTR_CP_SEL_9                            0x000008d9
1122
1123 #define REG_A6XX_CP_PERFCTR_CP_SEL_10                           0x000008da
1124
1125 #define REG_A6XX_CP_PERFCTR_CP_SEL_11                           0x000008db
1126
1127 #define REG_A6XX_CP_PERFCTR_CP_SEL_12                           0x000008dc
1128
1129 #define REG_A6XX_CP_PERFCTR_CP_SEL_13                           0x000008dd
1130
1131 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO                        0x00000900
1132
1133 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI                        0x00000901
1134
1135 #define REG_A6XX_CP_CRASH_DUMP_CNTL                             0x00000902
1136
1137 #define REG_A6XX_CP_CRASH_DUMP_STATUS                           0x00000903
1138
1139 #define REG_A6XX_CP_SQE_STAT_ADDR                               0x00000908
1140
1141 #define REG_A6XX_CP_SQE_STAT_DATA                               0x00000909
1142
1143 #define REG_A6XX_CP_DRAW_STATE_ADDR                             0x0000090a
1144
1145 #define REG_A6XX_CP_DRAW_STATE_DATA                             0x0000090b
1146
1147 #define REG_A6XX_CP_ROQ_DBG_ADDR                                0x0000090c
1148
1149 #define REG_A6XX_CP_ROQ_DBG_DATA                                0x0000090d
1150
1151 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR                           0x0000090e
1152
1153 #define REG_A6XX_CP_MEM_POOL_DBG_DATA                           0x0000090f
1154
1155 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR                          0x00000910
1156
1157 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA                          0x00000911
1158
1159 #define REG_A6XX_CP_IB1_BASE                                    0x00000928
1160
1161 #define REG_A6XX_CP_IB1_BASE_HI                                 0x00000929
1162
1163 #define REG_A6XX_CP_IB1_REM_SIZE                                0x0000092a
1164
1165 #define REG_A6XX_CP_IB2_BASE                                    0x0000092b
1166
1167 #define REG_A6XX_CP_IB2_BASE_HI                                 0x0000092c
1168
1169 #define REG_A6XX_CP_IB2_REM_SIZE                                0x0000092d
1170
1171 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO                        0x00000980
1172
1173 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI                        0x00000981
1174
1175 #define REG_A6XX_CP_AHB_CNTL                                    0x0000098d
1176
1177 #define REG_A6XX_CP_APERTURE_CNTL_HOST                          0x00000a00
1178
1179 #define REG_A6XX_CP_APERTURE_CNTL_CD                            0x00000a03
1180
1181 #define REG_A6XX_VSC_ADDR_MODE_CNTL                             0x00000c01
1182
1183 #define REG_A6XX_RBBM_INT_0_STATUS                              0x00000201
1184
1185 #define REG_A6XX_RBBM_STATUS                                    0x00000210
1186 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB                       0x00800000
1187 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP                    0x00400000
1188 #define A6XX_RBBM_STATUS_HLSQ_BUSY                              0x00200000
1189 #define A6XX_RBBM_STATUS_VSC_BUSY                               0x00100000
1190 #define A6XX_RBBM_STATUS_TPL1_BUSY                              0x00080000
1191 #define A6XX_RBBM_STATUS_SP_BUSY                                0x00040000
1192 #define A6XX_RBBM_STATUS_UCHE_BUSY                              0x00020000
1193 #define A6XX_RBBM_STATUS_VPC_BUSY                               0x00010000
1194 #define A6XX_RBBM_STATUS_VFD_BUSY                               0x00008000
1195 #define A6XX_RBBM_STATUS_TESS_BUSY                              0x00004000
1196 #define A6XX_RBBM_STATUS_PC_VSD_BUSY                            0x00002000
1197 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY                          0x00001000
1198 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY                          0x00000800
1199 #define A6XX_RBBM_STATUS_LRZ_BUSY                               0x00000400
1200 #define A6XX_RBBM_STATUS_A2D_BUSY                               0x00000200
1201 #define A6XX_RBBM_STATUS_CCU_BUSY                               0x00000100
1202 #define A6XX_RBBM_STATUS_RB_BUSY                                0x00000080
1203 #define A6XX_RBBM_STATUS_RAS_BUSY                               0x00000040
1204 #define A6XX_RBBM_STATUS_TSE_BUSY                               0x00000020
1205 #define A6XX_RBBM_STATUS_VBIF_BUSY                              0x00000010
1206 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY                          0x00000008
1207 #define A6XX_RBBM_STATUS_CP_BUSY                                0x00000004
1208 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER                  0x00000002
1209 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER                  0x00000001
1210
1211 #define REG_A6XX_RBBM_STATUS3                                   0x00000213
1212
1213 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS                      0x00000215
1214
1215 #define REG_A6XX_RBBM_PERFCTR_CP_0_LO                           0x00000400
1216
1217 #define REG_A6XX_RBBM_PERFCTR_CP_0_HI                           0x00000401
1218
1219 #define REG_A6XX_RBBM_PERFCTR_CP_1_LO                           0x00000402
1220
1221 #define REG_A6XX_RBBM_PERFCTR_CP_1_HI                           0x00000403
1222
1223 #define REG_A6XX_RBBM_PERFCTR_CP_2_LO                           0x00000404
1224
1225 #define REG_A6XX_RBBM_PERFCTR_CP_2_HI                           0x00000405
1226
1227 #define REG_A6XX_RBBM_PERFCTR_CP_3_LO                           0x00000406
1228
1229 #define REG_A6XX_RBBM_PERFCTR_CP_3_HI                           0x00000407
1230
1231 #define REG_A6XX_RBBM_PERFCTR_CP_4_LO                           0x00000408
1232
1233 #define REG_A6XX_RBBM_PERFCTR_CP_4_HI                           0x00000409
1234
1235 #define REG_A6XX_RBBM_PERFCTR_CP_5_LO                           0x0000040a
1236
1237 #define REG_A6XX_RBBM_PERFCTR_CP_5_HI                           0x0000040b
1238
1239 #define REG_A6XX_RBBM_PERFCTR_CP_6_LO                           0x0000040c
1240
1241 #define REG_A6XX_RBBM_PERFCTR_CP_6_HI                           0x0000040d
1242
1243 #define REG_A6XX_RBBM_PERFCTR_CP_7_LO                           0x0000040e
1244
1245 #define REG_A6XX_RBBM_PERFCTR_CP_7_HI                           0x0000040f
1246
1247 #define REG_A6XX_RBBM_PERFCTR_CP_8_LO                           0x00000410
1248
1249 #define REG_A6XX_RBBM_PERFCTR_CP_8_HI                           0x00000411
1250
1251 #define REG_A6XX_RBBM_PERFCTR_CP_9_LO                           0x00000412
1252
1253 #define REG_A6XX_RBBM_PERFCTR_CP_9_HI                           0x00000413
1254
1255 #define REG_A6XX_RBBM_PERFCTR_CP_10_LO                          0x00000414
1256
1257 #define REG_A6XX_RBBM_PERFCTR_CP_10_HI                          0x00000415
1258
1259 #define REG_A6XX_RBBM_PERFCTR_CP_11_LO                          0x00000416
1260
1261 #define REG_A6XX_RBBM_PERFCTR_CP_11_HI                          0x00000417
1262
1263 #define REG_A6XX_RBBM_PERFCTR_CP_12_LO                          0x00000418
1264
1265 #define REG_A6XX_RBBM_PERFCTR_CP_12_HI                          0x00000419
1266
1267 #define REG_A6XX_RBBM_PERFCTR_CP_13_LO                          0x0000041a
1268
1269 #define REG_A6XX_RBBM_PERFCTR_CP_13_HI                          0x0000041b
1270
1271 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO                         0x0000041c
1272
1273 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI                         0x0000041d
1274
1275 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO                         0x0000041e
1276
1277 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI                         0x0000041f
1278
1279 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO                         0x00000420
1280
1281 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI                         0x00000421
1282
1283 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO                         0x00000422
1284
1285 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI                         0x00000423
1286
1287 #define REG_A6XX_RBBM_PERFCTR_PC_0_LO                           0x00000424
1288
1289 #define REG_A6XX_RBBM_PERFCTR_PC_0_HI                           0x00000425
1290
1291 #define REG_A6XX_RBBM_PERFCTR_PC_1_LO                           0x00000426
1292
1293 #define REG_A6XX_RBBM_PERFCTR_PC_1_HI                           0x00000427
1294
1295 #define REG_A6XX_RBBM_PERFCTR_PC_2_LO                           0x00000428
1296
1297 #define REG_A6XX_RBBM_PERFCTR_PC_2_HI                           0x00000429
1298
1299 #define REG_A6XX_RBBM_PERFCTR_PC_3_LO                           0x0000042a
1300
1301 #define REG_A6XX_RBBM_PERFCTR_PC_3_HI                           0x0000042b
1302
1303 #define REG_A6XX_RBBM_PERFCTR_PC_4_LO                           0x0000042c
1304
1305 #define REG_A6XX_RBBM_PERFCTR_PC_4_HI                           0x0000042d
1306
1307 #define REG_A6XX_RBBM_PERFCTR_PC_5_LO                           0x0000042e
1308
1309 #define REG_A6XX_RBBM_PERFCTR_PC_5_HI                           0x0000042f
1310
1311 #define REG_A6XX_RBBM_PERFCTR_PC_6_LO                           0x00000430
1312
1313 #define REG_A6XX_RBBM_PERFCTR_PC_6_HI                           0x00000431
1314
1315 #define REG_A6XX_RBBM_PERFCTR_PC_7_LO                           0x00000432
1316
1317 #define REG_A6XX_RBBM_PERFCTR_PC_7_HI                           0x00000433
1318
1319 #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO                          0x00000434
1320
1321 #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI                          0x00000435
1322
1323 #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO                          0x00000436
1324
1325 #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI                          0x00000437
1326
1327 #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO                          0x00000438
1328
1329 #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI                          0x00000439
1330
1331 #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO                          0x0000043a
1332
1333 #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI                          0x0000043b
1334
1335 #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO                          0x0000043c
1336
1337 #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI                          0x0000043d
1338
1339 #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO                          0x0000043e
1340
1341 #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI                          0x0000043f
1342
1343 #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO                          0x00000440
1344
1345 #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI                          0x00000441
1346
1347 #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO                          0x00000442
1348
1349 #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI                          0x00000443
1350
1351 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO                         0x00000444
1352
1353 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI                         0x00000445
1354
1355 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO                         0x00000446
1356
1357 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI                         0x00000447
1358
1359 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO                         0x00000448
1360
1361 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI                         0x00000449
1362
1363 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO                         0x0000044a
1364
1365 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI                         0x0000044b
1366
1367 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO                         0x0000044c
1368
1369 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI                         0x0000044d
1370
1371 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO                         0x0000044e
1372
1373 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI                         0x0000044f
1374
1375 #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO                          0x00000450
1376
1377 #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI                          0x00000451
1378
1379 #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO                          0x00000452
1380
1381 #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI                          0x00000453
1382
1383 #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO                          0x00000454
1384
1385 #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI                          0x00000455
1386
1387 #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO                          0x00000456
1388
1389 #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI                          0x00000457
1390
1391 #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO                          0x00000458
1392
1393 #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI                          0x00000459
1394
1395 #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO                          0x0000045a
1396
1397 #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI                          0x0000045b
1398
1399 #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO                          0x0000045c
1400
1401 #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI                          0x0000045d
1402
1403 #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO                          0x0000045e
1404
1405 #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI                          0x0000045f
1406
1407 #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO                          0x00000460
1408
1409 #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI                          0x00000461
1410
1411 #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO                          0x00000462
1412
1413 #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI                          0x00000463
1414
1415 #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO                          0x00000464
1416
1417 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI                          0x00000465
1418
1419 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO                          0x00000466
1420
1421 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI                          0x00000467
1422
1423 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO                          0x00000468
1424
1425 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI                          0x00000469
1426
1427 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO                          0x0000046a
1428
1429 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI                          0x00000465
1430
1431 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO                          0x00000466
1432
1433 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI                          0x00000467
1434
1435 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO                          0x00000468
1436
1437 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI                          0x00000469
1438
1439 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO                          0x0000046a
1440
1441 #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI                          0x0000046b
1442
1443 #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO                          0x0000046c
1444
1445 #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI                          0x0000046d
1446
1447 #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO                          0x0000046e
1448
1449 #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI                          0x0000046f
1450
1451 #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO                          0x00000470
1452
1453 #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI                          0x00000471
1454
1455 #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO                          0x00000472
1456
1457 #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI                          0x00000473
1458
1459 #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO                          0x00000474
1460
1461 #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI                          0x00000475
1462
1463 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO                         0x00000476
1464
1465 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI                         0x00000477
1466
1467 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO                         0x00000478
1468
1469 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI                         0x00000479
1470
1471 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO                         0x0000047a
1472
1473 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI                         0x0000047b
1474
1475 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO                         0x0000047c
1476
1477 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI                         0x0000047d
1478
1479 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO                         0x0000047e
1480
1481 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI                         0x0000047f
1482
1483 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO                         0x00000480
1484
1485 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI                         0x00000481
1486
1487 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO                         0x00000482
1488
1489 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI                         0x00000483
1490
1491 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO                         0x00000484
1492
1493 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI                         0x00000485
1494
1495 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO                         0x00000486
1496
1497 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI                         0x00000487
1498
1499 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO                         0x00000488
1500
1501 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI                         0x00000489
1502
1503 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO                        0x0000048a
1504
1505 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI                        0x0000048b
1506
1507 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO                        0x0000048c
1508
1509 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI                        0x0000048d
1510
1511 #define REG_A6XX_RBBM_PERFCTR_TP_0_LO                           0x0000048e
1512
1513 #define REG_A6XX_RBBM_PERFCTR_TP_0_HI                           0x0000048f
1514
1515 #define REG_A6XX_RBBM_PERFCTR_TP_1_LO                           0x00000490
1516
1517 #define REG_A6XX_RBBM_PERFCTR_TP_1_HI                           0x00000491
1518
1519 #define REG_A6XX_RBBM_PERFCTR_TP_2_LO                           0x00000492
1520
1521 #define REG_A6XX_RBBM_PERFCTR_TP_2_HI                           0x00000493
1522
1523 #define REG_A6XX_RBBM_PERFCTR_TP_3_LO                           0x00000494
1524
1525 #define REG_A6XX_RBBM_PERFCTR_TP_3_HI                           0x00000495
1526
1527 #define REG_A6XX_RBBM_PERFCTR_TP_4_LO                           0x00000496
1528
1529 #define REG_A6XX_RBBM_PERFCTR_TP_4_HI                           0x00000497
1530
1531 #define REG_A6XX_RBBM_PERFCTR_TP_5_LO                           0x00000498
1532
1533 #define REG_A6XX_RBBM_PERFCTR_TP_5_HI                           0x00000499
1534
1535 #define REG_A6XX_RBBM_PERFCTR_TP_6_LO                           0x0000049a
1536
1537 #define REG_A6XX_RBBM_PERFCTR_TP_6_HI                           0x0000049b
1538
1539 #define REG_A6XX_RBBM_PERFCTR_TP_7_LO                           0x0000049c
1540
1541 #define REG_A6XX_RBBM_PERFCTR_TP_7_HI                           0x0000049d
1542
1543 #define REG_A6XX_RBBM_PERFCTR_TP_8_LO                           0x0000049e
1544
1545 #define REG_A6XX_RBBM_PERFCTR_TP_8_HI                           0x0000049f
1546
1547 #define REG_A6XX_RBBM_PERFCTR_TP_9_LO                           0x000004a0
1548
1549 #define REG_A6XX_RBBM_PERFCTR_TP_9_HI                           0x000004a1
1550
1551 #define REG_A6XX_RBBM_PERFCTR_TP_10_LO                          0x000004a2
1552
1553 #define REG_A6XX_RBBM_PERFCTR_TP_10_HI                          0x000004a3
1554
1555 #define REG_A6XX_RBBM_PERFCTR_TP_11_LO                          0x000004a4
1556
1557 #define REG_A6XX_RBBM_PERFCTR_TP_11_HI                          0x000004a5
1558
1559 #define REG_A6XX_RBBM_PERFCTR_SP_0_LO                           0x000004a6
1560
1561 #define REG_A6XX_RBBM_PERFCTR_SP_0_HI                           0x000004a7
1562
1563 #define REG_A6XX_RBBM_PERFCTR_SP_1_LO                           0x000004a8
1564
1565 #define REG_A6XX_RBBM_PERFCTR_SP_1_HI                           0x000004a9
1566
1567 #define REG_A6XX_RBBM_PERFCTR_SP_2_LO                           0x000004aa
1568
1569 #define REG_A6XX_RBBM_PERFCTR_SP_2_HI                           0x000004ab
1570
1571 #define REG_A6XX_RBBM_PERFCTR_SP_3_LO                           0x000004ac
1572
1573 #define REG_A6XX_RBBM_PERFCTR_SP_3_HI                           0x000004ad
1574
1575 #define REG_A6XX_RBBM_PERFCTR_SP_4_LO                           0x000004ae
1576
1577 #define REG_A6XX_RBBM_PERFCTR_SP_4_HI                           0x000004af
1578
1579 #define REG_A6XX_RBBM_PERFCTR_SP_5_LO                           0x000004b0
1580
1581 #define REG_A6XX_RBBM_PERFCTR_SP_5_HI                           0x000004b1
1582
1583 #define REG_A6XX_RBBM_PERFCTR_SP_6_LO                           0x000004b2
1584
1585 #define REG_A6XX_RBBM_PERFCTR_SP_6_HI                           0x000004b3
1586
1587 #define REG_A6XX_RBBM_PERFCTR_SP_7_LO                           0x000004b4
1588
1589 #define REG_A6XX_RBBM_PERFCTR_SP_7_HI                           0x000004b5
1590
1591 #define REG_A6XX_RBBM_PERFCTR_SP_8_LO                           0x000004b6
1592
1593 #define REG_A6XX_RBBM_PERFCTR_SP_8_HI                           0x000004b7
1594
1595 #define REG_A6XX_RBBM_PERFCTR_SP_9_LO                           0x000004b8
1596
1597 #define REG_A6XX_RBBM_PERFCTR_SP_9_HI                           0x000004b9
1598
1599 #define REG_A6XX_RBBM_PERFCTR_SP_10_LO                          0x000004ba
1600
1601 #define REG_A6XX_RBBM_PERFCTR_SP_10_HI                          0x000004bb
1602
1603 #define REG_A6XX_RBBM_PERFCTR_SP_11_LO                          0x000004bc
1604
1605 #define REG_A6XX_RBBM_PERFCTR_SP_11_HI                          0x000004bd
1606
1607 #define REG_A6XX_RBBM_PERFCTR_SP_12_LO                          0x000004be
1608
1609 #define REG_A6XX_RBBM_PERFCTR_SP_12_HI                          0x000004bf
1610
1611 #define REG_A6XX_RBBM_PERFCTR_SP_13_LO                          0x000004c0
1612
1613 #define REG_A6XX_RBBM_PERFCTR_SP_13_HI                          0x000004c1
1614
1615 #define REG_A6XX_RBBM_PERFCTR_SP_14_LO                          0x000004c2
1616
1617 #define REG_A6XX_RBBM_PERFCTR_SP_14_HI                          0x000004c3
1618
1619 #define REG_A6XX_RBBM_PERFCTR_SP_15_LO                          0x000004c4
1620
1621 #define REG_A6XX_RBBM_PERFCTR_SP_15_HI                          0x000004c5
1622
1623 #define REG_A6XX_RBBM_PERFCTR_SP_16_LO                          0x000004c6
1624
1625 #define REG_A6XX_RBBM_PERFCTR_SP_16_HI                          0x000004c7
1626
1627 #define REG_A6XX_RBBM_PERFCTR_SP_17_LO                          0x000004c8
1628
1629 #define REG_A6XX_RBBM_PERFCTR_SP_17_HI                          0x000004c9
1630
1631 #define REG_A6XX_RBBM_PERFCTR_SP_18_LO                          0x000004ca
1632
1633 #define REG_A6XX_RBBM_PERFCTR_SP_18_HI                          0x000004cb
1634
1635 #define REG_A6XX_RBBM_PERFCTR_SP_19_LO                          0x000004cc
1636
1637 #define REG_A6XX_RBBM_PERFCTR_SP_19_HI                          0x000004cd
1638
1639 #define REG_A6XX_RBBM_PERFCTR_SP_20_LO                          0x000004ce
1640
1641 #define REG_A6XX_RBBM_PERFCTR_SP_20_HI                          0x000004cf
1642
1643 #define REG_A6XX_RBBM_PERFCTR_SP_21_LO                          0x000004d0
1644
1645 #define REG_A6XX_RBBM_PERFCTR_SP_21_HI                          0x000004d1
1646
1647 #define REG_A6XX_RBBM_PERFCTR_SP_22_LO                          0x000004d2
1648
1649 #define REG_A6XX_RBBM_PERFCTR_SP_22_HI                          0x000004d3
1650
1651 #define REG_A6XX_RBBM_PERFCTR_SP_23_LO                          0x000004d4
1652
1653 #define REG_A6XX_RBBM_PERFCTR_SP_23_HI                          0x000004d5
1654
1655 #define REG_A6XX_RBBM_PERFCTR_RB_0_LO                           0x000004d6
1656
1657 #define REG_A6XX_RBBM_PERFCTR_RB_0_HI                           0x000004d7
1658
1659 #define REG_A6XX_RBBM_PERFCTR_RB_1_LO                           0x000004d8
1660
1661 #define REG_A6XX_RBBM_PERFCTR_RB_1_HI                           0x000004d9
1662
1663 #define REG_A6XX_RBBM_PERFCTR_RB_2_LO                           0x000004da
1664
1665 #define REG_A6XX_RBBM_PERFCTR_RB_2_HI                           0x000004db
1666
1667 #define REG_A6XX_RBBM_PERFCTR_RB_3_LO                           0x000004dc
1668
1669 #define REG_A6XX_RBBM_PERFCTR_RB_3_HI                           0x000004dd
1670
1671 #define REG_A6XX_RBBM_PERFCTR_RB_4_LO                           0x000004de
1672
1673 #define REG_A6XX_RBBM_PERFCTR_RB_4_HI                           0x000004df
1674
1675 #define REG_A6XX_RBBM_PERFCTR_RB_5_LO                           0x000004e0
1676
1677 #define REG_A6XX_RBBM_PERFCTR_RB_5_HI                           0x000004e1
1678
1679 #define REG_A6XX_RBBM_PERFCTR_RB_6_LO                           0x000004e2
1680
1681 #define REG_A6XX_RBBM_PERFCTR_RB_6_HI                           0x000004e3
1682
1683 #define REG_A6XX_RBBM_PERFCTR_RB_7_LO                           0x000004e4
1684
1685 #define REG_A6XX_RBBM_PERFCTR_RB_7_HI                           0x000004e5
1686
1687 #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO                          0x000004e6
1688
1689 #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI                          0x000004e7
1690
1691 #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO                          0x000004e8
1692
1693 #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI                          0x000004e9
1694
1695 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO                          0x000004ea
1696
1697 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI                          0x000004eb
1698
1699 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO                          0x000004ec
1700
1701 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI                          0x000004ed
1702
1703 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO                          0x000004ee
1704
1705 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI                          0x000004ef
1706
1707 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO                          0x000004f0
1708
1709 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI                          0x000004f1
1710
1711 #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO                          0x000004f2
1712
1713 #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI                          0x000004f3
1714
1715 #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO                          0x000004f4
1716
1717 #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI                          0x000004f5
1718
1719 #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO                          0x000004f6
1720
1721 #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI                          0x000004f7
1722
1723 #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO                          0x000004f8
1724
1725 #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI                          0x000004f9
1726
1727 #define REG_A6XX_RBBM_PERFCTR_CNTL                              0x00000500
1728
1729 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0                         0x00000501
1730
1731 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1                         0x00000502
1732
1733 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2                         0x00000503
1734
1735 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3                         0x00000504
1736
1737 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO                     0x00000505
1738
1739 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI                     0x00000506
1740
1741 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0                        0x00000507
1742
1743 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1                        0x00000508
1744
1745 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2                        0x00000509
1746
1747 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3                        0x0000050a
1748
1749 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED                   0x0000050b
1750
1751 #define REG_A6XX_RBBM_ISDB_CNT                                  0x00000533
1752
1753 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL                         0x0000f400
1754
1755 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO                0x0000f800
1756
1757 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI                0x0000f801
1758
1759 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE                   0x0000f802
1760
1761 #define REG_A6XX_RBBM_SECVID_TSB_CNTL                           0x0000f803
1762
1763 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL                 0x0000f810
1764
1765 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL                      0x00000010
1766
1767 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL                   0x0000001f
1768
1769 #define REG_A6XX_RBBM_INT_CLEAR_CMD                             0x00000037
1770
1771 #define REG_A6XX_RBBM_INT_0_MASK                                0x00000038
1772
1773 #define REG_A6XX_RBBM_SP_HYST_CNT                               0x00000042
1774
1775 #define REG_A6XX_RBBM_SW_RESET_CMD                              0x00000043
1776
1777 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT                         0x00000044
1778
1779 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD                        0x00000045
1780
1781 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2                       0x00000046
1782
1783 #define REG_A6XX_RBBM_CLOCK_CNTL                                0x000000ae
1784
1785 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0                            0x000000b0
1786
1787 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1                            0x000000b1
1788
1789 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2                            0x000000b2
1790
1791 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3                            0x000000b3
1792
1793 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0                           0x000000b4
1794
1795 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1                           0x000000b5
1796
1797 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2                           0x000000b6
1798
1799 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3                           0x000000b7
1800
1801 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0                           0x000000b8
1802
1803 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1                           0x000000b9
1804
1805 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2                           0x000000ba
1806
1807 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3                           0x000000bb
1808
1809 #define REG_A6XX_RBBM_CLOCK_HYST_SP0                            0x000000bc
1810
1811 #define REG_A6XX_RBBM_CLOCK_HYST_SP1                            0x000000bd
1812
1813 #define REG_A6XX_RBBM_CLOCK_HYST_SP2                            0x000000be
1814
1815 #define REG_A6XX_RBBM_CLOCK_HYST_SP3                            0x000000bf
1816
1817 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0                            0x000000c0
1818
1819 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1                            0x000000c1
1820
1821 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2                            0x000000c2
1822
1823 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3                            0x000000c3
1824
1825 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0                           0x000000c4
1826
1827 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1                           0x000000c5
1828
1829 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2                           0x000000c6
1830
1831 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3                           0x000000c7
1832
1833 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0                           0x000000c8
1834
1835 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1                           0x000000c9
1836
1837 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2                           0x000000ca
1838
1839 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3                           0x000000cb
1840
1841 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0                           0x000000cc
1842
1843 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1                           0x000000cd
1844
1845 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2                           0x000000ce
1846
1847 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3                           0x000000cf
1848
1849 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0                           0x000000d0
1850
1851 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1                           0x000000d1
1852
1853 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2                           0x000000d2
1854
1855 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3                           0x000000d3
1856
1857 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0                          0x000000d4
1858
1859 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1                          0x000000d5
1860
1861 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2                          0x000000d6
1862
1863 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3                          0x000000d7
1864
1865 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0                          0x000000d8
1866
1867 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1                          0x000000d9
1868
1869 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2                          0x000000da
1870
1871 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3                          0x000000db
1872
1873 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0                          0x000000dc
1874
1875 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1                          0x000000dd
1876
1877 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2                          0x000000de
1878
1879 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3                          0x000000df
1880
1881 #define REG_A6XX_RBBM_CLOCK_HYST_TP0                            0x000000e0
1882
1883 #define REG_A6XX_RBBM_CLOCK_HYST_TP1                            0x000000e1
1884
1885 #define REG_A6XX_RBBM_CLOCK_HYST_TP2                            0x000000e2
1886
1887 #define REG_A6XX_RBBM_CLOCK_HYST_TP3                            0x000000e3
1888
1889 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0                           0x000000e4
1890
1891 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1                           0x000000e5
1892
1893 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2                           0x000000e6
1894
1895 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3                           0x000000e7
1896
1897 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0                           0x000000e8
1898
1899 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1                           0x000000e9
1900
1901 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2                           0x000000ea
1902
1903 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3                           0x000000eb
1904
1905 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0                           0x000000ec
1906
1907 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1                           0x000000ed
1908
1909 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2                           0x000000ee
1910
1911 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3                           0x000000ef
1912
1913 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0                            0x000000f0
1914
1915 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1                            0x000000f1
1916
1917 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2                            0x000000f2
1918
1919 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3                            0x000000f3
1920
1921 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0                           0x000000f4
1922
1923 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1                           0x000000f5
1924
1925 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2                           0x000000f6
1926
1927 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3                           0x000000f7
1928
1929 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0                           0x000000f8
1930
1931 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1                           0x000000f9
1932
1933 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2                           0x000000fa
1934
1935 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3                           0x000000fb
1936
1937 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0                        0x00000100
1938
1939 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1                        0x00000101
1940
1941 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2                        0x00000102
1942
1943 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3                        0x00000103
1944
1945 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC                            0x00000104
1946
1947 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC                           0x00000105
1948
1949 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC                           0x00000106
1950
1951 #define REG_A6XX_RBBM_CLOCK_HYST_RAC                            0x00000107
1952
1953 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM                   0x00000108
1954
1955 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM                  0x00000109
1956
1957 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM                   0x0000010a
1958
1959 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE                           0x0000010b
1960
1961 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE                          0x0000010c
1962
1963 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE                          0x0000010d
1964
1965 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE                          0x0000010e
1966
1967 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE                          0x0000010f
1968
1969 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE                           0x00000110
1970
1971 #define REG_A6XX_RBBM_CLOCK_MODE_VFD                            0x00000111
1972
1973 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD                           0x00000112
1974
1975 #define REG_A6XX_RBBM_CLOCK_HYST_VFD                            0x00000113
1976
1977 #define REG_A6XX_RBBM_CLOCK_MODE_GPC                            0x00000114
1978
1979 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC                           0x00000115
1980
1981 #define REG_A6XX_RBBM_CLOCK_HYST_GPC                            0x00000116
1982
1983 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2                        0x00000117
1984
1985 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX                         0x00000118
1986
1987 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX                        0x00000119
1988
1989 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX                         0x0000011a
1990
1991 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ                           0x0000011b
1992
1993 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ                          0x0000011c
1994
1995 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A                          0x00000600
1996
1997 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B                          0x00000601
1998
1999 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C                          0x00000602
2000
2001 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D                          0x00000603
2002 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK             0x000000ff
2003 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT            0
2004 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
2005 {
2006         return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
2007 }
2008 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK           0x0000ff00
2009 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT          8
2010 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
2011 {
2012         return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
2013 }
2014
2015 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT                          0x00000604
2016 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK                0x0000003f
2017 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT               0
2018 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
2019 {
2020         return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
2021 }
2022 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK                  0x00007000
2023 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT                 12
2024 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
2025 {
2026         return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
2027 }
2028 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK                   0xf0000000
2029 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT                  28
2030 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
2031 {
2032         return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
2033 }
2034
2035 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM                          0x00000605
2036 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK                 0x0f000000
2037 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT                24
2038 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
2039 {
2040         return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
2041 }
2042
2043 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0                         0x00000608
2044
2045 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1                         0x00000609
2046
2047 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2                         0x0000060a
2048
2049 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3                         0x0000060b
2050
2051 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0                        0x0000060c
2052
2053 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1                        0x0000060d
2054
2055 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2                        0x0000060e
2056
2057 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3                        0x0000060f
2058
2059 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0                        0x00000610
2060 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK               0x0000000f
2061 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT              0
2062 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
2063 {
2064         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
2065 }
2066 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK               0x000000f0
2067 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT              4
2068 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
2069 {
2070         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
2071 }
2072 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK               0x00000f00
2073 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT              8
2074 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
2075 {
2076         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
2077 }
2078 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK               0x0000f000
2079 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT              12
2080 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
2081 {
2082         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
2083 }
2084 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK               0x000f0000
2085 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT              16
2086 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
2087 {
2088         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
2089 }
2090 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK               0x00f00000
2091 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT              20
2092 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
2093 {
2094         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
2095 }
2096 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK               0x0f000000
2097 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT              24
2098 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
2099 {
2100         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
2101 }
2102 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK               0xf0000000
2103 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT              28
2104 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
2105 {
2106         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
2107 }
2108
2109 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1                        0x00000611
2110 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK               0x0000000f
2111 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT              0
2112 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
2113 {
2114         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
2115 }
2116 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK               0x000000f0
2117 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT              4
2118 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
2119 {
2120         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
2121 }
2122 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK              0x00000f00
2123 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT             8
2124 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
2125 {
2126         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
2127 }
2128 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK              0x0000f000
2129 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT             12
2130 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
2131 {
2132         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
2133 }
2134 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK              0x000f0000
2135 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT             16
2136 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
2137 {
2138         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
2139 }
2140 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK              0x00f00000
2141 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT             20
2142 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
2143 {
2144         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
2145 }
2146 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK              0x0f000000
2147 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT             24
2148 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
2149 {
2150         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
2151 }
2152 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK              0xf0000000
2153 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT             28
2154 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
2155 {
2156         return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
2157 }
2158
2159 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1                     0x0000062f
2160
2161 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2                     0x00000630
2162
2163 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0                          0x00000cd8
2164
2165 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1                          0x00000cd9
2166
2167 #define REG_A6XX_GRAS_ADDR_MODE_CNTL                            0x00008601
2168
2169 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0                         0x00008610
2170
2171 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1                         0x00008611
2172
2173 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2                         0x00008612
2174
2175 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3                         0x00008613
2176
2177 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0                         0x00008614
2178
2179 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1                         0x00008615
2180
2181 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2                         0x00008616
2182
2183 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3                         0x00008617
2184
2185 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0                         0x00008618
2186
2187 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1                         0x00008619
2188
2189 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2                         0x0000861a
2190
2191 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3                         0x0000861b
2192
2193 #define REG_A6XX_RB_ADDR_MODE_CNTL                              0x00008e05
2194
2195 #define REG_A6XX_RB_NC_MODE_CNTL                                0x00008e08
2196
2197 #define REG_A6XX_RB_PERFCTR_RB_SEL_0                            0x00008e10
2198
2199 #define REG_A6XX_RB_PERFCTR_RB_SEL_1                            0x00008e11
2200
2201 #define REG_A6XX_RB_PERFCTR_RB_SEL_2                            0x00008e12
2202
2203 #define REG_A6XX_RB_PERFCTR_RB_SEL_3                            0x00008e13
2204
2205 #define REG_A6XX_RB_PERFCTR_RB_SEL_4                            0x00008e14
2206
2207 #define REG_A6XX_RB_PERFCTR_RB_SEL_5                            0x00008e15
2208
2209 #define REG_A6XX_RB_PERFCTR_RB_SEL_6                            0x00008e16
2210
2211 #define REG_A6XX_RB_PERFCTR_RB_SEL_7                            0x00008e17
2212
2213 #define REG_A6XX_RB_PERFCTR_CCU_SEL_0                           0x00008e18
2214
2215 #define REG_A6XX_RB_PERFCTR_CCU_SEL_1                           0x00008e19
2216
2217 #define REG_A6XX_RB_PERFCTR_CCU_SEL_2                           0x00008e1a
2218
2219 #define REG_A6XX_RB_PERFCTR_CCU_SEL_3                           0x00008e1b
2220
2221 #define REG_A6XX_RB_PERFCTR_CCU_SEL_4                           0x00008e1c
2222
2223 #define REG_A6XX_RB_PERFCTR_CMP_SEL_0                           0x00008e2c
2224
2225 #define REG_A6XX_RB_PERFCTR_CMP_SEL_1                           0x00008e2d
2226
2227 #define REG_A6XX_RB_PERFCTR_CMP_SEL_2                           0x00008e2e
2228
2229 #define REG_A6XX_RB_PERFCTR_CMP_SEL_3                           0x00008e2f
2230
2231 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD                    0x00008e3d
2232
2233 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE            0x00008e50
2234
2235 #define REG_A6XX_PC_DBG_ECO_CNTL                                0x00009e00
2236
2237 #define REG_A6XX_PC_ADDR_MODE_CNTL                              0x00009e01
2238
2239 #define REG_A6XX_PC_PERFCTR_PC_SEL_0                            0x00009e34
2240
2241 #define REG_A6XX_PC_PERFCTR_PC_SEL_1                            0x00009e35
2242
2243 #define REG_A6XX_PC_PERFCTR_PC_SEL_2                            0x00009e36
2244
2245 #define REG_A6XX_PC_PERFCTR_PC_SEL_3                            0x00009e37
2246
2247 #define REG_A6XX_PC_PERFCTR_PC_SEL_4                            0x00009e38
2248
2249 #define REG_A6XX_PC_PERFCTR_PC_SEL_5                            0x00009e39
2250
2251 #define REG_A6XX_PC_PERFCTR_PC_SEL_6                            0x00009e3a
2252
2253 #define REG_A6XX_PC_PERFCTR_PC_SEL_7                            0x00009e3b
2254
2255 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL                            0x0000be05
2256
2257 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0                        0x0000be10
2258
2259 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1                        0x0000be11
2260
2261 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2                        0x0000be12
2262
2263 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3                        0x0000be13
2264
2265 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4                        0x0000be14
2266
2267 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5                        0x0000be15
2268
2269 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE                     0x0000c800
2270
2271 #define REG_A6XX_HLSQ_DBG_READ_SEL                              0x0000d000
2272
2273 #define REG_A6XX_VFD_ADDR_MODE_CNTL                             0x0000a601
2274
2275 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0                          0x0000a610
2276
2277 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1                          0x0000a611
2278
2279 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2                          0x0000a612
2280
2281 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3                          0x0000a613
2282
2283 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4                          0x0000a614
2284
2285 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5                          0x0000a615
2286
2287 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6                          0x0000a616
2288
2289 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7                          0x0000a617
2290
2291 #define REG_A6XX_VPC_ADDR_MODE_CNTL                             0x00009601
2292
2293 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0                          0x00009604
2294
2295 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1                          0x00009605
2296
2297 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2                          0x00009606
2298
2299 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3                          0x00009607
2300
2301 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4                          0x00009608
2302
2303 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5                          0x00009609
2304
2305 #define REG_A6XX_UCHE_ADDR_MODE_CNTL                            0x00000e00
2306
2307 #define REG_A6XX_UCHE_MODE_CNTL                                 0x00000e01
2308
2309 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO                        0x00000e05
2310
2311 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI                        0x00000e06
2312
2313 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO                        0x00000e07
2314
2315 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI                        0x00000e08
2316
2317 #define REG_A6XX_UCHE_TRAP_BASE_LO                              0x00000e09
2318
2319 #define REG_A6XX_UCHE_TRAP_BASE_HI                              0x00000e0a
2320
2321 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO                         0x00000e0b
2322
2323 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI                         0x00000e0c
2324
2325 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO                         0x00000e0d
2326
2327 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI                         0x00000e0e
2328
2329 #define REG_A6XX_UCHE_CACHE_WAYS                                0x00000e17
2330
2331 #define REG_A6XX_UCHE_FILTER_CNTL                               0x00000e18
2332
2333 #define REG_A6XX_UCHE_CLIENT_PF                                 0x00000e19
2334 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK                       0x000000ff
2335 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT                      0
2336 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
2337 {
2338         return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
2339 }
2340
2341 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0                        0x00000e1c
2342
2343 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1                        0x00000e1d
2344
2345 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2                        0x00000e1e
2346
2347 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3                        0x00000e1f
2348
2349 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4                        0x00000e20
2350
2351 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5                        0x00000e21
2352
2353 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6                        0x00000e22
2354
2355 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7                        0x00000e23
2356
2357 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8                        0x00000e24
2358
2359 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9                        0x00000e25
2360
2361 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10                       0x00000e26
2362
2363 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11                       0x00000e27
2364
2365 #define REG_A6XX_SP_ADDR_MODE_CNTL                              0x0000ae01
2366
2367 #define REG_A6XX_SP_NC_MODE_CNTL                                0x0000ae02
2368
2369 #define REG_A6XX_SP_PERFCTR_SP_SEL_0                            0x0000ae10
2370
2371 #define REG_A6XX_SP_PERFCTR_SP_SEL_1                            0x0000ae11
2372
2373 #define REG_A6XX_SP_PERFCTR_SP_SEL_2                            0x0000ae12
2374
2375 #define REG_A6XX_SP_PERFCTR_SP_SEL_3                            0x0000ae13
2376
2377 #define REG_A6XX_SP_PERFCTR_SP_SEL_4                            0x0000ae14
2378
2379 #define REG_A6XX_SP_PERFCTR_SP_SEL_5                            0x0000ae15
2380
2381 #define REG_A6XX_SP_PERFCTR_SP_SEL_6                            0x0000ae16
2382
2383 #define REG_A6XX_SP_PERFCTR_SP_SEL_7                            0x0000ae17
2384
2385 #define REG_A6XX_SP_PERFCTR_SP_SEL_8                            0x0000ae18
2386
2387 #define REG_A6XX_SP_PERFCTR_SP_SEL_9                            0x0000ae19
2388
2389 #define REG_A6XX_SP_PERFCTR_SP_SEL_10                           0x0000ae1a
2390
2391 #define REG_A6XX_SP_PERFCTR_SP_SEL_11                           0x0000ae1b
2392
2393 #define REG_A6XX_SP_PERFCTR_SP_SEL_12                           0x0000ae1c
2394
2395 #define REG_A6XX_SP_PERFCTR_SP_SEL_13                           0x0000ae1d
2396
2397 #define REG_A6XX_SP_PERFCTR_SP_SEL_14                           0x0000ae1e
2398
2399 #define REG_A6XX_SP_PERFCTR_SP_SEL_15                           0x0000ae1f
2400
2401 #define REG_A6XX_SP_PERFCTR_SP_SEL_16                           0x0000ae20
2402
2403 #define REG_A6XX_SP_PERFCTR_SP_SEL_17                           0x0000ae21
2404
2405 #define REG_A6XX_SP_PERFCTR_SP_SEL_18                           0x0000ae22
2406
2407 #define REG_A6XX_SP_PERFCTR_SP_SEL_19                           0x0000ae23
2408
2409 #define REG_A6XX_SP_PERFCTR_SP_SEL_20                           0x0000ae24
2410
2411 #define REG_A6XX_SP_PERFCTR_SP_SEL_21                           0x0000ae25
2412
2413 #define REG_A6XX_SP_PERFCTR_SP_SEL_22                           0x0000ae26
2414
2415 #define REG_A6XX_SP_PERFCTR_SP_SEL_23                           0x0000ae27
2416
2417 #define REG_A6XX_TPL1_ADDR_MODE_CNTL                            0x0000b601
2418
2419 #define REG_A6XX_TPL1_NC_MODE_CNTL                              0x0000b604
2420
2421 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0                          0x0000b610
2422
2423 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1                          0x0000b611
2424
2425 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2                          0x0000b612
2426
2427 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3                          0x0000b613
2428
2429 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4                          0x0000b614
2430
2431 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5                          0x0000b615
2432
2433 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6                          0x0000b616
2434
2435 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7                          0x0000b617
2436
2437 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8                          0x0000b618
2438
2439 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9                          0x0000b619
2440
2441 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10                         0x0000b61a
2442
2443 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11                         0x0000b61b
2444
2445 #define REG_A6XX_VBIF_VERSION                                   0x00003000
2446
2447 #define REG_A6XX_VBIF_CLKON                                     0x00003001
2448 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS                        0x00000002
2449
2450 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN                         0x0000302a
2451
2452 #define REG_A6XX_VBIF_XIN_HALT_CTRL0                            0x00003080
2453
2454 #define REG_A6XX_VBIF_XIN_HALT_CTRL1                            0x00003081
2455
2456 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL                         0x00003084
2457
2458 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0                           0x00003085
2459
2460 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1                           0x00003086
2461 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK                0x0000000f
2462 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT               0
2463 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
2464 {
2465         return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
2466 }
2467
2468 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0                           0x00003087
2469
2470 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1                           0x00003088
2471 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK                0x000001ff
2472 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT               0
2473 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
2474 {
2475         return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
2476 }
2477
2478 #define REG_A6XX_VBIF_TEST_BUS_OUT                              0x0000308c
2479
2480 #define REG_A6XX_VBIF_PERF_CNT_SEL0                             0x000030d0
2481
2482 #define REG_A6XX_VBIF_PERF_CNT_SEL1                             0x000030d1
2483
2484 #define REG_A6XX_VBIF_PERF_CNT_SEL2                             0x000030d2
2485
2486 #define REG_A6XX_VBIF_PERF_CNT_SEL3                             0x000030d3
2487
2488 #define REG_A6XX_VBIF_PERF_CNT_LOW0                             0x000030d8
2489
2490 #define REG_A6XX_VBIF_PERF_CNT_LOW1                             0x000030d9
2491
2492 #define REG_A6XX_VBIF_PERF_CNT_LOW2                             0x000030da
2493
2494 #define REG_A6XX_VBIF_PERF_CNT_LOW3                             0x000030db
2495
2496 #define REG_A6XX_VBIF_PERF_CNT_HIGH0                            0x000030e0
2497
2498 #define REG_A6XX_VBIF_PERF_CNT_HIGH1                            0x000030e1
2499
2500 #define REG_A6XX_VBIF_PERF_CNT_HIGH2                            0x000030e2
2501
2502 #define REG_A6XX_VBIF_PERF_CNT_HIGH3                            0x000030e3
2503
2504 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0                          0x00003100
2505
2506 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1                          0x00003101
2507
2508 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2                          0x00003102
2509
2510 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0                         0x00003110
2511
2512 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1                         0x00003111
2513
2514 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2                         0x00003112
2515
2516 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0                        0x00003118
2517
2518 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1                        0x00003119
2519
2520 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2                        0x0000311a
2521
2522 #define REG_A6XX_RB_WINDOW_OFFSET2                              0x000088d4
2523 #define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE            0x80000000
2524 #define A6XX_RB_WINDOW_OFFSET2_X__MASK                          0x00007fff
2525 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT                         0
2526 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
2527 {
2528         return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
2529 }
2530 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK                          0x7fff0000
2531 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT                         16
2532 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
2533 {
2534         return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
2535 }
2536
2537 #define REG_A6XX_SP_WINDOW_OFFSET                               0x0000b4d1
2538 #define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE             0x80000000
2539 #define A6XX_SP_WINDOW_OFFSET_X__MASK                           0x00007fff
2540 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT                          0
2541 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
2542 {
2543         return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
2544 }
2545 #define A6XX_SP_WINDOW_OFFSET_Y__MASK                           0x7fff0000
2546 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT                          16
2547 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
2548 {
2549         return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
2550 }
2551
2552 #define REG_A6XX_SP_TP_WINDOW_OFFSET                            0x0000b307
2553 #define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE          0x80000000
2554 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK                        0x00007fff
2555 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT                       0
2556 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
2557 {
2558         return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
2559 }
2560 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK                        0x7fff0000
2561 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT                       16
2562 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
2563 {
2564         return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
2565 }
2566
2567 #define REG_A6XX_GRAS_BIN_CONTROL                               0x000080a1
2568 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK                        0x000000ff
2569 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT                       0
2570 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
2571 {
2572         return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
2573 }
2574 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK                        0x0001ff00
2575 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT                       8
2576 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
2577 {
2578         return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
2579 }
2580 #define A6XX_GRAS_BIN_CONTROL_BINNING_PASS                      0x00040000
2581 #define A6XX_GRAS_BIN_CONTROL_USE_VIZ                           0x00200000
2582
2583 #define REG_A6XX_RB_BIN_CONTROL2                                0x000088d3
2584 #define A6XX_RB_BIN_CONTROL2_BINW__MASK                         0x000000ff
2585 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT                        0
2586 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
2587 {
2588         return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
2589 }
2590 #define A6XX_RB_BIN_CONTROL2_BINH__MASK                         0x0001ff00
2591 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT                        8
2592 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
2593 {
2594         return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
2595 }
2596
2597 #define REG_A6XX_VSC_BIN_SIZE                                   0x00000c02
2598 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK                           0x000000ff
2599 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT                          0
2600 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2601 {
2602         return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
2603 }
2604 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK                          0x0001ff00
2605 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT                         8
2606 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2607 {
2608         return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2609 }
2610
2611 #define REG_A6XX_VSC_SIZE_ADDRESS_LO                            0x00000c03
2612
2613 #define REG_A6XX_VSC_SIZE_ADDRESS_HI                            0x00000c04
2614
2615 #define REG_A6XX_VSC_BIN_COUNT                                  0x00000c06
2616 #define A6XX_VSC_BIN_COUNT_NX__MASK                             0x000007fe
2617 #define A6XX_VSC_BIN_COUNT_NX__SHIFT                            1
2618 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
2619 {
2620         return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
2621 }
2622 #define A6XX_VSC_BIN_COUNT_NY__MASK                             0x001ff800
2623 #define A6XX_VSC_BIN_COUNT_NY__SHIFT                            11
2624 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
2625 {
2626         return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
2627 }
2628
2629 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2630
2631 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2632 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK                        0x000003ff
2633 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT                       0
2634 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2635 {
2636         return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
2637 }
2638 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK                        0x000ffc00
2639 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT                       10
2640 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2641 {
2642         return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2643 }
2644 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK                        0x03f00000
2645 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT                       20
2646 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2647 {
2648         return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
2649 }
2650 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK                        0xfc000000
2651 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT                       26
2652 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2653 {
2654         return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2655 }
2656
2657 #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO                      0x00000c30
2658
2659 #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI                      0x00000c31
2660
2661 #define REG_A6XX_VSC_PIPE_DATA2_PITCH                           0x00000c32
2662
2663 #define REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH                     0x00000c33
2664 #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK                   0xffffffff
2665 #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT                  0
2666 static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val)
2667 {
2668         return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK;
2669 }
2670
2671 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO                       0x00000c34
2672
2673 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI                       0x00000c35
2674
2675 #define REG_A6XX_VSC_PIPE_DATA_PITCH                            0x00000c36
2676
2677 #define REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH                      0x00000c37
2678 #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK                    0xffffffff
2679 #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT                   0
2680 static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val)
2681 {
2682         return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK;
2683 }
2684
2685 static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2686
2687 static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2688
2689 #define REG_A6XX_UCHE_UNKNOWN_0E12                              0x00000e12
2690
2691 #define REG_A6XX_GRAS_UNKNOWN_8000                              0x00008000
2692
2693 #define REG_A6XX_GRAS_UNKNOWN_8001                              0x00008001
2694
2695 #define REG_A6XX_GRAS_UNKNOWN_8004                              0x00008004
2696
2697 #define REG_A6XX_GRAS_CNTL                                      0x00008005
2698 #define A6XX_GRAS_CNTL_VARYING                                  0x00000001
2699 #define A6XX_GRAS_CNTL_UNK3                                     0x00000008
2700 #define A6XX_GRAS_CNTL_XCOORD                                   0x00000040
2701 #define A6XX_GRAS_CNTL_YCOORD                                   0x00000080
2702 #define A6XX_GRAS_CNTL_ZCOORD                                   0x00000100
2703 #define A6XX_GRAS_CNTL_WCOORD                                   0x00000200
2704
2705 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ                     0x00008006
2706 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK              0x000003ff
2707 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT             0
2708 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2709 {
2710         return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2711 }
2712 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK              0x000ffc00
2713 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT             10
2714 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2715 {
2716         return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2717 }
2718
2719 #define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0                        0x00008010
2720 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK                      0xffffffff
2721 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT                     0
2722 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2723 {
2724         return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2725 }
2726
2727 #define REG_A6XX_GRAS_CL_VPORT_XSCALE_0                         0x00008011
2728 #define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK                       0xffffffff
2729 #define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT                      0
2730 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val)
2731 {
2732         return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2733 }
2734
2735 #define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0                        0x00008012
2736 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK                      0xffffffff
2737 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT                     0
2738 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2739 {
2740         return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2741 }
2742
2743 #define REG_A6XX_GRAS_CL_VPORT_YSCALE_0                         0x00008013
2744 #define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK                       0xffffffff
2745 #define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT                      0
2746 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val)
2747 {
2748         return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2749 }
2750
2751 #define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0                        0x00008014
2752 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK                      0xffffffff
2753 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT                     0
2754 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2755 {
2756         return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2757 }
2758
2759 #define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0                         0x00008015
2760 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK                       0xffffffff
2761 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT                      0
2762 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2763 {
2764         return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2765 }
2766
2767 #define REG_A6XX_GRAS_SU_CNTL                                   0x00008090
2768 #define A6XX_GRAS_SU_CNTL_CULL_FRONT                            0x00000001
2769 #define A6XX_GRAS_SU_CNTL_CULL_BACK                             0x00000002
2770 #define A6XX_GRAS_SU_CNTL_FRONT_CW                              0x00000004
2771 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK                   0x000007f8
2772 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT                  3
2773 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2774 {
2775         return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2776 }
2777 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET                           0x00000800
2778 #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE                           0x00002000
2779
2780 #define REG_A6XX_GRAS_SU_POINT_MINMAX                           0x00008091
2781 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK                     0x0000ffff
2782 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT                    0
2783 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2784 {
2785         return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2786 }
2787 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK                     0xffff0000
2788 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT                    16
2789 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2790 {
2791         return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2792 }
2793
2794 #define REG_A6XX_GRAS_SU_POINT_SIZE                             0x00008092
2795 #define A6XX_GRAS_SU_POINT_SIZE__MASK                           0xffffffff
2796 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT                          0
2797 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
2798 {
2799         return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2800 }
2801
2802 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL                       0x00008094
2803 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z             0x00000001
2804
2805 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE                      0x00008095
2806 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK                    0xffffffff
2807 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT                   0
2808 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2809 {
2810         return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2811 }
2812
2813 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET                     0x00008096
2814 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK                   0xffffffff
2815 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                  0
2816 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2817 {
2818         return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2819 }
2820
2821 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP               0x00008097
2822 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK             0xffffffff
2823 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT            0
2824 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2825 {
2826         return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2827 }
2828
2829 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO                      0x00008098
2830 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK       0x00000007
2831 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT      0
2832 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2833 {
2834         return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2835 }
2836
2837 #define REG_A6XX_GRAS_UNKNOWN_8099                              0x00008099
2838
2839 #define REG_A6XX_GRAS_UNKNOWN_809B                              0x0000809b
2840
2841 #define REG_A6XX_GRAS_UNKNOWN_80A0                              0x000080a0
2842
2843 #define REG_A6XX_GRAS_RAS_MSAA_CNTL                             0x000080a2
2844 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK                   0x00000003
2845 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT                  0
2846 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2847 {
2848         return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2849 }
2850
2851 #define REG_A6XX_GRAS_DEST_MSAA_CNTL                            0x000080a3
2852 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK                  0x00000003
2853 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT                 0
2854 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2855 {
2856         return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
2857 }
2858 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE                   0x00000004
2859
2860 #define REG_A6XX_GRAS_UNKNOWN_80A4                              0x000080a4
2861
2862 #define REG_A6XX_GRAS_UNKNOWN_80A5                              0x000080a5
2863
2864 #define REG_A6XX_GRAS_UNKNOWN_80A6                              0x000080a6
2865
2866 #define REG_A6XX_GRAS_UNKNOWN_80AF                              0x000080af
2867
2868 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0                    0x000080b0
2869 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE  0x80000000
2870 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK                0x00007fff
2871 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT               0
2872 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2873 {
2874         return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2875 }
2876 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK                0x7fff0000
2877 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT               16
2878 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2879 {
2880         return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2881 }
2882
2883 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0                    0x000080b1
2884 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE  0x80000000
2885 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK                0x00007fff
2886 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT               0
2887 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2888 {
2889         return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2890 }
2891 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK                0x7fff0000
2892 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT               16
2893 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2894 {
2895         return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2896 }
2897
2898 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0                  0x000080d0
2899 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE        0x80000000
2900 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK              0x00007fff
2901 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT             0
2902 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2903 {
2904         return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2905 }
2906 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK              0x7fff0000
2907 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT             16
2908 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2909 {
2910         return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2911 }
2912
2913 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0                  0x000080d1
2914 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE        0x80000000
2915 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK              0x00007fff
2916 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT             0
2917 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2918 {
2919         return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2920 }
2921 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK              0x7fff0000
2922 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT             16
2923 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2924 {
2925         return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2926 }
2927
2928 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL                      0x000080f0
2929 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
2930 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK                  0x00007fff
2931 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT                 0
2932 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2933 {
2934         return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2935 }
2936 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK                  0x7fff0000
2937 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT                 16
2938 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2939 {
2940         return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2941 }
2942
2943 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR                      0x000080f1
2944 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
2945 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK                  0x00007fff
2946 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT                 0
2947 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2948 {
2949         return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2950 }
2951 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK                  0x7fff0000
2952 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT                 16
2953 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2954 {
2955         return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2956 }
2957
2958 #define REG_A6XX_GRAS_LRZ_CNTL                                  0x00008100
2959 #define A6XX_GRAS_LRZ_CNTL_ENABLE                               0x00000001
2960 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE                            0x00000002
2961 #define A6XX_GRAS_LRZ_CNTL_GREATER                              0x00000004
2962
2963 #define REG_A6XX_GRAS_UNKNOWN_8101                              0x00008101
2964
2965 #define REG_A6XX_GRAS_2D_BLIT_INFO                              0x00008102
2966 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK               0x000000ff
2967 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT              0
2968 static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
2969 {
2970         return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
2971 }
2972
2973 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO                        0x00008103
2974
2975 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI                        0x00008104
2976
2977 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH                          0x00008105
2978 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK                  0x000007ff
2979 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT                 0
2980 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
2981 {
2982         return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
2983 }
2984 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK            0x003ff800
2985 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT           11
2986 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
2987 {
2988         return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
2989 }
2990
2991 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO             0x00008106
2992
2993 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI             0x00008107
2994
2995 #define REG_A6XX_GRAS_UNKNOWN_8109                              0x00008109
2996
2997 #define REG_A6XX_GRAS_UNKNOWN_8110                              0x00008110
2998
2999 #define REG_A6XX_GRAS_2D_BLIT_CNTL                              0x00008400
3000
3001 #define REG_A6XX_GRAS_2D_SRC_TL_X                               0x00008401
3002 #define A6XX_GRAS_2D_SRC_TL_X_X__MASK                           0x00ffff00
3003 #define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT                          8
3004 static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val)
3005 {
3006         return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK;
3007 }
3008
3009 #define REG_A6XX_GRAS_2D_SRC_BR_X                               0x00008402
3010 #define A6XX_GRAS_2D_SRC_BR_X_X__MASK                           0x00ffff00
3011 #define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT                          8
3012 static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val)
3013 {
3014         return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK;
3015 }
3016
3017 #define REG_A6XX_GRAS_2D_SRC_TL_Y                               0x00008403
3018 #define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK                           0x00ffff00
3019 #define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT                          8
3020 static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val)
3021 {
3022         return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK;
3023 }
3024
3025 #define REG_A6XX_GRAS_2D_SRC_BR_Y                               0x00008404
3026 #define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK                           0x00ffff00
3027 #define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT                          8
3028 static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val)
3029 {
3030         return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK;
3031 }
3032
3033 #define REG_A6XX_GRAS_2D_DST_TL                                 0x00008405
3034 #define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE               0x80000000
3035 #define A6XX_GRAS_2D_DST_TL_X__MASK                             0x00007fff
3036 #define A6XX_GRAS_2D_DST_TL_X__SHIFT                            0
3037 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
3038 {
3039         return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
3040 }
3041 #define A6XX_GRAS_2D_DST_TL_Y__MASK                             0x7fff0000
3042 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT                            16
3043 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
3044 {
3045         return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
3046 }
3047
3048 #define REG_A6XX_GRAS_2D_DST_BR                                 0x00008406
3049 #define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE               0x80000000
3050 #define A6XX_GRAS_2D_DST_BR_X__MASK                             0x00007fff
3051 #define A6XX_GRAS_2D_DST_BR_X__SHIFT                            0
3052 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
3053 {
3054         return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
3055 }
3056 #define A6XX_GRAS_2D_DST_BR_Y__MASK                             0x7fff0000
3057 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT                            16
3058 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
3059 {
3060         return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
3061 }
3062
3063 #define REG_A6XX_GRAS_RESOLVE_CNTL_1                            0x0000840a
3064 #define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE          0x80000000
3065 #define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK                        0x00007fff
3066 #define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT                       0
3067 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val)
3068 {
3069         return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK;
3070 }
3071 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK                        0x7fff0000
3072 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT                       16
3073 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val)
3074 {
3075         return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK;
3076 }
3077
3078 #define REG_A6XX_GRAS_RESOLVE_CNTL_2                            0x0000840b
3079 #define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE          0x80000000
3080 #define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK                        0x00007fff
3081 #define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT                       0
3082 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val)
3083 {
3084         return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK;
3085 }
3086 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK                        0x7fff0000
3087 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT                       16
3088 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val)
3089 {
3090         return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK;
3091 }
3092
3093 #define REG_A6XX_GRAS_UNKNOWN_8600                              0x00008600
3094
3095 #define REG_A6XX_RB_BIN_CONTROL                                 0x00008800
3096 #define A6XX_RB_BIN_CONTROL_BINW__MASK                          0x000000ff
3097 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT                         0
3098 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
3099 {
3100         return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
3101 }
3102 #define A6XX_RB_BIN_CONTROL_BINH__MASK                          0x0001ff00
3103 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT                         8
3104 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
3105 {
3106         return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
3107 }
3108 #define A6XX_RB_BIN_CONTROL_BINNING_PASS                        0x00040000
3109 #define A6XX_RB_BIN_CONTROL_USE_VIZ                             0x00200000
3110
3111 #define REG_A6XX_RB_RENDER_CNTL                                 0x00008801
3112 #define A6XX_RB_RENDER_CNTL_UNK4                                0x00000010
3113 #define A6XX_RB_RENDER_CNTL_BINNING                             0x00000080
3114 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH                          0x00004000
3115 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK                     0x00ff0000
3116 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT                    16
3117 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
3118 {
3119         return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
3120 }
3121
3122 #define REG_A6XX_RB_RAS_MSAA_CNTL                               0x00008802
3123 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK                     0x00000003
3124 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT                    0
3125 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3126 {
3127         return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3128 }
3129
3130 #define REG_A6XX_RB_DEST_MSAA_CNTL                              0x00008803
3131 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK                    0x00000003
3132 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT                   0
3133 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3134 {
3135         return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
3136 }
3137 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE                     0x00000004
3138
3139 #define REG_A6XX_RB_UNKNOWN_8804                                0x00008804
3140
3141 #define REG_A6XX_RB_UNKNOWN_8805                                0x00008805
3142
3143 #define REG_A6XX_RB_UNKNOWN_8806                                0x00008806
3144
3145 #define REG_A6XX_RB_RENDER_CONTROL0                             0x00008809
3146 #define A6XX_RB_RENDER_CONTROL0_VARYING                         0x00000001
3147 #define A6XX_RB_RENDER_CONTROL0_UNK3                            0x00000008
3148 #define A6XX_RB_RENDER_CONTROL0_XCOORD                          0x00000040
3149 #define A6XX_RB_RENDER_CONTROL0_YCOORD                          0x00000080
3150 #define A6XX_RB_RENDER_CONTROL0_ZCOORD                          0x00000100
3151 #define A6XX_RB_RENDER_CONTROL0_WCOORD                          0x00000200
3152 #define A6XX_RB_RENDER_CONTROL0_UNK10                           0x00000400
3153
3154 #define REG_A6XX_RB_RENDER_CONTROL1                             0x0000880a
3155 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK                      0x00000001
3156 #define A6XX_RB_RENDER_CONTROL1_FACENESS                        0x00000002
3157 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID                        0x00000008
3158
3159 #define REG_A6XX_RB_FS_OUTPUT_CNTL0                             0x0000880b
3160 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z                   0x00000002
3161
3162 #define REG_A6XX_RB_FS_OUTPUT_CNTL1                             0x0000880c
3163 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK                       0x0000000f
3164 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT                      0
3165 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
3166 {
3167         return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
3168 }
3169
3170 #define REG_A6XX_RB_RENDER_COMPONENTS                           0x0000880d
3171 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK                     0x0000000f
3172 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT                    0
3173 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3174 {
3175         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
3176 }
3177 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK                     0x000000f0
3178 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT                    4
3179 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3180 {
3181         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
3182 }
3183 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK                     0x00000f00
3184 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT                    8
3185 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3186 {
3187         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
3188 }
3189 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK                     0x0000f000
3190 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT                    12
3191 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3192 {
3193         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
3194 }
3195 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK                     0x000f0000
3196 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT                    16
3197 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3198 {
3199         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
3200 }
3201 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK                     0x00f00000
3202 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT                    20
3203 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3204 {
3205         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
3206 }
3207 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK                     0x0f000000
3208 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT                    24
3209 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3210 {
3211         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
3212 }
3213 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK                     0xf0000000
3214 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT                    28
3215 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3216 {
3217         return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
3218 }
3219
3220 #define REG_A6XX_RB_DITHER_CNTL                                 0x0000880e
3221 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK              0x00000003
3222 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT             0
3223 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
3224 {
3225         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
3226 }
3227 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK              0x0000000c
3228 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT             2
3229 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
3230 {
3231         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
3232 }
3233 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK              0x00000030
3234 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT             4
3235 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
3236 {
3237         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
3238 }
3239 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK              0x000000c0
3240 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT             6
3241 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
3242 {
3243         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
3244 }
3245 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK              0x00000300
3246 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT             8
3247 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
3248 {
3249         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
3250 }
3251 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK              0x00000c00
3252 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT             10
3253 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
3254 {
3255         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
3256 }
3257 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK              0x00001000
3258 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT             12
3259 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
3260 {
3261         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
3262 }
3263 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK              0x0000c000
3264 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT             14
3265 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
3266 {
3267         return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
3268 }
3269
3270 #define REG_A6XX_RB_SRGB_CNTL                                   0x0000880f
3271 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0                             0x00000001
3272 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1                             0x00000002
3273 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2                             0x00000004
3274 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3                             0x00000008
3275 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4                             0x00000010
3276 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5                             0x00000020
3277 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6                             0x00000040
3278 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7                             0x00000080
3279
3280 #define REG_A6XX_RB_UNKNOWN_8810                                0x00008810
3281
3282 #define REG_A6XX_RB_UNKNOWN_8811                                0x00008811
3283
3284 #define REG_A6XX_RB_UNKNOWN_8818                                0x00008818
3285
3286 #define REG_A6XX_RB_UNKNOWN_8819                                0x00008819
3287
3288 #define REG_A6XX_RB_UNKNOWN_881A                                0x0000881a
3289
3290 #define REG_A6XX_RB_UNKNOWN_881B                                0x0000881b
3291
3292 #define REG_A6XX_RB_UNKNOWN_881C                                0x0000881c
3293
3294 #define REG_A6XX_RB_UNKNOWN_881D                                0x0000881d
3295
3296 #define REG_A6XX_RB_UNKNOWN_881E                                0x0000881e
3297
3298 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3299
3300 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3301 #define A6XX_RB_MRT_CONTROL_BLEND                               0x00000001
3302 #define A6XX_RB_MRT_CONTROL_BLEND2                              0x00000002
3303 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE                          0x00000004
3304 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK                      0x00000078
3305 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT                     3
3306 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3307 {
3308         return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3309 }
3310 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK              0x00000780
3311 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT             7
3312 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3313 {
3314         return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3315 }
3316
3317 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
3318 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK          0x0000001f
3319 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT         0
3320 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3321 {
3322         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3323 }
3324 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK        0x000000e0
3325 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT       5
3326 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3327 {
3328         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3329 }
3330 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK         0x00001f00
3331 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT        8
3332 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3333 {
3334         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3335 }
3336 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK        0x001f0000
3337 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT       16
3338 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3339 {
3340         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3341 }
3342 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK      0x00e00000
3343 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT     21
3344 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3345 {
3346         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3347 }
3348 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK       0x1f000000
3349 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT      24
3350 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3351 {
3352         return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3353 }
3354
3355 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
3356 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK                 0x000000ff
3357 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT                0
3358 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3359 {
3360         return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3361 }
3362 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK              0x00000300
3363 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT             8
3364 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
3365 {
3366         return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3367 }
3368 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK                   0x00006000
3369 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT                  13
3370 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3371 {
3372         return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3373 }
3374
3375 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
3376 #define A6XX_RB_MRT_PITCH__MASK                                 0xffffffff
3377 #define A6XX_RB_MRT_PITCH__SHIFT                                0
3378 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
3379 {
3380         return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
3381 }
3382
3383 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3384 #define A6XX_RB_MRT_ARRAY_PITCH__MASK                           0xffffffff
3385 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT                          0
3386 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3387 {
3388         return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3389 }
3390
3391 static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3392
3393 static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
3394
3395 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
3396
3397 #define REG_A6XX_RB_BLEND_RED_F32                               0x00008860
3398 #define A6XX_RB_BLEND_RED_F32__MASK                             0xffffffff
3399 #define A6XX_RB_BLEND_RED_F32__SHIFT                            0
3400 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
3401 {
3402         return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
3403 }
3404
3405 #define REG_A6XX_RB_BLEND_GREEN_F32                             0x00008861
3406 #define A6XX_RB_BLEND_GREEN_F32__MASK                           0xffffffff
3407 #define A6XX_RB_BLEND_GREEN_F32__SHIFT                          0
3408 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
3409 {
3410         return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
3411 }
3412
3413 #define REG_A6XX_RB_BLEND_BLUE_F32                              0x00008862
3414 #define A6XX_RB_BLEND_BLUE_F32__MASK                            0xffffffff
3415 #define A6XX_RB_BLEND_BLUE_F32__SHIFT                           0
3416 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
3417 {
3418         return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
3419 }
3420
3421 #define REG_A6XX_RB_BLEND_ALPHA_F32                             0x00008863
3422 #define A6XX_RB_BLEND_ALPHA_F32__MASK                           0xffffffff
3423 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT                          0
3424 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
3425 {
3426         return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
3427 }
3428
3429 #define REG_A6XX_RB_ALPHA_CONTROL                               0x00008864
3430 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK                   0x000000ff
3431 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT                  0
3432 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3433 {
3434         return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3435 }
3436 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST                        0x00000100
3437 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK             0x00000e00
3438 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT            9
3439 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3440 {
3441         return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3442 }
3443
3444 #define REG_A6XX_RB_BLEND_CNTL                                  0x00008865
3445 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK                   0x000000ff
3446 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT                  0
3447 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3448 {
3449         return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3450 }
3451 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND                    0x00000100
3452 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK                    0xffff0000
3453 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT                   16
3454 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3455 {
3456         return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3457 }
3458
3459 #define REG_A6XX_RB_DEPTH_PLANE_CNTL                            0x00008870
3460 #define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z                  0x00000001
3461
3462 #define REG_A6XX_RB_DEPTH_CNTL                                  0x00008871
3463 #define A6XX_RB_DEPTH_CNTL_Z_ENABLE                             0x00000001
3464 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE                       0x00000002
3465 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK                          0x0000001c
3466 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT                         2
3467 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3468 {
3469         return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3470 }
3471 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE                        0x00000040
3472
3473 #define REG_A6XX_RB_DEPTH_BUFFER_INFO                           0x00008872
3474 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK            0x00000007
3475 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT           0
3476 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
3477 {
3478         return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3479 }
3480
3481 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH                          0x00008873
3482 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK                        0xffffffff
3483 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT                       0
3484 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3485 {
3486         return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
3487 }
3488
3489 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH                    0x00008874
3490 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK                  0xffffffff
3491 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT                 0
3492 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3493 {
3494         return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3495 }
3496
3497 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO                        0x00008875
3498
3499 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI                        0x00008876
3500
3501 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM                      0x00008877
3502
3503 #define REG_A6XX_RB_UNKNOWN_8878                                0x00008878
3504
3505 #define REG_A6XX_RB_UNKNOWN_8879                                0x00008879
3506
3507 #define REG_A6XX_RB_STENCIL_CONTROL                             0x00008880
3508 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE                  0x00000001
3509 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF               0x00000002
3510 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ                    0x00000004
3511 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK                      0x00000700
3512 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT                     8
3513 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3514 {
3515         return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
3516 }
3517 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK                      0x00003800
3518 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT                     11
3519 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3520 {
3521         return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
3522 }
3523 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK                     0x0001c000
3524 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT                    14
3525 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3526 {
3527         return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3528 }
3529 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK                     0x000e0000
3530 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT                    17
3531 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3532 {
3533         return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3534 }
3535 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK                   0x00700000
3536 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT                  20
3537 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3538 {
3539         return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3540 }
3541 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK                   0x03800000
3542 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT                  23
3543 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3544 {
3545         return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3546 }
3547 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK                  0x1c000000
3548 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT                 26
3549 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3550 {
3551         return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3552 }
3553 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK                  0xe0000000
3554 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT                 29
3555 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3556 {
3557         return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3558 }
3559
3560 #define REG_A6XX_RB_STENCIL_INFO                                0x00008881
3561 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL                   0x00000001
3562
3563 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH                        0x00008882
3564 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK                      0xffffffff
3565 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT                     0
3566 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
3567 {
3568         return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
3569 }
3570
3571 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH                  0x00008883
3572 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK                0xffffffff
3573 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT               0
3574 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
3575 {
3576         return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3577 }
3578
3579 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO                      0x00008884
3580
3581 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI                      0x00008885
3582
3583 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM                    0x00008886
3584
3585 #define REG_A6XX_RB_STENCILREF                                  0x00008887
3586 #define A6XX_RB_STENCILREF_REF__MASK                            0x000000ff
3587 #define A6XX_RB_STENCILREF_REF__SHIFT                           0
3588 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
3589 {
3590         return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
3591 }
3592 #define A6XX_RB_STENCILREF_BFREF__MASK                          0x0000ff00
3593 #define A6XX_RB_STENCILREF_BFREF__SHIFT                         8
3594 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
3595 {
3596         return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
3597 }
3598
3599 #define REG_A6XX_RB_STENCILMASK                                 0x00008888
3600 #define A6XX_RB_STENCILMASK_MASK__MASK                          0x000000ff
3601 #define A6XX_RB_STENCILMASK_MASK__SHIFT                         0
3602 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
3603 {
3604         return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
3605 }
3606 #define A6XX_RB_STENCILMASK_BFMASK__MASK                        0x0000ff00
3607 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT                       8
3608 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
3609 {
3610         return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
3611 }
3612
3613 #define REG_A6XX_RB_STENCILWRMASK                               0x00008889
3614 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK                      0x000000ff
3615 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT                     0
3616 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
3617 {
3618         return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
3619 }
3620 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK                    0x0000ff00
3621 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT                   8
3622 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
3623 {
3624         return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
3625 }
3626
3627 #define REG_A6XX_RB_WINDOW_OFFSET                               0x00008890
3628 #define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE             0x80000000
3629 #define A6XX_RB_WINDOW_OFFSET_X__MASK                           0x00007fff
3630 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT                          0
3631 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
3632 {
3633         return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
3634 }
3635 #define A6XX_RB_WINDOW_OFFSET_Y__MASK                           0x7fff0000
3636 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT                          16
3637 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3638 {
3639         return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
3640 }
3641
3642 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL                        0x00008891
3643 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY                       0x00000002
3644
3645 #define REG_A6XX_RB_UNKNOWN_88D0                                0x000088d0
3646
3647 #define REG_A6XX_RB_BLIT_SCISSOR_TL                             0x000088d1
3648 #define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE           0x80000000
3649 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK                         0x00007fff
3650 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT                        0
3651 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
3652 {
3653         return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
3654 }
3655 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK                         0x7fff0000
3656 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT                        16
3657 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
3658 {
3659         return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
3660 }
3661
3662 #define REG_A6XX_RB_BLIT_SCISSOR_BR                             0x000088d2
3663 #define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE           0x80000000
3664 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK                         0x00007fff
3665 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT                        0
3666 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
3667 {
3668         return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
3669 }
3670 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK                         0x7fff0000
3671 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT                        16
3672 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
3673 {
3674         return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
3675 }
3676
3677 #define REG_A6XX_RB_BLIT_BASE_GMEM                              0x000088d6
3678
3679 #define REG_A6XX_RB_BLIT_DST_INFO                               0x000088d7
3680 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK                   0x00000003
3681 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT                  0
3682 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3683 {
3684         return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
3685 }
3686 #define A6XX_RB_BLIT_DST_INFO_FLAGS                             0x00000004
3687 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK                0x00007f80
3688 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT               7
3689 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3690 {
3691         return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
3692 }
3693 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK                  0x00000060
3694 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT                 5
3695 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3696 {
3697         return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
3698 }
3699
3700 #define REG_A6XX_RB_BLIT_DST_LO                                 0x000088d8
3701
3702 #define REG_A6XX_RB_BLIT_DST_HI                                 0x000088d9
3703
3704 #define REG_A6XX_RB_BLIT_DST_PITCH                              0x000088da
3705 #define A6XX_RB_BLIT_DST_PITCH__MASK                            0xffffffff
3706 #define A6XX_RB_BLIT_DST_PITCH__SHIFT                           0
3707 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
3708 {
3709         return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
3710 }
3711
3712 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH                        0x000088db
3713 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK                      0xffffffff
3714 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT                     0
3715 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3716 {
3717         return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3718 }
3719
3720 #define REG_A6XX_RB_BLIT_FLAG_DST_LO                            0x000088dc
3721
3722 #define REG_A6XX_RB_BLIT_FLAG_DST_HI                            0x000088dd
3723
3724 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0                        0x000088df
3725
3726 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1                        0x000088e0
3727
3728 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2                        0x000088e1
3729
3730 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3                        0x000088e2
3731
3732 #define REG_A6XX_RB_BLIT_INFO                                   0x000088e3
3733 #define A6XX_RB_BLIT_INFO_UNK0                                  0x00000001
3734 #define A6XX_RB_BLIT_INFO_GMEM                                  0x00000002
3735 #define A6XX_RB_BLIT_INFO_INTEGER                               0x00000004
3736 #define A6XX_RB_BLIT_INFO_DEPTH                                 0x00000008
3737 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK                      0x000000f0
3738 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT                     4
3739 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
3740 {
3741         return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
3742 }
3743
3744 #define REG_A6XX_RB_UNKNOWN_88F0                                0x000088f0
3745
3746 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO                   0x00008900
3747
3748 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI                   0x00008901
3749
3750 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH                     0x00008902
3751
3752 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3753
3754 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3755
3756 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
3757
3758 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
3759 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK               0x000007ff
3760 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT              0
3761 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3762 {
3763         return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
3764 }
3765 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK         0x003ff800
3766 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT        11
3767 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3768 {
3769         return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3770 }
3771
3772 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO                        0x00008927
3773
3774 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI                        0x00008928
3775
3776 #define REG_A6XX_RB_2D_BLIT_CNTL                                0x00008c00
3777 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK                 0x0000ff00
3778 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT                8
3779 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
3780 {
3781         return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3782 }
3783
3784 #define REG_A6XX_RB_2D_DST_INFO                                 0x00008c17
3785 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK                  0x000000ff
3786 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT                 0
3787 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3788 {
3789         return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
3790 }
3791 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK                     0x00000300
3792 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT                    8
3793 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3794 {
3795         return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
3796 }
3797 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK                    0x00000c00
3798 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT                   10
3799 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3800 {
3801         return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
3802 }
3803 #define A6XX_RB_2D_DST_INFO_FLAGS                               0x00001000
3804
3805 #define REG_A6XX_RB_2D_DST_LO                                   0x00008c18
3806
3807 #define REG_A6XX_RB_2D_DST_HI                                   0x00008c19
3808
3809 #define REG_A6XX_RB_2D_DST_SIZE                                 0x00008c1a
3810 #define A6XX_RB_2D_DST_SIZE_PITCH__MASK                         0x0000ffff
3811 #define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT                        0
3812 static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
3813 {
3814         return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK;
3815 }
3816
3817 #define REG_A6XX_RB_2D_DST_FLAGS_LO                             0x00008c20
3818
3819 #define REG_A6XX_RB_2D_DST_FLAGS_HI                             0x00008c21
3820
3821 #define REG_A6XX_RB_2D_SRC_SOLID_C0                             0x00008c2c
3822
3823 #define REG_A6XX_RB_2D_SRC_SOLID_C1                             0x00008c2d
3824
3825 #define REG_A6XX_RB_2D_SRC_SOLID_C2                             0x00008c2e
3826
3827 #define REG_A6XX_RB_2D_SRC_SOLID_C3                             0x00008c2f
3828
3829 #define REG_A6XX_RB_UNKNOWN_8E01                                0x00008e01
3830
3831 #define REG_A6XX_RB_UNKNOWN_8E04                                0x00008e04
3832
3833 #define REG_A6XX_RB_CCU_CNTL                                    0x00008e07
3834
3835 #define REG_A6XX_VPC_UNKNOWN_9101                               0x00009101
3836
3837 #define REG_A6XX_VPC_GS_SIV_CNTL                                0x00009104
3838
3839 #define REG_A6XX_VPC_UNKNOWN_9107                               0x00009107
3840
3841 #define REG_A6XX_VPC_UNKNOWN_9108                               0x00009108
3842
3843 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
3844
3845 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
3846
3847 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
3848
3849 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
3850
3851 #define REG_A6XX_VPC_UNKNOWN_9210                               0x00009210
3852
3853 #define REG_A6XX_VPC_UNKNOWN_9211                               0x00009211
3854
3855 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
3856
3857 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
3858
3859 #define REG_A6XX_VPC_SO_CNTL                                    0x00009216
3860 #define A6XX_VPC_SO_CNTL_ENABLE                                 0x00010000
3861
3862 #define REG_A6XX_VPC_SO_PROG                                    0x00009217
3863 #define A6XX_VPC_SO_PROG_A_BUF__MASK                            0x00000003
3864 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT                           0
3865 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
3866 {
3867         return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
3868 }
3869 #define A6XX_VPC_SO_PROG_A_OFF__MASK                            0x000007fc
3870 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT                           2
3871 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
3872 {
3873         return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
3874 }
3875 #define A6XX_VPC_SO_PROG_A_EN                                   0x00000800
3876 #define A6XX_VPC_SO_PROG_B_BUF__MASK                            0x00003000
3877 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT                           12
3878 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
3879 {
3880         return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
3881 }
3882 #define A6XX_VPC_SO_PROG_B_OFF__MASK                            0x007fc000
3883 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT                           14
3884 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
3885 {
3886         return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
3887 }
3888 #define A6XX_VPC_SO_PROG_B_EN                                   0x00800000
3889
3890 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
3891
3892 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
3893
3894 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
3895
3896 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
3897
3898 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
3899
3900 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
3901
3902 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
3903
3904 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
3905
3906 #define REG_A6XX_VPC_UNKNOWN_9236                               0x00009236
3907
3908 #define REG_A6XX_VPC_UNKNOWN_9300                               0x00009300
3909
3910 #define REG_A6XX_VPC_PACK                                       0x00009301
3911 #define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK                       0x000000ff
3912 #define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT                      0
3913 static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val)
3914 {
3915         return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK;
3916 }
3917 #define A6XX_VPC_PACK_NUMNONPOSVAR__MASK                        0x0000ff00
3918 #define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT                       8
3919 static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3920 {
3921         return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK;
3922 }
3923 #define A6XX_VPC_PACK_PSIZELOC__MASK                            0x00ff0000
3924 #define A6XX_VPC_PACK_PSIZELOC__SHIFT                           16
3925 static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val)
3926 {
3927         return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK;
3928 }
3929
3930 #define REG_A6XX_VPC_CNTL_0                                     0x00009304
3931 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK                      0x000000ff
3932 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT                     0
3933 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
3934 {
3935         return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
3936 }
3937 #define A6XX_VPC_CNTL_0_VARYING                                 0x00010000
3938
3939 #define REG_A6XX_VPC_SO_BUF_CNTL                                0x00009305
3940 #define A6XX_VPC_SO_BUF_CNTL_BUF0                               0x00000001
3941 #define A6XX_VPC_SO_BUF_CNTL_BUF1                               0x00000008
3942 #define A6XX_VPC_SO_BUF_CNTL_BUF2                               0x00000040
3943 #define A6XX_VPC_SO_BUF_CNTL_BUF3                               0x00000200
3944 #define A6XX_VPC_SO_BUF_CNTL_ENABLE                             0x00008000
3945
3946 #define REG_A6XX_VPC_SO_OVERRIDE                                0x00009306
3947 #define A6XX_VPC_SO_OVERRIDE_SO_DISABLE                         0x00000001
3948
3949 #define REG_A6XX_VPC_UNKNOWN_9600                               0x00009600
3950
3951 #define REG_A6XX_VPC_UNKNOWN_9602                               0x00009602
3952
3953 #define REG_A6XX_PC_UNKNOWN_9801                                0x00009801
3954
3955 #define REG_A6XX_PC_RESTART_INDEX                               0x00009803
3956
3957 #define REG_A6XX_PC_MODE_CNTL                                   0x00009804
3958
3959 #define REG_A6XX_PC_UNKNOWN_9805                                0x00009805
3960
3961 #define REG_A6XX_PC_UNKNOWN_9806                                0x00009806
3962
3963 #define REG_A6XX_PC_UNKNOWN_9980                                0x00009980
3964
3965 #define REG_A6XX_PC_UNKNOWN_9981                                0x00009981
3966
3967 #define REG_A6XX_PC_UNKNOWN_9990                                0x00009990
3968
3969 #define REG_A6XX_PC_PRIMITIVE_CNTL_0                            0x00009b00
3970 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART              0x00000001
3971 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST             0x00000002
3972
3973 #define REG_A6XX_PC_PRIMITIVE_CNTL_1                            0x00009b01
3974 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK            0x0000007f
3975 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT           0
3976 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
3977 {
3978         return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK;
3979 }
3980 #define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE                          0x00000100
3981
3982 #define REG_A6XX_PC_UNKNOWN_9B06                                0x00009b06
3983
3984 #define REG_A6XX_PC_UNKNOWN_9B07                                0x00009b07
3985
3986 #define REG_A6XX_PC_TESSFACTOR_ADDR_LO                          0x00009e08
3987
3988 #define REG_A6XX_PC_TESSFACTOR_ADDR_HI                          0x00009e09
3989
3990 #define REG_A6XX_PC_UNKNOWN_9E72                                0x00009e72
3991
3992 #define REG_A6XX_VFD_CONTROL_0                                  0x0000a000
3993 #define A6XX_VFD_CONTROL_0_VTXCNT__MASK                         0x0000003f
3994 #define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT                        0
3995 static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
3996 {
3997         return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK;
3998 }
3999
4000 #define REG_A6XX_VFD_CONTROL_1                                  0x0000a001
4001 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK                      0x000000ff
4002 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT                     0
4003 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
4004 {
4005         return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
4006 }
4007 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK                     0x0000ff00
4008 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT                    8
4009 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
4010 {
4011         return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
4012 }
4013 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK                   0x00ff0000
4014 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT                  16
4015 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
4016 {
4017         return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4018 }
4019
4020 #define REG_A6XX_VFD_CONTROL_2                                  0x0000a002
4021 #define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK                  0x000000ff
4022 #define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT                 0
4023 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
4024 {
4025         return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
4026 }
4027
4028 #define REG_A6XX_VFD_CONTROL_3                                  0x0000a003
4029 #define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK                  0x0000ff00
4030 #define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT                 8
4031 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
4032 {
4033         return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
4034 }
4035 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK                    0x00ff0000
4036 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT                   16
4037 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
4038 {
4039         return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
4040 }
4041 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK                    0xff000000
4042 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT                   24
4043 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4044 {
4045         return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
4046 }
4047
4048 #define REG_A6XX_VFD_CONTROL_4                                  0x0000a004
4049
4050 #define REG_A6XX_VFD_CONTROL_5                                  0x0000a005
4051
4052 #define REG_A6XX_VFD_CONTROL_6                                  0x0000a006
4053
4054 #define REG_A6XX_VFD_MODE_CNTL                                  0x0000a007
4055 #define A6XX_VFD_MODE_CNTL_BINNING_PASS                         0x00000001
4056
4057 #define REG_A6XX_VFD_UNKNOWN_A008                               0x0000a008
4058
4059 #define REG_A6XX_VFD_UNKNOWN_A009                               0x0000a009
4060
4061 #define REG_A6XX_VFD_INDEX_OFFSET                               0x0000a00e
4062
4063 #define REG_A6XX_VFD_INSTANCE_START_OFFSET                      0x0000a00f
4064
4065 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4066
4067 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4068
4069 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
4070
4071 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
4072
4073 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
4074
4075 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4076
4077 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4078 #define A6XX_VFD_DECODE_INSTR_IDX__MASK                         0x0000001f
4079 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT                        0
4080 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
4081 {
4082         return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
4083 }
4084 #define A6XX_VFD_DECODE_INSTR_INSTANCED                         0x00020000
4085 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK                      0x0ff00000
4086 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT                     20
4087 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val)
4088 {
4089         return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
4090 }
4091 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK                        0x30000000
4092 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT                       28
4093 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
4094 {
4095         return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
4096 }
4097 #define A6XX_VFD_DECODE_INSTR_UNK30                             0x40000000
4098 #define A6XX_VFD_DECODE_INSTR_FLOAT                             0x80000000
4099
4100 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
4101
4102 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
4103
4104 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
4105 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK                0x0000000f
4106 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT               0
4107 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
4108 {
4109         return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
4110 }
4111 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK                    0x00000ff0
4112 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT                   4
4113 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
4114 {
4115         return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
4116 }
4117
4118 #define REG_A6XX_SP_UNKNOWN_A0F8                                0x0000a0f8
4119
4120 #define REG_A6XX_SP_PRIMITIVE_CNTL                              0x0000a802
4121 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK                      0x0000001f
4122 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT                     0
4123 static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
4124 {
4125         return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
4126 }
4127
4128 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4129
4130 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4131 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK                        0x000000ff
4132 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT                       0
4133 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4134 {
4135         return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
4136 }
4137 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK                     0x00000f00
4138 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT                    8
4139 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
4140 {
4141         return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
4142 }
4143 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK                        0x00ff0000
4144 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT                       16
4145 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
4146 {
4147         return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
4148 }
4149 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK                     0x0f000000
4150 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT                    24
4151 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
4152 {
4153         return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
4154 }
4155
4156 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
4157
4158 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
4159 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK                    0x000000ff
4160 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT                   0
4161 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
4162 {
4163         return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
4164 }
4165 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK                    0x0000ff00
4166 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT                   8
4167 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
4168 {
4169         return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
4170 }
4171 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK                    0x00ff0000
4172 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT                   16
4173 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
4174 {
4175         return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
4176 }
4177 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK                    0xff000000
4178 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT                   24
4179 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
4180 {
4181         return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
4182 }
4183
4184 #define REG_A6XX_SP_VS_CTRL_REG0                                0x0000a800
4185 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4186 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4187 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4188 {
4189         return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4190 }
4191 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4192 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4193 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4194 {
4195         return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4196 }
4197 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4198 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4199 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4200 {
4201         return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4202 }
4203 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4204 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT                  20
4205 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4206 {
4207         return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
4208 }
4209 #define A6XX_SP_VS_CTRL_REG0_VARYING                            0x00400000
4210 #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE                       0x04000000
4211 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS                         0x80000000
4212
4213 #define REG_A6XX_SP_UNKNOWN_A81B                                0x0000a81b
4214
4215 #define REG_A6XX_SP_VS_OBJ_START_LO                             0x0000a81c
4216
4217 #define REG_A6XX_SP_VS_OBJ_START_HI                             0x0000a81d
4218
4219 #define REG_A6XX_SP_VS_TEX_COUNT                                0x0000a822
4220
4221 #define REG_A6XX_SP_VS_CONFIG                                   0x0000a823
4222 #define A6XX_SP_VS_CONFIG_ENABLED                               0x00000100
4223 #define A6XX_SP_VS_CONFIG_NTEX__MASK                            0x0001fe00
4224 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT                           9
4225 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
4226 {
4227         return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
4228 }
4229 #define A6XX_SP_VS_CONFIG_NSAMP__MASK                           0x01fe0000
4230 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT                          17
4231 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
4232 {
4233         return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
4234 }
4235
4236 #define REG_A6XX_SP_VS_INSTRLEN                                 0x0000a824
4237
4238 #define REG_A6XX_SP_HS_CTRL_REG0                                0x0000a830
4239 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4240 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4241 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4242 {
4243         return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4244 }
4245 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4246 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4247 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4248 {
4249         return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4250 }
4251 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4252 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4253 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4254 {
4255         return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
4256 }
4257 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4258 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT                  20
4259 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4260 {
4261         return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
4262 }
4263 #define A6XX_SP_HS_CTRL_REG0_VARYING                            0x00400000
4264 #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE                       0x04000000
4265 #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS                         0x80000000
4266
4267 #define REG_A6XX_SP_HS_UNKNOWN_A831                             0x0000a831
4268
4269 #define REG_A6XX_SP_HS_OBJ_START_LO                             0x0000a834
4270
4271 #define REG_A6XX_SP_HS_OBJ_START_HI                             0x0000a835
4272
4273 #define REG_A6XX_SP_HS_TEX_COUNT                                0x0000a83a
4274
4275 #define REG_A6XX_SP_HS_CONFIG                                   0x0000a83b
4276 #define A6XX_SP_HS_CONFIG_ENABLED                               0x00000100
4277 #define A6XX_SP_HS_CONFIG_NTEX__MASK                            0x0001fe00
4278 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT                           9
4279 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
4280 {
4281         return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
4282 }
4283 #define A6XX_SP_HS_CONFIG_NSAMP__MASK                           0x01fe0000
4284 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT                          17
4285 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
4286 {
4287         return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
4288 }
4289
4290 #define REG_A6XX_SP_HS_INSTRLEN                                 0x0000a83c
4291
4292 #define REG_A6XX_SP_DS_CTRL_REG0                                0x0000a840
4293 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4294 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4295 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4296 {
4297         return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4298 }
4299 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4300 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4301 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4302 {
4303         return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4304 }
4305 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4306 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4307 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4308 {
4309         return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
4310 }
4311 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4312 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT                  20
4313 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4314 {
4315         return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
4316 }
4317 #define A6XX_SP_DS_CTRL_REG0_VARYING                            0x00400000
4318 #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE                       0x04000000
4319 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS                         0x80000000
4320
4321 #define REG_A6XX_SP_DS_OBJ_START_LO                             0x0000a85c
4322
4323 #define REG_A6XX_SP_DS_OBJ_START_HI                             0x0000a85d
4324
4325 #define REG_A6XX_SP_DS_TEX_COUNT                                0x0000a862
4326
4327 #define REG_A6XX_SP_DS_CONFIG                                   0x0000a863
4328 #define A6XX_SP_DS_CONFIG_ENABLED                               0x00000100
4329 #define A6XX_SP_DS_CONFIG_NTEX__MASK                            0x0001fe00
4330 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT                           9
4331 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
4332 {
4333         return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
4334 }
4335 #define A6XX_SP_DS_CONFIG_NSAMP__MASK                           0x01fe0000
4336 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT                          17
4337 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
4338 {
4339         return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
4340 }
4341
4342 #define REG_A6XX_SP_DS_INSTRLEN                                 0x0000a864
4343
4344 #define REG_A6XX_SP_GS_CTRL_REG0                                0x0000a870
4345 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4346 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4347 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4348 {
4349         return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4350 }
4351 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4352 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4353 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4354 {
4355         return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4356 }
4357 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4358 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4359 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4360 {
4361         return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
4362 }
4363 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4364 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT                  20
4365 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4366 {
4367         return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
4368 }
4369 #define A6XX_SP_GS_CTRL_REG0_VARYING                            0x00400000
4370 #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE                       0x04000000
4371 #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS                         0x80000000
4372
4373 #define REG_A6XX_SP_GS_UNKNOWN_A871                             0x0000a871
4374
4375 #define REG_A6XX_SP_GS_OBJ_START_LO                             0x0000a88d
4376
4377 #define REG_A6XX_SP_GS_OBJ_START_HI                             0x0000a88e
4378
4379 #define REG_A6XX_SP_GS_TEX_COUNT                                0x0000a893
4380
4381 #define REG_A6XX_SP_GS_CONFIG                                   0x0000a894
4382 #define A6XX_SP_GS_CONFIG_ENABLED                               0x00000100
4383 #define A6XX_SP_GS_CONFIG_NTEX__MASK                            0x0001fe00
4384 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT                           9
4385 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
4386 {
4387         return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
4388 }
4389 #define A6XX_SP_GS_CONFIG_NSAMP__MASK                           0x01fe0000
4390 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT                          17
4391 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
4392 {
4393         return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
4394 }
4395
4396 #define REG_A6XX_SP_GS_INSTRLEN                                 0x0000a895
4397
4398 #define REG_A6XX_SP_VS_TEX_SAMP_LO                              0x0000a8a0
4399
4400 #define REG_A6XX_SP_VS_TEX_SAMP_HI                              0x0000a8a1
4401
4402 #define REG_A6XX_SP_HS_TEX_SAMP_LO                              0x0000a8a2
4403
4404 #define REG_A6XX_SP_HS_TEX_SAMP_HI                              0x0000a8a3
4405
4406 #define REG_A6XX_SP_DS_TEX_SAMP_LO                              0x0000a8a4
4407
4408 #define REG_A6XX_SP_DS_TEX_SAMP_HI                              0x0000a8a5
4409
4410 #define REG_A6XX_SP_GS_TEX_SAMP_LO                              0x0000a8a6
4411
4412 #define REG_A6XX_SP_GS_TEX_SAMP_HI                              0x0000a8a7
4413
4414 #define REG_A6XX_SP_VS_TEX_CONST_LO                             0x0000a8a8
4415
4416 #define REG_A6XX_SP_VS_TEX_CONST_HI                             0x0000a8a9
4417
4418 #define REG_A6XX_SP_HS_TEX_CONST_LO                             0x0000a8aa
4419
4420 #define REG_A6XX_SP_HS_TEX_CONST_HI                             0x0000a8ab
4421
4422 #define REG_A6XX_SP_DS_TEX_CONST_LO                             0x0000a8ac
4423
4424 #define REG_A6XX_SP_DS_TEX_CONST_HI                             0x0000a8ad
4425
4426 #define REG_A6XX_SP_GS_TEX_CONST_LO                             0x0000a8ae
4427
4428 #define REG_A6XX_SP_GS_TEX_CONST_HI                             0x0000a8af
4429
4430 #define REG_A6XX_SP_FS_CTRL_REG0                                0x0000a980
4431 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4432 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4433 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4434 {
4435         return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4436 }
4437 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4438 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4439 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4440 {
4441         return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4442 }
4443 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4444 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4445 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4446 {
4447         return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4448 }
4449 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4450 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT                  20
4451 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4452 {
4453         return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
4454 }
4455 #define A6XX_SP_FS_CTRL_REG0_VARYING                            0x00400000
4456 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE                       0x04000000
4457 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS                         0x80000000
4458
4459 #define REG_A6XX_SP_UNKNOWN_A982                                0x0000a982
4460
4461 #define REG_A6XX_SP_FS_OBJ_START_LO                             0x0000a983
4462
4463 #define REG_A6XX_SP_FS_OBJ_START_HI                             0x0000a984
4464
4465 #define REG_A6XX_SP_BLEND_CNTL                                  0x0000a989
4466 #define A6XX_SP_BLEND_CNTL_ENABLED                              0x00000001
4467 #define A6XX_SP_BLEND_CNTL_UNK8                                 0x00000100
4468
4469 #define REG_A6XX_SP_SRGB_CNTL                                   0x0000a98a
4470 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0                             0x00000001
4471 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1                             0x00000002
4472 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2                             0x00000004
4473 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3                             0x00000008
4474 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4                             0x00000010
4475 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5                             0x00000020
4476 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6                             0x00000040
4477 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7                             0x00000080
4478
4479 #define REG_A6XX_SP_FS_RENDER_COMPONENTS                        0x0000a98b
4480 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK                  0x0000000f
4481 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT                 0
4482 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
4483 {
4484         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
4485 }
4486 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK                  0x000000f0
4487 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT                 4
4488 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
4489 {
4490         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
4491 }
4492 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK                  0x00000f00
4493 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT                 8
4494 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
4495 {
4496         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
4497 }
4498 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK                  0x0000f000
4499 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT                 12
4500 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
4501 {
4502         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
4503 }
4504 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK                  0x000f0000
4505 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT                 16
4506 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
4507 {
4508         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
4509 }
4510 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK                  0x00f00000
4511 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT                 20
4512 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
4513 {
4514         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
4515 }
4516 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK                  0x0f000000
4517 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT                 24
4518 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
4519 {
4520         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
4521 }
4522 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK                  0xf0000000
4523 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT                 28
4524 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
4525 {
4526         return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
4527 }
4528
4529 #define REG_A6XX_SP_FS_OUTPUT_CNTL0                             0x0000a98c
4530 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK               0x0000ff00
4531 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT              8
4532 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
4533 {
4534         return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
4535 }
4536
4537 #define REG_A6XX_SP_FS_OUTPUT_CNTL1                             0x0000a98d
4538 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK                       0x0000000f
4539 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT                      0
4540 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
4541 {
4542         return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
4543 }
4544
4545 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
4546
4547 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
4548 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK                   0x000000ff
4549 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT                  0
4550 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
4551 {
4552         return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4553 }
4554 #define A6XX_SP_FS_MRT_REG_COLOR_SINT                           0x00000100
4555 #define A6XX_SP_FS_MRT_REG_COLOR_UINT                           0x00000200
4556
4557 #define REG_A6XX_SP_UNKNOWN_A99E                                0x0000a99e
4558
4559 #define REG_A6XX_SP_FS_TEX_COUNT                                0x0000a9a7
4560
4561 #define REG_A6XX_SP_UNKNOWN_A9A8                                0x0000a9a8
4562
4563 #define REG_A6XX_SP_FS_TEX_SAMP_LO                              0x0000a9e0
4564
4565 #define REG_A6XX_SP_FS_TEX_SAMP_HI                              0x0000a9e1
4566
4567 #define REG_A6XX_SP_CS_TEX_SAMP_LO                              0x0000a9e2
4568
4569 #define REG_A6XX_SP_CS_TEX_SAMP_HI                              0x0000a9e3
4570
4571 #define REG_A6XX_SP_FS_TEX_CONST_LO                             0x0000a9e4
4572
4573 #define REG_A6XX_SP_FS_TEX_CONST_HI                             0x0000a9e5
4574
4575 #define REG_A6XX_SP_CS_TEX_CONST_LO                             0x0000a9e6
4576
4577 #define REG_A6XX_SP_CS_TEX_CONST_HI                             0x0000a9e7
4578
4579 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
4580
4581 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
4582 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK                       0x000000ff
4583 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT                      0
4584 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4585 {
4586         return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
4587 }
4588 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION                    0x00000100
4589
4590 #define REG_A6XX_SP_CS_CTRL_REG0                                0x0000a9b0
4591 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x0000007e
4592 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            1
4593 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4594 {
4595         return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4596 }
4597 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x00001f80
4598 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            7
4599 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4600 {
4601         return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4602 }
4603 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK                  0x000fc000
4604 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT                 14
4605 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4606 {
4607         return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4608 }
4609 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
4610 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT                  20
4611 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4612 {
4613         return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4614 }
4615 #define A6XX_SP_CS_CTRL_REG0_VARYING                            0x00400000
4616 #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE                       0x04000000
4617 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS                         0x80000000
4618
4619 #define REG_A6XX_SP_CS_OBJ_START_LO                             0x0000a9b4
4620
4621 #define REG_A6XX_SP_CS_OBJ_START_HI                             0x0000a9b5
4622
4623 #define REG_A6XX_SP_CS_INSTRLEN                                 0x0000a9bc
4624
4625 #define REG_A6XX_SP_UNKNOWN_AB00                                0x0000ab00
4626
4627 #define REG_A6XX_SP_FS_CONFIG                                   0x0000ab04
4628 #define A6XX_SP_FS_CONFIG_ENABLED                               0x00000100
4629 #define A6XX_SP_FS_CONFIG_NTEX__MASK                            0x0001fe00
4630 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT                           9
4631 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
4632 {
4633         return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
4634 }
4635 #define A6XX_SP_FS_CONFIG_NSAMP__MASK                           0x01fe0000
4636 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT                          17
4637 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
4638 {
4639         return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
4640 }
4641
4642 #define REG_A6XX_SP_FS_INSTRLEN                                 0x0000ab05
4643
4644 #define REG_A6XX_SP_UNKNOWN_AB20                                0x0000ab20
4645
4646 #define REG_A6XX_SP_UNKNOWN_AE00                                0x0000ae00
4647
4648 #define REG_A6XX_SP_UNKNOWN_AE03                                0x0000ae03
4649
4650 #define REG_A6XX_SP_UNKNOWN_AE04                                0x0000ae04
4651
4652 #define REG_A6XX_SP_UNKNOWN_AE0F                                0x0000ae0f
4653
4654 #define REG_A6XX_SP_UNKNOWN_B182                                0x0000b182
4655
4656 #define REG_A6XX_SP_UNKNOWN_B183                                0x0000b183
4657
4658 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL                            0x0000b300
4659 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK                  0x00000003
4660 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT                 0
4661 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4662 {
4663         return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4664 }
4665
4666 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL                           0x0000b301
4667 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK                 0x00000003
4668 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT                0
4669 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4670 {
4671         return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4672 }
4673 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE                  0x00000004
4674
4675 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO                0x0000b302
4676
4677 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI                0x0000b303
4678
4679 #define REG_A6XX_SP_TP_UNKNOWN_B304                             0x0000b304
4680
4681 #define REG_A6XX_SP_TP_UNKNOWN_B309                             0x0000b309
4682
4683 #define REG_A6XX_SP_PS_2D_SRC_INFO                              0x0000b4c0
4684 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK               0x000000ff
4685 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT              0
4686 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
4687 {
4688         return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
4689 }
4690 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK                  0x00000300
4691 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT                 8
4692 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
4693 {
4694         return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
4695 }
4696 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK                 0x00000c00
4697 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT                10
4698 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4699 {
4700         return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
4701 }
4702 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS                            0x00001000
4703
4704 #define REG_A6XX_SP_PS_2D_SRC_LO                                0x0000b4c2
4705
4706 #define REG_A6XX_SP_PS_2D_SRC_HI                                0x0000b4c3
4707
4708 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO                          0x0000b4ca
4709
4710 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI                          0x0000b4cb
4711
4712 #define REG_A6XX_SP_UNKNOWN_B600                                0x0000b600
4713
4714 #define REG_A6XX_SP_UNKNOWN_B605                                0x0000b605
4715
4716 #define REG_A6XX_HLSQ_VS_CNTL                                   0x0000b800
4717 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK                        0x000000ff
4718 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT                       0
4719 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
4720 {
4721         return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
4722 }
4723
4724 #define REG_A6XX_HLSQ_HS_CNTL                                   0x0000b801
4725 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK                        0x000000ff
4726 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT                       0
4727 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
4728 {
4729         return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
4730 }
4731
4732 #define REG_A6XX_HLSQ_DS_CNTL                                   0x0000b802
4733 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK                        0x000000ff
4734 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT                       0
4735 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
4736 {
4737         return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
4738 }
4739
4740 #define REG_A6XX_HLSQ_GS_CNTL                                   0x0000b803
4741 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK                        0x000000ff
4742 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT                       0
4743 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
4744 {
4745         return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
4746 }
4747
4748 #define REG_A6XX_HLSQ_UNKNOWN_B980                              0x0000b980
4749
4750 #define REG_A6XX_HLSQ_CONTROL_1_REG                             0x0000b982
4751
4752 #define REG_A6XX_HLSQ_CONTROL_2_REG                             0x0000b983
4753 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK                 0x000000ff
4754 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT                0
4755 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4756 {
4757         return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4758 }
4759 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK                  0x0000ff00
4760 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT                 8
4761 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
4762 {
4763         return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
4764 }
4765 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK                0x00ff0000
4766 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT               16
4767 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
4768 {
4769         return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
4770 }
4771
4772 #define REG_A6XX_HLSQ_CONTROL_3_REG                             0x0000b984
4773 #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK          0x000000ff
4774 #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT         0
4775 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
4776 {
4777         return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
4778 }
4779
4780 #define REG_A6XX_HLSQ_CONTROL_4_REG                             0x0000b985
4781 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK              0x00ff0000
4782 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT             16
4783 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4784 {
4785         return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4786 }
4787 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK              0xff000000
4788 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT             24
4789 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4790 {
4791         return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4792 }
4793
4794 #define REG_A6XX_HLSQ_CONTROL_5_REG                             0x0000b986
4795
4796 #define REG_A6XX_HLSQ_CS_NDRANGE_0                              0x0000b990
4797 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK                  0x00000003
4798 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT                 0
4799 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4800 {
4801         return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4802 }
4803 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK                 0x00000ffc
4804 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT                2
4805 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4806 {
4807         return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4808 }
4809 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK                 0x003ff000
4810 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT                12
4811 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4812 {
4813         return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4814 }
4815 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK                 0xffc00000
4816 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT                22
4817 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4818 {
4819         return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4820 }
4821
4822 #define REG_A6XX_HLSQ_CS_NDRANGE_1                              0x0000b991
4823 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK               0xffffffff
4824 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT              0
4825 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
4826 {
4827         return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
4828 }
4829
4830 #define REG_A6XX_HLSQ_CS_NDRANGE_2                              0x0000b992
4831 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK                0xffffffff
4832 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT               0
4833 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
4834 {
4835         return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
4836 }
4837
4838 #define REG_A6XX_HLSQ_CS_NDRANGE_3                              0x0000b993
4839 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK               0xffffffff
4840 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT              0
4841 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
4842 {
4843         return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
4844 }
4845
4846 #define REG_A6XX_HLSQ_CS_NDRANGE_4                              0x0000b994
4847 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK                0xffffffff
4848 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT               0
4849 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
4850 {
4851         return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
4852 }
4853
4854 #define REG_A6XX_HLSQ_CS_NDRANGE_5                              0x0000b995
4855 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK               0xffffffff
4856 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT              0
4857 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
4858 {
4859         return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
4860 }
4861
4862 #define REG_A6XX_HLSQ_CS_NDRANGE_6                              0x0000b996
4863 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK                0xffffffff
4864 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT               0
4865 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
4866 {
4867         return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
4868 }
4869
4870 #define REG_A6XX_HLSQ_CS_CNTL_0                                 0x0000b997
4871 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK                   0x000000ff
4872 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT                  0
4873 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
4874 {
4875         return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
4876 }
4877 #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK                          0x0000ff00
4878 #define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT                         8
4879 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
4880 {
4881         return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
4882 }
4883 #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK                          0x00ff0000
4884 #define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT                         16
4885 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
4886 {
4887         return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
4888 }
4889 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK                  0xff000000
4890 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT                 24
4891 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
4892 {
4893         return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
4894 }
4895
4896 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X                         0x0000b999
4897
4898 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y                         0x0000b99a
4899
4900 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z                         0x0000b99b
4901
4902 #define REG_A6XX_HLSQ_UPDATE_CNTL                               0x0000bb08
4903
4904 #define REG_A6XX_HLSQ_FS_CNTL                                   0x0000bb10
4905 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK                        0x000000ff
4906 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT                       0
4907 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
4908 {
4909         return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
4910 }
4911
4912 #define REG_A6XX_HLSQ_UNKNOWN_BB11                              0x0000bb11
4913
4914 #define REG_A6XX_HLSQ_UNKNOWN_BE00                              0x0000be00
4915
4916 #define REG_A6XX_HLSQ_UNKNOWN_BE01                              0x0000be01
4917
4918 #define REG_A6XX_HLSQ_UNKNOWN_BE04                              0x0000be04
4919
4920 #define REG_A6XX_TEX_SAMP_0                                     0x00000000
4921 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR                   0x00000001
4922 #define A6XX_TEX_SAMP_0_XY_MAG__MASK                            0x00000006
4923 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT                           1
4924 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
4925 {
4926         return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
4927 }
4928 #define A6XX_TEX_SAMP_0_XY_MIN__MASK                            0x00000018
4929 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT                           3
4930 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
4931 {
4932         return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
4933 }
4934 #define A6XX_TEX_SAMP_0_WRAP_S__MASK                            0x000000e0
4935 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT                           5
4936 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
4937 {
4938         return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
4939 }
4940 #define A6XX_TEX_SAMP_0_WRAP_T__MASK                            0x00000700
4941 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT                           8
4942 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
4943 {
4944         return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
4945 }
4946 #define A6XX_TEX_SAMP_0_WRAP_R__MASK                            0x00003800
4947 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT                           11
4948 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
4949 {
4950         return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
4951 }
4952 #define A6XX_TEX_SAMP_0_ANISO__MASK                             0x0001c000
4953 #define A6XX_TEX_SAMP_0_ANISO__SHIFT                            14
4954 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
4955 {
4956         return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
4957 }
4958 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK                          0xfff80000
4959 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT                         19
4960 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
4961 {
4962         return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
4963 }
4964
4965 #define REG_A6XX_TEX_SAMP_1                                     0x00000001
4966 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK                      0x0000000e
4967 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT                     1
4968 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
4969 {
4970         return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
4971 }
4972 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF                  0x00000010
4973 #define A6XX_TEX_SAMP_1_UNNORM_COORDS                           0x00000020
4974 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR                    0x00000040
4975 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK                           0x000fff00
4976 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT                          8
4977 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
4978 {
4979         return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
4980 }
4981 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK                           0xfff00000
4982 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT                          20
4983 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
4984 {
4985         return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
4986 }
4987
4988 #define REG_A6XX_TEX_SAMP_2                                     0x00000002
4989 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK                     0xfffffff0
4990 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT                    4
4991 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
4992 {
4993         return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
4994 }
4995
4996 #define REG_A6XX_TEX_SAMP_3                                     0x00000003
4997
4998 #define REG_A6XX_TEX_CONST_0                                    0x00000000
4999 #define A6XX_TEX_CONST_0_TILE_MODE__MASK                        0x00000003
5000 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT                       0
5001 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
5002 {
5003         return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
5004 }
5005 #define A6XX_TEX_CONST_0_SRGB                                   0x00000004
5006 #define A6XX_TEX_CONST_0_SWIZ_X__MASK                           0x00000070
5007 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT                          4
5008 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
5009 {
5010         return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
5011 }
5012 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK                           0x00000380
5013 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT                          7
5014 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
5015 {
5016         return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
5017 }
5018 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK                           0x00001c00
5019 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT                          10
5020 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
5021 {
5022         return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
5023 }
5024 #define A6XX_TEX_CONST_0_SWIZ_W__MASK                           0x0000e000
5025 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT                          13
5026 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
5027 {
5028         return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
5029 }
5030 #define A6XX_TEX_CONST_0_MIPLVLS__MASK                          0x000f0000
5031 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT                         16
5032 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
5033 {
5034         return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
5035 }
5036 #define A6XX_TEX_CONST_0_FMT__MASK                              0x3fc00000
5037 #define A6XX_TEX_CONST_0_FMT__SHIFT                             22
5038 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val)
5039 {
5040         return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
5041 }
5042 #define A6XX_TEX_CONST_0_SWAP__MASK                             0xc0000000
5043 #define A6XX_TEX_CONST_0_SWAP__SHIFT                            30
5044 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
5045 {
5046         return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
5047 }
5048
5049 #define REG_A6XX_TEX_CONST_1                                    0x00000001
5050 #define A6XX_TEX_CONST_1_WIDTH__MASK                            0x00007fff
5051 #define A6XX_TEX_CONST_1_WIDTH__SHIFT                           0
5052 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
5053 {
5054         return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
5055 }
5056 #define A6XX_TEX_CONST_1_HEIGHT__MASK                           0x3fff8000
5057 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT                          15
5058 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
5059 {
5060         return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
5061 }
5062
5063 #define REG_A6XX_TEX_CONST_2                                    0x00000002
5064 #define A6XX_TEX_CONST_2_FETCHSIZE__MASK                        0x0000000f
5065 #define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT                       0
5066 static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val)
5067 {
5068         return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK;
5069 }
5070 #define A6XX_TEX_CONST_2_PITCH__MASK                            0x1fffff80
5071 #define A6XX_TEX_CONST_2_PITCH__SHIFT                           7
5072 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
5073 {
5074         return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
5075 }
5076 #define A6XX_TEX_CONST_2_TYPE__MASK                             0x60000000
5077 #define A6XX_TEX_CONST_2_TYPE__SHIFT                            29
5078 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
5079 {
5080         return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
5081 }
5082
5083 #define REG_A6XX_TEX_CONST_3                                    0x00000003
5084 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK                      0x00003fff
5085 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT                     0
5086 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5087 {
5088         return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5089 }
5090 #define A6XX_TEX_CONST_3_FLAG                                   0x10000000
5091
5092 #define REG_A6XX_TEX_CONST_4                                    0x00000004
5093 #define A6XX_TEX_CONST_4_BASE_LO__MASK                          0xffffffe0
5094 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT                         5
5095 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
5096 {
5097         return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
5098 }
5099
5100 #define REG_A6XX_TEX_CONST_5                                    0x00000005
5101 #define A6XX_TEX_CONST_5_BASE_HI__MASK                          0x0001ffff
5102 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT                         0
5103 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
5104 {
5105         return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
5106 }
5107 #define A6XX_TEX_CONST_5_DEPTH__MASK                            0x3ffe0000
5108 #define A6XX_TEX_CONST_5_DEPTH__SHIFT                           17
5109 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
5110 {
5111         return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
5112 }
5113
5114 #define REG_A6XX_TEX_CONST_6                                    0x00000006
5115
5116 #define REG_A6XX_TEX_CONST_7                                    0x00000007
5117 #define A6XX_TEX_CONST_7_FLAG_LO__MASK                          0xffffffe0
5118 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT                         5
5119 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
5120 {
5121         return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
5122 }
5123
5124 #define REG_A6XX_TEX_CONST_8                                    0x00000008
5125 #define A6XX_TEX_CONST_8_FLAG_HI__MASK                          0x0001ffff
5126 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT                         0
5127 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
5128 {
5129         return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
5130 }
5131
5132 #define REG_A6XX_TEX_CONST_9                                    0x00000009
5133
5134 #define REG_A6XX_TEX_CONST_10                                   0x0000000a
5135
5136 #define REG_A6XX_TEX_CONST_11                                   0x0000000b
5137
5138 #define REG_A6XX_TEX_CONST_12                                   0x0000000c
5139
5140 #define REG_A6XX_TEX_CONST_13                                   0x0000000d
5141
5142 #define REG_A6XX_TEX_CONST_14                                   0x0000000e
5143
5144 #define REG_A6XX_TEX_CONST_15                                   0x0000000f
5145
5146 #define REG_A6XX_PDC_GPU_ENABLE_PDC                             0x00001140
5147
5148 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR                         0x00001148
5149
5150 #define REG_A6XX_PDC_GPU_TCS0_CONTROL                           0x00001540
5151
5152 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK                   0x00001541
5153
5154 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK            0x00001542
5155
5156 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID                        0x00001543
5157
5158 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR                         0x00001544
5159
5160 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA                         0x00001545
5161
5162 #define REG_A6XX_PDC_GPU_TCS1_CONTROL                           0x00001572
5163
5164 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK                   0x00001573
5165
5166 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK            0x00001574
5167
5168 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID                        0x00001575
5169
5170 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR                         0x00001576
5171
5172 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA                         0x00001577
5173
5174 #define REG_A6XX_PDC_GPU_TCS2_CONTROL                           0x000015a4
5175
5176 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK                   0x000015a5
5177
5178 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK            0x000015a6
5179
5180 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID                        0x000015a7
5181
5182 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR                         0x000015a8
5183
5184 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA                         0x000015a9
5185
5186 #define REG_A6XX_PDC_GPU_TCS3_CONTROL                           0x000015d6
5187
5188 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK                   0x000015d7
5189
5190 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK            0x000015d8
5191
5192 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID                        0x000015d9
5193
5194 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR                         0x000015da
5195
5196 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA                         0x000015db
5197
5198 #define REG_A6XX_PDC_GPU_SEQ_MEM_0                              0x00000000
5199
5200 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A                       0x00000000
5201 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK          0x000000ff
5202 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT         0
5203 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
5204 {
5205         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
5206 }
5207 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK        0x0000ff00
5208 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT       8
5209 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
5210 {
5211         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
5212 }
5213
5214 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B                       0x00000001
5215
5216 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C                       0x00000002
5217
5218 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D                       0x00000003
5219
5220 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT                       0x00000004
5221 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK             0x0000003f
5222 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT            0
5223 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
5224 {
5225         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
5226 }
5227 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK               0x00007000
5228 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT              12
5229 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
5230 {
5231         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
5232 }
5233 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK                0xf0000000
5234 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT               28
5235 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
5236 {
5237         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
5238 }
5239
5240 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM                       0x00000005
5241 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK              0x0f000000
5242 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT             24
5243 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
5244 {
5245         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
5246 }
5247
5248 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0                      0x00000008
5249
5250 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1                      0x00000009
5251
5252 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2                      0x0000000a
5253
5254 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3                      0x0000000b
5255
5256 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0                     0x0000000c
5257
5258 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1                     0x0000000d
5259
5260 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2                     0x0000000e
5261
5262 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3                     0x0000000f
5263
5264 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0                     0x00000010
5265 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK            0x0000000f
5266 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT           0
5267 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
5268 {
5269         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
5270 }
5271 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK            0x000000f0
5272 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT           4
5273 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
5274 {
5275         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
5276 }
5277 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK            0x00000f00
5278 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT           8
5279 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
5280 {
5281         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
5282 }
5283 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK            0x0000f000
5284 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT           12
5285 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
5286 {
5287         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
5288 }
5289 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK            0x000f0000
5290 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT           16
5291 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
5292 {
5293         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
5294 }
5295 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK            0x00f00000
5296 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT           20
5297 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
5298 {
5299         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
5300 }
5301 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK            0x0f000000
5302 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT           24
5303 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
5304 {
5305         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
5306 }
5307 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK            0xf0000000
5308 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT           28
5309 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
5310 {
5311         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
5312 }
5313
5314 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1                     0x00000011
5315 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK            0x0000000f
5316 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT           0
5317 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
5318 {
5319         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
5320 }
5321 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK            0x000000f0
5322 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT           4
5323 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
5324 {
5325         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
5326 }
5327 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK           0x00000f00
5328 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT          8
5329 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
5330 {
5331         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
5332 }
5333 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK           0x0000f000
5334 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT          12
5335 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
5336 {
5337         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
5338 }
5339 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK           0x000f0000
5340 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT          16
5341 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
5342 {
5343         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
5344 }
5345 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK           0x00f00000
5346 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT          20
5347 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
5348 {
5349         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
5350 }
5351 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK           0x0f000000
5352 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT          24
5353 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
5354 {
5355         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
5356 }
5357 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK           0xf0000000
5358 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT          28
5359 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
5360 {
5361         return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
5362 }
5363
5364 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1                  0x0000002f
5365
5366 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2                  0x00000030
5367
5368
5369 #endif /* A6XX_XML */