4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
23 Copyright (C) 2013-2018 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
55 RB6_R4G4B4A4_UNORM = 8,
56 RB6_R5G5B5A1_UNORM = 10,
57 RB6_R5G6B5_UNORM = 14,
67 RB6_R8G8B8A8_UNORM = 48,
68 RB6_R8G8B8_UNORM = 49,
69 RB6_R8G8B8A8_SNORM = 50,
70 RB6_R8G8B8A8_UINT = 51,
71 RB6_R8G8B8A8_SINT = 52,
72 RB6_R10G10B10A2_UNORM = 55,
73 RB6_R10G10B10A2_UINT = 58,
74 RB6_R11G11B10_FLOAT = 66,
75 RB6_R16G16_UNORM = 67,
76 RB6_R16G16_SNORM = 68,
77 RB6_R16G16_FLOAT = 69,
83 RB6_R16G16B16A16_UNORM = 96,
84 RB6_R16G16B16A16_SNORM = 97,
85 RB6_R16G16B16A16_FLOAT = 98,
86 RB6_R16G16B16A16_UINT = 99,
87 RB6_R16G16B16A16_SINT = 100,
88 RB6_R32G32_FLOAT = 103,
89 RB6_R32G32_UINT = 104,
90 RB6_R32G32_SINT = 105,
91 RB6_R32G32B32A32_FLOAT = 130,
92 RB6_R32G32B32A32_UINT = 131,
93 RB6_R32G32B32A32_SINT = 132,
94 RB6_X8Z24_UNORM = 160,
108 VFMT6_8_8_UNORM = 15,
109 VFMT6_8_8_SNORM = 16,
117 VFMT6_8_8_8_UNORM = 33,
118 VFMT6_8_8_8_SNORM = 34,
119 VFMT6_8_8_8_UINT = 35,
120 VFMT6_8_8_8_SINT = 36,
121 VFMT6_8_8_8_8_UNORM = 48,
122 VFMT6_8_8_8_8_SNORM = 50,
123 VFMT6_8_8_8_8_UINT = 51,
124 VFMT6_8_8_8_8_SINT = 52,
125 VFMT6_10_10_10_2_UNORM = 54,
126 VFMT6_10_10_10_2_SNORM = 57,
127 VFMT6_10_10_10_2_UINT = 58,
128 VFMT6_10_10_10_2_SINT = 59,
129 VFMT6_11_11_10_FLOAT = 66,
130 VFMT6_16_16_UNORM = 67,
131 VFMT6_16_16_SNORM = 68,
132 VFMT6_16_16_FLOAT = 69,
133 VFMT6_16_16_UINT = 70,
134 VFMT6_16_16_SINT = 71,
141 VFMT6_16_16_16_UNORM = 88,
142 VFMT6_16_16_16_SNORM = 89,
143 VFMT6_16_16_16_FLOAT = 90,
144 VFMT6_16_16_16_UINT = 91,
145 VFMT6_16_16_16_SINT = 92,
146 VFMT6_16_16_16_16_UNORM = 96,
147 VFMT6_16_16_16_16_SNORM = 97,
148 VFMT6_16_16_16_16_FLOAT = 98,
149 VFMT6_16_16_16_16_UINT = 99,
150 VFMT6_16_16_16_16_SINT = 100,
151 VFMT6_32_32_UNORM = 101,
152 VFMT6_32_32_SNORM = 102,
153 VFMT6_32_32_FLOAT = 103,
154 VFMT6_32_32_UINT = 104,
155 VFMT6_32_32_SINT = 105,
156 VFMT6_32_32_FIXED = 106,
157 VFMT6_32_32_32_UNORM = 112,
158 VFMT6_32_32_32_SNORM = 113,
159 VFMT6_32_32_32_UINT = 114,
160 VFMT6_32_32_32_SINT = 115,
161 VFMT6_32_32_32_FLOAT = 116,
162 VFMT6_32_32_32_FIXED = 117,
163 VFMT6_32_32_32_32_UNORM = 128,
164 VFMT6_32_32_32_32_SNORM = 129,
165 VFMT6_32_32_32_32_FLOAT = 130,
166 VFMT6_32_32_32_32_UINT = 131,
167 VFMT6_32_32_32_32_SINT = 132,
168 VFMT6_32_32_32_32_FIXED = 133,
177 TFMT6_4_4_4_4_UNORM = 8,
178 TFMT6_5_5_5_1_UNORM = 10,
179 TFMT6_5_6_5_UNORM = 14,
180 TFMT6_8_8_UNORM = 15,
181 TFMT6_8_8_SNORM = 16,
184 TFMT6_L8_A8_UNORM = 19,
190 TFMT6_8_8_8_8_UNORM = 48,
191 TFMT6_8_8_8_UNORM = 49,
192 TFMT6_8_8_8_8_SNORM = 50,
193 TFMT6_8_8_8_8_UINT = 51,
194 TFMT6_8_8_8_8_SINT = 52,
195 TFMT6_9_9_9_E5_FLOAT = 53,
196 TFMT6_10_10_10_2_UNORM = 54,
197 TFMT6_10_10_10_2_UINT = 58,
198 TFMT6_11_11_10_FLOAT = 66,
199 TFMT6_16_16_UNORM = 67,
200 TFMT6_16_16_SNORM = 68,
201 TFMT6_16_16_FLOAT = 69,
202 TFMT6_16_16_UINT = 70,
203 TFMT6_16_16_SINT = 71,
207 TFMT6_16_16_16_16_UNORM = 96,
208 TFMT6_16_16_16_16_SNORM = 97,
209 TFMT6_16_16_16_16_FLOAT = 98,
210 TFMT6_16_16_16_16_UINT = 99,
211 TFMT6_16_16_16_16_SINT = 100,
212 TFMT6_32_32_FLOAT = 103,
213 TFMT6_32_32_UINT = 104,
214 TFMT6_32_32_SINT = 105,
215 TFMT6_32_32_32_UINT = 114,
216 TFMT6_32_32_32_SINT = 115,
217 TFMT6_32_32_32_FLOAT = 116,
218 TFMT6_32_32_32_32_FLOAT = 130,
219 TFMT6_32_32_32_32_UINT = 131,
220 TFMT6_32_32_32_32_SINT = 132,
221 TFMT6_X8Z24_UNORM = 160,
222 TFMT6_ETC2_RG11_UNORM = 171,
223 TFMT6_ETC2_RG11_SNORM = 172,
224 TFMT6_ETC2_R11_UNORM = 173,
225 TFMT6_ETC2_R11_SNORM = 174,
227 TFMT6_ETC2_RGB8 = 176,
228 TFMT6_ETC2_RGBA8 = 177,
229 TFMT6_ETC2_RGB8A1 = 178,
233 TFMT6_RGTC1_UNORM = 183,
234 TFMT6_RGTC1_SNORM = 184,
235 TFMT6_RGTC2_UNORM = 187,
236 TFMT6_RGTC2_SNORM = 188,
237 TFMT6_BPTC_UFLOAT = 190,
238 TFMT6_BPTC_FLOAT = 191,
240 TFMT6_ASTC_4x4 = 193,
241 TFMT6_ASTC_5x4 = 194,
242 TFMT6_ASTC_5x5 = 195,
243 TFMT6_ASTC_6x5 = 196,
244 TFMT6_ASTC_6x6 = 197,
245 TFMT6_ASTC_8x5 = 198,
246 TFMT6_ASTC_8x6 = 199,
247 TFMT6_ASTC_8x8 = 200,
248 TFMT6_ASTC_10x5 = 201,
249 TFMT6_ASTC_10x6 = 202,
250 TFMT6_ASTC_10x8 = 203,
251 TFMT6_ASTC_10x10 = 204,
252 TFMT6_ASTC_12x10 = 205,
253 TFMT6_ASTC_12x12 = 206,
256 enum a6xx_tex_fetchsize {
264 enum a6xx_depth_format {
271 enum a6xx_cp_perfcounter_select {
272 PERF_CP_ALWAYS_COUNT = 0,
275 enum a6xx_tex_filter {
276 A6XX_TEX_NEAREST = 0,
281 enum a6xx_tex_clamp {
283 A6XX_TEX_CLAMP_TO_EDGE = 1,
284 A6XX_TEX_MIRROR_REPEAT = 2,
285 A6XX_TEX_CLAMP_TO_BORDER = 3,
286 A6XX_TEX_MIRROR_CLAMP = 4,
289 enum a6xx_tex_aniso {
290 A6XX_TEX_ANISO_1 = 0,
291 A6XX_TEX_ANISO_2 = 1,
292 A6XX_TEX_ANISO_4 = 2,
293 A6XX_TEX_ANISO_8 = 3,
294 A6XX_TEX_ANISO_16 = 4,
313 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
314 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002
315 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040
316 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
317 #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100
318 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
319 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
320 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
321 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
322 #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
323 #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
324 #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000
325 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
326 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
327 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
328 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
329 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000
330 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
331 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
332 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
333 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
334 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
335 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
336 #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
337 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
338 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
339 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
340 #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020
341 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040
342 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080
343 #define REG_A6XX_CP_RB_BASE 0x00000800
345 #define REG_A6XX_CP_RB_BASE_HI 0x00000801
347 #define REG_A6XX_CP_RB_CNTL 0x00000802
349 #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804
351 #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805
353 #define REG_A6XX_CP_RB_RPTR 0x00000806
355 #define REG_A6XX_CP_RB_WPTR 0x00000807
357 #define REG_A6XX_CP_SQE_CNTL 0x00000808
359 #define REG_A6XX_CP_HW_FAULT 0x00000821
361 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
363 #define REG_A6XX_CP_PROTECT_STATUS 0x00000824
365 #define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830
367 #define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831
369 #define REG_A6XX_CP_MISC_CNTL 0x00000840
371 #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
373 #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
375 #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
377 #define REG_A6XX_CP_CHICKEN_DBG 0x00000841
379 #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842
381 #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
383 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
385 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
387 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
389 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
391 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
392 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
393 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
394 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
396 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
398 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000
399 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18
400 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
402 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
404 #define A6XX_CP_PROTECT_REG_READ 0x80000000
406 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0
408 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1
410 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2
412 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3
414 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4
416 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5
418 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6
420 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
422 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
424 #define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0
426 #define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1
428 #define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2
430 #define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3
432 #define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4
434 #define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5
436 #define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6
438 #define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7
440 #define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8
442 #define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9
444 #define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da
446 #define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db
448 #define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc
450 #define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd
452 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
454 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901
456 #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
458 #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
460 #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908
462 #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909
464 #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a
466 #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b
468 #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c
470 #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d
472 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e
474 #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f
476 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910
478 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911
480 #define REG_A6XX_CP_IB1_BASE 0x00000928
482 #define REG_A6XX_CP_IB1_BASE_HI 0x00000929
484 #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a
486 #define REG_A6XX_CP_IB2_BASE 0x0000092b
488 #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c
490 #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
492 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
494 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
496 #define REG_A6XX_CP_AHB_CNTL 0x0000098d
498 #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
500 #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
502 #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
504 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
506 #define REG_A6XX_RBBM_STATUS 0x00000210
507 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
508 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
509 #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000
510 #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000
511 #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000
512 #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000
513 #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000
514 #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000
515 #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000
516 #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000
517 #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000
518 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000
519 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800
520 #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400
521 #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200
522 #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100
523 #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080
524 #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040
525 #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020
526 #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010
527 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008
528 #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004
529 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
530 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
532 #define REG_A6XX_RBBM_STATUS3 0x00000213
534 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
536 #define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400
538 #define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401
540 #define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402
542 #define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403
544 #define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404
546 #define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405
548 #define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406
550 #define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407
552 #define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408
554 #define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409
556 #define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a
558 #define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b
560 #define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c
562 #define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d
564 #define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e
566 #define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f
568 #define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410
570 #define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411
572 #define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412
574 #define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413
576 #define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414
578 #define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415
580 #define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416
582 #define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417
584 #define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418
586 #define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419
588 #define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a
590 #define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b
592 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c
594 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d
596 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e
598 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f
600 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420
602 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421
604 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422
606 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423
608 #define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424
610 #define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425
612 #define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426
614 #define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427
616 #define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428
618 #define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429
620 #define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a
622 #define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b
624 #define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c
626 #define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d
628 #define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e
630 #define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f
632 #define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430
634 #define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431
636 #define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432
638 #define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433
640 #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434
642 #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435
644 #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436
646 #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437
648 #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438
650 #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439
652 #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a
654 #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b
656 #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c
658 #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d
660 #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e
662 #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f
664 #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440
666 #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441
668 #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442
670 #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443
672 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444
674 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445
676 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446
678 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447
680 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448
682 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449
684 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a
686 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b
688 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c
690 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d
692 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e
694 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f
696 #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450
698 #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451
700 #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452
702 #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453
704 #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454
706 #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455
708 #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456
710 #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457
712 #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458
714 #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459
716 #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a
718 #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b
720 #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c
722 #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d
724 #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e
726 #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f
728 #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460
730 #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461
732 #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462
734 #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463
736 #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464
738 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
740 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
742 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
744 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
746 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
748 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
750 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
752 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
754 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
756 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
758 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
760 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
762 #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
764 #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
766 #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d
768 #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e
770 #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f
772 #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470
774 #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471
776 #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472
778 #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473
780 #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474
782 #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475
784 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476
786 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477
788 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478
790 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479
792 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a
794 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b
796 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c
798 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d
800 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e
802 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f
804 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480
806 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481
808 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482
810 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483
812 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484
814 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485
816 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486
818 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487
820 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488
822 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489
824 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a
826 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b
828 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c
830 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d
832 #define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e
834 #define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f
836 #define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490
838 #define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491
840 #define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492
842 #define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493
844 #define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494
846 #define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495
848 #define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496
850 #define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497
852 #define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498
854 #define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499
856 #define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a
858 #define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b
860 #define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c
862 #define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d
864 #define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e
866 #define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f
868 #define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0
870 #define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1
872 #define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2
874 #define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3
876 #define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4
878 #define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5
880 #define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6
882 #define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7
884 #define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8
886 #define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9
888 #define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa
890 #define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab
892 #define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac
894 #define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad
896 #define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae
898 #define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af
900 #define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0
902 #define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1
904 #define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2
906 #define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3
908 #define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4
910 #define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5
912 #define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6
914 #define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7
916 #define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8
918 #define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9
920 #define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba
922 #define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb
924 #define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc
926 #define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd
928 #define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be
930 #define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf
932 #define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0
934 #define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1
936 #define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2
938 #define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3
940 #define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4
942 #define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5
944 #define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6
946 #define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7
948 #define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8
950 #define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9
952 #define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca
954 #define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb
956 #define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc
958 #define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd
960 #define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce
962 #define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf
964 #define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0
966 #define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1
968 #define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2
970 #define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3
972 #define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4
974 #define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5
976 #define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6
978 #define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7
980 #define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8
982 #define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9
984 #define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da
986 #define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db
988 #define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc
990 #define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd
992 #define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de
994 #define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df
996 #define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0
998 #define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1
1000 #define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2
1002 #define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3
1004 #define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4
1006 #define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5
1008 #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6
1010 #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7
1012 #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8
1014 #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9
1016 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea
1018 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb
1020 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec
1022 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed
1024 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee
1026 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef
1028 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0
1030 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1
1032 #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2
1034 #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3
1036 #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4
1038 #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5
1040 #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6
1042 #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7
1044 #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8
1046 #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9
1048 #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1050 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
1052 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
1054 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
1056 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
1058 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
1060 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1062 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507
1064 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508
1066 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509
1068 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a
1070 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1072 #define REG_A6XX_RBBM_ISDB_CNT 0x00000533
1074 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1076 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1078 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1080 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1082 #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1084 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1086 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
1088 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
1090 #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
1092 #define REG_A6XX_RBBM_INT_0_MASK 0x00000038
1094 #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
1096 #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043
1098 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044
1100 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1102 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1104 #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
1106 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
1108 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1
1110 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2
1112 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3
1114 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4
1116 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5
1118 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6
1120 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7
1122 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8
1124 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9
1126 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba
1128 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb
1130 #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc
1132 #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd
1134 #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be
1136 #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf
1138 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0
1140 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1
1142 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2
1144 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3
1146 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4
1148 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5
1150 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6
1152 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7
1154 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8
1156 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9
1158 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca
1160 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb
1162 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc
1164 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd
1166 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce
1168 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf
1170 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0
1172 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1
1174 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2
1176 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3
1178 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4
1180 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5
1182 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6
1184 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7
1186 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8
1188 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9
1190 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da
1192 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db
1194 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc
1196 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd
1198 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de
1200 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df
1202 #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0
1204 #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1
1206 #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2
1208 #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3
1210 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4
1212 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5
1214 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6
1216 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7
1218 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8
1220 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9
1222 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea
1224 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb
1226 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec
1228 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed
1230 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee
1232 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef
1234 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0
1236 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1
1238 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2
1240 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3
1242 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4
1244 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5
1246 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6
1248 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7
1250 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8
1252 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9
1254 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa
1256 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb
1258 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100
1260 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101
1262 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102
1264 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103
1266 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104
1268 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105
1270 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106
1272 #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107
1274 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108
1276 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109
1278 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a
1280 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b
1282 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c
1284 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d
1286 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e
1288 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f
1290 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110
1292 #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111
1294 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112
1296 #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113
1298 #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114
1300 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115
1302 #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116
1304 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117
1306 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118
1308 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119
1310 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a
1312 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b
1314 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
1316 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
1318 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
1320 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602
1322 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603
1323 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
1324 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
1325 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
1327 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
1329 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
1330 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
1331 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
1333 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
1336 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604
1337 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
1338 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
1339 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
1341 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
1343 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
1344 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
1345 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
1347 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
1349 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
1350 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
1351 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
1353 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
1356 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605
1357 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
1358 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
1359 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
1361 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
1364 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608
1366 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609
1368 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a
1370 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b
1372 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c
1374 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d
1376 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e
1378 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f
1380 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610
1381 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
1382 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
1383 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
1385 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
1387 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
1388 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
1389 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
1391 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
1393 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
1394 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
1395 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
1397 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
1399 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
1400 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
1401 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
1403 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
1405 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
1406 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
1407 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
1409 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
1411 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
1412 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
1413 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
1415 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
1417 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
1418 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
1419 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
1421 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
1423 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
1424 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
1425 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
1427 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
1430 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611
1431 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
1432 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
1433 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
1435 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
1437 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
1438 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
1439 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
1441 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
1443 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
1444 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
1445 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
1447 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
1449 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
1450 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
1451 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
1453 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
1455 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
1456 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
1457 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
1459 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
1461 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
1462 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
1463 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
1465 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
1467 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
1468 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
1469 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
1471 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
1473 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
1474 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
1475 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
1477 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
1480 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
1482 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
1484 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8
1486 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9
1488 #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
1490 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610
1492 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611
1494 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612
1496 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613
1498 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614
1500 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615
1502 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616
1504 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617
1506 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618
1508 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619
1510 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a
1512 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b
1514 #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
1516 #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08
1518 #define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10
1520 #define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11
1522 #define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12
1524 #define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13
1526 #define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14
1528 #define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15
1530 #define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16
1532 #define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17
1534 #define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18
1536 #define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19
1538 #define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a
1540 #define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b
1542 #define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c
1544 #define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c
1546 #define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d
1548 #define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e
1550 #define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f
1552 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
1554 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
1556 #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
1558 #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
1560 #define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34
1562 #define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35
1564 #define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36
1566 #define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37
1568 #define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38
1570 #define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39
1572 #define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a
1574 #define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b
1576 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
1578 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10
1580 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11
1582 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12
1584 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13
1586 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14
1588 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15
1590 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
1592 #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
1594 #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
1596 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610
1598 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611
1600 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612
1602 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613
1604 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614
1606 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615
1608 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616
1610 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617
1612 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
1614 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604
1616 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605
1618 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606
1620 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607
1622 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608
1624 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609
1626 #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
1628 #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
1630 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
1632 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
1634 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
1636 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
1638 #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
1640 #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
1642 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
1644 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
1646 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
1648 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
1650 #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
1652 #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
1654 #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
1655 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
1656 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
1657 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
1659 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
1662 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c
1664 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d
1666 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e
1668 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f
1670 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20
1672 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21
1674 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22
1676 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23
1678 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24
1680 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25
1682 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26
1684 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27
1686 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
1688 #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
1690 #define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10
1692 #define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11
1694 #define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12
1696 #define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13
1698 #define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14
1700 #define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15
1702 #define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16
1704 #define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17
1706 #define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18
1708 #define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19
1710 #define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a
1712 #define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b
1714 #define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c
1716 #define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d
1718 #define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e
1720 #define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f
1722 #define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20
1724 #define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21
1726 #define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22
1728 #define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23
1730 #define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24
1732 #define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25
1734 #define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26
1736 #define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27
1738 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
1740 #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
1742 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610
1744 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611
1746 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612
1748 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613
1750 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614
1752 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615
1754 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616
1756 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617
1758 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618
1760 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619
1762 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a
1764 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b
1766 #define REG_A6XX_VBIF_VERSION 0x00003000
1768 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1770 #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
1772 #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
1774 #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
1776 #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
1778 #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2
1780 #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3
1782 #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8
1784 #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9
1786 #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da
1788 #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db
1790 #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0
1792 #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1
1794 #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2
1796 #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3
1798 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
1800 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
1802 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
1804 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
1806 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
1808 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
1810 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
1812 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
1814 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
1816 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00018400
1818 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00018401
1820 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00018402
1822 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00018403
1823 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
1824 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
1825 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
1827 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
1829 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
1830 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
1831 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
1833 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
1836 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00018404
1837 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
1838 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
1839 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
1841 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
1843 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
1844 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
1845 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
1847 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
1849 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
1850 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
1851 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
1853 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
1856 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00018405
1857 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
1858 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
1859 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
1861 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
1864 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00018408
1866 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00018409
1868 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0001840a
1870 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0001840b
1872 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0001840c
1874 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0001840d
1876 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0001840e
1878 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0001840f
1880 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00018410
1881 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
1882 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
1883 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
1885 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
1887 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
1888 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
1889 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
1891 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
1893 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
1894 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
1895 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
1897 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
1899 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
1900 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
1901 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
1903 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
1905 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
1906 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
1907 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
1909 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
1911 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
1912 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
1913 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
1915 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
1917 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
1918 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
1919 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
1921 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
1923 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
1924 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
1925 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
1927 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
1930 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00018411
1931 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
1932 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
1933 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
1935 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
1937 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
1938 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
1939 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
1941 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
1943 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
1944 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
1945 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
1947 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
1949 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
1950 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
1951 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
1953 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
1955 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
1956 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
1957 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
1959 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
1961 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
1962 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
1963 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
1965 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
1967 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
1968 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
1969 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
1971 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
1973 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
1974 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
1975 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
1977 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
1980 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0001842f
1982 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00018430
1984 #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
1986 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
1988 #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
1990 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
1992 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
1994 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
1996 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
1998 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
2000 #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
2002 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
2004 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
2006 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
2008 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
2010 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
2012 #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
2014 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
2016 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
2018 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
2020 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
2022 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
2024 #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
2026 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
2028 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
2030 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
2032 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
2034 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
2036 #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
2038 #define REG_A6XX_X1_WINDOW_OFFSET 0x000088d4
2039 #define A6XX_X1_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2040 #define A6XX_X1_WINDOW_OFFSET_X__MASK 0x00007fff
2041 #define A6XX_X1_WINDOW_OFFSET_X__SHIFT 0
2042 static inline uint32_t A6XX_X1_WINDOW_OFFSET_X(uint32_t val)
2044 return ((val) << A6XX_X1_WINDOW_OFFSET_X__SHIFT) & A6XX_X1_WINDOW_OFFSET_X__MASK;
2046 #define A6XX_X1_WINDOW_OFFSET_Y__MASK 0x7fff0000
2047 #define A6XX_X1_WINDOW_OFFSET_Y__SHIFT 16
2048 static inline uint32_t A6XX_X1_WINDOW_OFFSET_Y(uint32_t val)
2050 return ((val) << A6XX_X1_WINDOW_OFFSET_Y__SHIFT) & A6XX_X1_WINDOW_OFFSET_Y__MASK;
2053 #define REG_A6XX_X2_WINDOW_OFFSET 0x0000b4d1
2054 #define A6XX_X2_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2055 #define A6XX_X2_WINDOW_OFFSET_X__MASK 0x00007fff
2056 #define A6XX_X2_WINDOW_OFFSET_X__SHIFT 0
2057 static inline uint32_t A6XX_X2_WINDOW_OFFSET_X(uint32_t val)
2059 return ((val) << A6XX_X2_WINDOW_OFFSET_X__SHIFT) & A6XX_X2_WINDOW_OFFSET_X__MASK;
2061 #define A6XX_X2_WINDOW_OFFSET_Y__MASK 0x7fff0000
2062 #define A6XX_X2_WINDOW_OFFSET_Y__SHIFT 16
2063 static inline uint32_t A6XX_X2_WINDOW_OFFSET_Y(uint32_t val)
2065 return ((val) << A6XX_X2_WINDOW_OFFSET_Y__SHIFT) & A6XX_X2_WINDOW_OFFSET_Y__MASK;
2068 #define REG_A6XX_X3_WINDOW_OFFSET 0x0000b307
2069 #define A6XX_X3_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2070 #define A6XX_X3_WINDOW_OFFSET_X__MASK 0x00007fff
2071 #define A6XX_X3_WINDOW_OFFSET_X__SHIFT 0
2072 static inline uint32_t A6XX_X3_WINDOW_OFFSET_X(uint32_t val)
2074 return ((val) << A6XX_X3_WINDOW_OFFSET_X__SHIFT) & A6XX_X3_WINDOW_OFFSET_X__MASK;
2076 #define A6XX_X3_WINDOW_OFFSET_Y__MASK 0x7fff0000
2077 #define A6XX_X3_WINDOW_OFFSET_Y__SHIFT 16
2078 static inline uint32_t A6XX_X3_WINDOW_OFFSET_Y(uint32_t val)
2080 return ((val) << A6XX_X3_WINDOW_OFFSET_Y__SHIFT) & A6XX_X3_WINDOW_OFFSET_Y__MASK;
2083 #define REG_A6XX_X1_BIN_SIZE 0x000080a1
2084 #define A6XX_X1_BIN_SIZE_WIDTH__MASK 0x000000ff
2085 #define A6XX_X1_BIN_SIZE_WIDTH__SHIFT 0
2086 static inline uint32_t A6XX_X1_BIN_SIZE_WIDTH(uint32_t val)
2088 return ((val >> 5) << A6XX_X1_BIN_SIZE_WIDTH__SHIFT) & A6XX_X1_BIN_SIZE_WIDTH__MASK;
2090 #define A6XX_X1_BIN_SIZE_HEIGHT__MASK 0x0001ff00
2091 #define A6XX_X1_BIN_SIZE_HEIGHT__SHIFT 8
2092 static inline uint32_t A6XX_X1_BIN_SIZE_HEIGHT(uint32_t val)
2094 return ((val >> 4) << A6XX_X1_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X1_BIN_SIZE_HEIGHT__MASK;
2097 #define REG_A6XX_X2_BIN_SIZE 0x00008800
2098 #define A6XX_X2_BIN_SIZE_WIDTH__MASK 0x000000ff
2099 #define A6XX_X2_BIN_SIZE_WIDTH__SHIFT 0
2100 static inline uint32_t A6XX_X2_BIN_SIZE_WIDTH(uint32_t val)
2102 return ((val >> 5) << A6XX_X2_BIN_SIZE_WIDTH__SHIFT) & A6XX_X2_BIN_SIZE_WIDTH__MASK;
2104 #define A6XX_X2_BIN_SIZE_HEIGHT__MASK 0x0001ff00
2105 #define A6XX_X2_BIN_SIZE_HEIGHT__SHIFT 8
2106 static inline uint32_t A6XX_X2_BIN_SIZE_HEIGHT(uint32_t val)
2108 return ((val >> 4) << A6XX_X2_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X2_BIN_SIZE_HEIGHT__MASK;
2111 #define REG_A6XX_X3_BIN_SIZE 0x000088d3
2112 #define A6XX_X3_BIN_SIZE_WIDTH__MASK 0x000000ff
2113 #define A6XX_X3_BIN_SIZE_WIDTH__SHIFT 0
2114 static inline uint32_t A6XX_X3_BIN_SIZE_WIDTH(uint32_t val)
2116 return ((val >> 5) << A6XX_X3_BIN_SIZE_WIDTH__SHIFT) & A6XX_X3_BIN_SIZE_WIDTH__MASK;
2118 #define A6XX_X3_BIN_SIZE_HEIGHT__MASK 0x0001ff00
2119 #define A6XX_X3_BIN_SIZE_HEIGHT__SHIFT 8
2120 static inline uint32_t A6XX_X3_BIN_SIZE_HEIGHT(uint32_t val)
2122 return ((val >> 4) << A6XX_X3_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X3_BIN_SIZE_HEIGHT__MASK;
2125 #define REG_A6XX_VSC_BIN_SIZE 0x00000c02
2126 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
2127 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2128 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2130 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
2132 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
2133 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
2134 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2136 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2139 #define REG_A6XX_VSC_SIZE_ADDRESS_LO 0x00000c03
2141 #define REG_A6XX_VSC_SIZE_ADDRESS_HI 0x00000c04
2143 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06
2144 #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
2145 #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
2146 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
2148 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
2150 #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800
2151 #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11
2152 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
2154 return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
2157 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2159 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2160 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2161 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
2162 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2164 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
2166 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2167 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
2168 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2170 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2172 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000
2173 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
2174 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2176 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
2178 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
2179 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
2180 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2182 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2185 #define REG_A6XX_VSC_XXX_ADDRESS_LO 0x00000c30
2187 #define REG_A6XX_VSC_XXX_ADDRESS_HI 0x00000c31
2189 #define REG_A6XX_VSC_XXX_PITCH 0x00000c32
2191 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO 0x00000c34
2193 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI 0x00000c35
2195 #define REG_A6XX_VSC_PIPE_DATA_PITCH 0x00000c36
2197 static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2199 static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2201 #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
2203 #define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001
2205 #define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004
2207 #define REG_A6XX_GRAS_CNTL 0x00008005
2208 #define A6XX_GRAS_CNTL_VARYING 0x00000001
2209 #define A6XX_GRAS_CNTL_XCOORD 0x00000040
2210 #define A6XX_GRAS_CNTL_YCOORD 0x00000080
2211 #define A6XX_GRAS_CNTL_ZCOORD 0x00000100
2212 #define A6XX_GRAS_CNTL_WCOORD 0x00000200
2214 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
2215 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
2216 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
2217 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2219 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2221 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
2222 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
2223 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2225 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2228 #define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0 0x00008010
2229 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2230 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2231 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2233 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2236 #define REG_A6XX_GRAS_CL_VPORT_XSCALE_0 0x00008011
2237 #define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2238 #define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2239 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val)
2241 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2244 #define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0 0x00008012
2245 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2246 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2247 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2249 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2252 #define REG_A6XX_GRAS_CL_VPORT_YSCALE_0 0x00008013
2253 #define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2254 #define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2255 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val)
2257 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2260 #define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0 0x00008014
2261 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2262 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2263 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2265 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2268 #define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0 0x00008015
2269 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2270 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2271 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2273 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2276 #define REG_A6XX_GRAS_SU_CNTL 0x00008090
2277 #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2278 #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2279 #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2280 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2281 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
2282 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2284 return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2286 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2287 #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2289 #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
2290 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2291 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2292 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2294 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2296 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2297 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2298 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2300 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2303 #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092
2304 #define A6XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2305 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0
2306 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
2308 return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2311 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
2312 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2313 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2314 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2316 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2319 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096
2320 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2321 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2322 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2324 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2327 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097
2328 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2329 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2330 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2332 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2335 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098
2336 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2337 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2338 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2340 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2343 #define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099
2345 #define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b
2347 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
2348 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2349 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2350 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2352 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2355 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
2356 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2357 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2358 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2360 return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
2362 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2364 #define REG_A6XX_GRAS_UNKNOWN_80A4 0x000080a4
2366 #define REG_A6XX_GRAS_UNKNOWN_80A5 0x000080a5
2368 #define REG_A6XX_GRAS_UNKNOWN_80A6 0x000080a6
2370 #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
2372 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x000080b0
2373 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2374 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2375 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2376 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2378 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2380 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2381 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2382 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2384 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2387 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x000080b1
2388 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2389 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
2390 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
2391 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2393 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2395 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
2396 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
2397 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2399 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2402 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x000080d0
2403 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2404 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
2405 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
2406 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2408 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2410 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
2411 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
2412 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2414 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2417 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x000080d1
2418 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2419 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
2420 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
2421 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2423 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2425 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
2426 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
2427 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2429 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2432 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0
2433 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2434 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2435 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2436 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2438 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2440 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2441 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2442 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2444 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2447 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1
2448 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2449 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2450 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2451 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2453 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2455 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2456 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2457 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2459 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2462 #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
2463 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2464 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2465 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2467 #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
2468 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
2469 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
2470 static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
2472 return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
2475 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103
2477 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104
2479 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
2480 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000007ff
2481 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
2482 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
2484 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
2486 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800
2487 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
2488 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
2490 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
2493 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106
2495 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
2497 #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
2499 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
2500 #define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0x00ffff00
2501 #define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT 8
2502 static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val)
2504 return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK;
2507 #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
2508 #define A6XX_GRAS_2D_SRC_BR_X_X__MASK 0x00ffff00
2509 #define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT 8
2510 static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val)
2512 return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK;
2515 #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
2516 #define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK 0x00ffff00
2517 #define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT 8
2518 static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val)
2520 return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK;
2523 #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
2524 #define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK 0x00ffff00
2525 #define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT 8
2526 static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val)
2528 return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK;
2531 #define REG_A6XX_GRAS_2D_DST_TL 0x00008405
2532 #define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE 0x80000000
2533 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00007fff
2534 #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0
2535 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
2537 return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
2539 #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x7fff0000
2540 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16
2541 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
2543 return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
2546 #define REG_A6XX_GRAS_2D_DST_BR 0x00008406
2547 #define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE 0x80000000
2548 #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00007fff
2549 #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0
2550 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
2552 return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
2554 #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x7fff0000
2555 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16
2556 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
2558 return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
2561 #define REG_A6XX_GRAS_RESOLVE_CNTL_1 0x0000840a
2562 #define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
2563 #define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK 0x00007fff
2564 #define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT 0
2565 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val)
2567 return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK;
2569 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
2570 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT 16
2571 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val)
2573 return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK;
2576 #define REG_A6XX_GRAS_RESOLVE_CNTL_2 0x0000840b
2577 #define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
2578 #define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK 0x00007fff
2579 #define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT 0
2580 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val)
2582 return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK;
2584 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
2585 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT 16
2586 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val)
2588 return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK;
2591 #define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
2593 #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
2594 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2595 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2596 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2598 return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
2601 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
2602 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2603 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2604 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2606 return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
2608 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2610 #define REG_A6XX_RB_UNKNOWN_8804 0x00008804
2612 #define REG_A6XX_RB_UNKNOWN_8805 0x00008805
2614 #define REG_A6XX_RB_UNKNOWN_8806 0x00008806
2616 #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
2617 #define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001
2618 #define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
2619 #define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
2620 #define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
2621 #define A6XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
2622 #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
2624 #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
2625 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
2626 #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
2627 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
2629 #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
2630 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
2632 #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
2633 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
2634 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0
2635 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
2637 return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
2640 #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d
2641 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
2642 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
2643 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
2645 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
2647 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
2648 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
2649 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
2651 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
2653 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
2654 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
2655 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
2657 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
2659 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
2660 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
2661 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
2663 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
2665 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
2666 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
2667 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
2669 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
2671 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
2672 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
2673 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
2675 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
2677 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
2678 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
2679 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
2681 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
2683 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
2684 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
2685 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
2687 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
2690 #define REG_A6XX_RB_DITHER_CNTL 0x0000880e
2691 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003
2692 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0
2693 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
2695 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
2697 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c
2698 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2
2699 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
2701 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
2703 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030
2704 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4
2705 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
2707 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
2709 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0
2710 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6
2711 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
2713 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
2715 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300
2716 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8
2717 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
2719 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
2721 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00
2722 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10
2723 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
2725 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
2727 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000
2728 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
2729 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
2731 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
2733 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000
2734 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14
2735 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
2737 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
2740 #define REG_A6XX_RB_SRGB_CNTL 0x0000880f
2741 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001
2742 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002
2743 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004
2744 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008
2745 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010
2746 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020
2747 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
2748 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
2750 #define REG_A6XX_RB_UNKNOWN_8818 0x00008818
2752 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819
2754 #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a
2756 #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b
2758 #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c
2760 #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d
2762 #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
2764 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
2766 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
2767 #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
2768 #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002
2769 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
2770 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
2771 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
2772 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
2774 return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
2776 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
2777 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
2778 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
2780 return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
2783 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
2784 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
2785 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
2786 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
2788 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
2790 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
2791 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
2792 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
2794 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
2796 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
2797 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
2798 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
2800 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
2802 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
2803 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
2804 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
2806 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
2808 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
2809 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
2810 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
2812 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
2814 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
2815 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
2816 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
2818 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
2821 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
2822 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
2823 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
2824 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
2826 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
2828 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
2829 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
2830 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
2832 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
2834 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
2835 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
2836 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
2838 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
2840 #define A6XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
2842 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
2843 #define A6XX_RB_MRT_PITCH__MASK 0xffffffff
2844 #define A6XX_RB_MRT_PITCH__SHIFT 0
2845 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
2847 return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
2850 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
2851 #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
2852 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
2853 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
2855 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
2858 static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
2860 static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
2862 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
2864 #define REG_A6XX_RB_BLEND_RED_F32 0x00008860
2865 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff
2866 #define A6XX_RB_BLEND_RED_F32__SHIFT 0
2867 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
2869 return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
2872 #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861
2873 #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
2874 #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0
2875 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
2877 return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
2880 #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862
2881 #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
2882 #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0
2883 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
2885 return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
2888 #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863
2889 #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
2890 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0
2891 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
2893 return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
2896 #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864
2897 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
2898 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
2899 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
2901 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
2903 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
2904 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
2905 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
2906 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
2908 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
2911 #define REG_A6XX_RB_BLEND_CNTL 0x00008865
2912 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
2913 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
2914 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
2916 return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
2918 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
2919 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
2920 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
2921 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
2923 return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
2926 #define REG_A6XX_RB_DEPTH_CNTL 0x00008871
2927 #define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
2928 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
2929 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
2930 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
2931 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
2933 return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
2935 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
2937 #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
2938 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2939 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2940 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2942 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2945 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873
2946 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
2947 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
2948 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
2950 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
2953 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
2954 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
2955 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
2956 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
2958 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
2961 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875
2963 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876
2965 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
2967 #define REG_A6XX_RB_UNKNOWN_8878 0x00008878
2969 #define REG_A6XX_RB_UNKNOWN_8879 0x00008879
2971 #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880
2972 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
2973 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
2974 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
2975 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
2976 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
2977 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
2979 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
2981 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
2982 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
2983 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
2985 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
2987 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
2988 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
2989 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
2991 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
2993 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
2994 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
2995 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
2997 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
2999 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3000 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
3001 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3003 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3005 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3006 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
3007 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3009 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3011 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3012 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
3013 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3015 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3017 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3018 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
3019 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3021 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3024 #define REG_A6XX_RB_STENCIL_INFO 0x00008881
3025 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3027 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882
3028 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0xffffffff
3029 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0
3030 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
3032 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
3035 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
3036 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3037 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
3038 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
3040 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3043 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884
3045 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885
3047 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
3049 #define REG_A6XX_RB_STENCILREF 0x00008887
3050 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff
3051 #define A6XX_RB_STENCILREF_REF__SHIFT 0
3052 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
3054 return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
3057 #define REG_A6XX_RB_STENCILMASK 0x00008888
3058 #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff
3059 #define A6XX_RB_STENCILMASK_MASK__SHIFT 0
3060 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
3062 return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
3065 #define REG_A6XX_RB_STENCILWRMASK 0x00008889
3066 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff
3067 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0
3068 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
3070 return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
3073 #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890
3074 #define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
3075 #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
3076 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0
3077 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
3079 return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
3081 #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
3082 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16
3083 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3085 return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
3088 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
3089 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3091 #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
3093 #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
3094 #define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3095 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00007fff
3096 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0
3097 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
3099 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
3101 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x7fff0000
3102 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16
3103 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
3105 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
3108 #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2
3109 #define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3110 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00007fff
3111 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0
3112 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
3114 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
3116 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x7fff0000
3117 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16
3118 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
3120 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
3123 #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
3125 #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
3126 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003
3127 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0
3128 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3130 return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
3132 #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
3133 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
3134 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
3135 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3137 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
3139 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060
3140 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5
3141 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3143 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
3146 #define REG_A6XX_RB_BLIT_DST_LO 0x000088d8
3148 #define REG_A6XX_RB_BLIT_DST_HI 0x000088d9
3150 #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
3151 #define A6XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
3152 #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
3153 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
3155 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
3158 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db
3159 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
3160 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
3161 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3163 return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3166 #define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc
3168 #define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
3170 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
3172 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
3174 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
3176 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
3178 #define REG_A6XX_RB_BLIT_INFO 0x000088e3
3179 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001
3180 #define A6XX_RB_BLIT_INFO_FAST_CLEAR 0x00000002
3181 #define A6XX_RB_BLIT_INFO_INTEGER 0x00000004
3182 #define A6XX_RB_BLIT_INFO_UNK3 0x00000008
3183 #define A6XX_RB_BLIT_INFO_MASK__MASK 0x000000f0
3184 #define A6XX_RB_BLIT_INFO_MASK__SHIFT 4
3185 static inline uint32_t A6XX_RB_BLIT_INFO_MASK(uint32_t val)
3187 return ((val) << A6XX_RB_BLIT_INFO_MASK__SHIFT) & A6XX_RB_BLIT_INFO_MASK__MASK;
3190 #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
3192 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900
3194 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
3196 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
3198 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3200 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3202 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
3204 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
3205 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
3206 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
3207 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3209 return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
3211 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800
3212 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3213 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3215 return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3218 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927
3220 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928
3222 #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
3223 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
3224 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
3225 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
3227 return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3230 #define REG_A6XX_RB_2D_DST_INFO 0x00008c17
3231 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3232 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3233 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
3235 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
3237 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
3238 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
3239 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3241 return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
3243 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3244 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3245 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3247 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
3249 #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000
3251 #define REG_A6XX_RB_2D_DST_LO 0x00008c18
3253 #define REG_A6XX_RB_2D_DST_HI 0x00008c19
3255 #define REG_A6XX_RB_2D_DST_SIZE 0x00008c1a
3256 #define A6XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
3257 #define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
3258 static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
3260 return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK;
3263 #define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20
3265 #define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
3267 #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
3269 #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
3271 #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e
3273 #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f
3275 #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01
3277 #define REG_A6XX_RB_CCU_CNTL 0x00008e07
3279 #define REG_A6XX_VPC_UNKNOWN_9101 0x00009101
3281 #define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104
3283 #define REG_A6XX_VPC_UNKNOWN_9108 0x00009108
3285 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
3287 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
3289 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
3291 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
3293 #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210
3295 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
3297 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
3299 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
3301 #define REG_A6XX_VPC_SO_CNTL 0x00009216
3302 #define A6XX_VPC_SO_CNTL_ENABLE 0x00010000
3304 #define REG_A6XX_VPC_SO_PROG 0x00009217
3305 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
3306 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
3307 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
3309 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
3311 #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
3312 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2
3313 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
3315 return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
3317 #define A6XX_VPC_SO_PROG_A_EN 0x00000800
3318 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
3319 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12
3320 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
3322 return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
3324 #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
3325 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
3326 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
3328 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
3330 #define A6XX_VPC_SO_PROG_B_EN 0x00800000
3332 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
3334 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
3336 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
3338 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
3340 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
3342 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
3344 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
3346 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
3348 #define REG_A6XX_VPC_UNKNOWN_9236 0x00009236
3350 #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
3352 #define REG_A6XX_VPC_PACK 0x00009301
3353 #define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK 0x000000ff
3354 #define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT 0
3355 static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val)
3357 return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK;
3359 #define A6XX_VPC_PACK_NUMNONPOSVAR__MASK 0x0000ff00
3360 #define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT 8
3361 static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3363 return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK;
3365 #define A6XX_VPC_PACK_PSIZELOC__MASK 0x00ff0000
3366 #define A6XX_VPC_PACK_PSIZELOC__SHIFT 16
3367 static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val)
3369 return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK;
3372 #define REG_A6XX_VPC_CNTL_0 0x00009304
3373 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
3374 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
3375 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
3377 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
3379 #define A6XX_VPC_CNTL_0_VARYING 0x00010000
3381 #define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305
3382 #define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
3383 #define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
3384 #define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
3385 #define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
3386 #define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
3388 #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600
3390 #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
3392 #define REG_A6XX_PC_UNKNOWN_9801 0x00009801
3394 #define REG_A6XX_PC_RESTART_INDEX 0x00009803
3396 #define REG_A6XX_PC_MODE_CNTL 0x00009804
3398 #define REG_A6XX_PC_UNKNOWN_9805 0x00009805
3400 #define REG_A6XX_PC_UNKNOWN_9981 0x00009981
3402 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
3403 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
3404 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
3406 #define REG_A6XX_PC_PRIMITIVE_CNTL_1 0x00009b01
3407 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK 0x0000007f
3408 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT 0
3409 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
3411 return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK;
3414 #define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06
3416 #define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07
3418 #define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08
3420 #define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09
3422 #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
3424 #define REG_A6XX_VFD_CONTROL_0 0x0000a000
3425 #define A6XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
3426 #define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
3427 static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
3429 return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK;
3432 #define REG_A6XX_VFD_CONTROL_1 0x0000a001
3433 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
3434 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
3435 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
3437 return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
3439 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
3440 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
3441 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
3443 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
3445 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
3446 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
3447 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
3449 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
3452 #define REG_A6XX_VFD_CONTROL_2 0x0000a002
3453 #define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
3454 #define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
3455 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
3457 return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
3460 #define REG_A6XX_VFD_CONTROL_3 0x0000a003
3461 #define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
3462 #define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
3463 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
3465 return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
3467 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
3468 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
3469 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
3471 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
3473 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
3474 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
3475 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
3477 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
3480 #define REG_A6XX_VFD_CONTROL_4 0x0000a004
3482 #define REG_A6XX_VFD_CONTROL_5 0x0000a005
3484 #define REG_A6XX_VFD_CONTROL_6 0x0000a006
3486 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007
3487 #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
3489 #define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008
3491 #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
3493 #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
3495 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
3497 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
3499 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
3501 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
3503 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
3505 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
3507 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
3508 #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
3509 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0
3510 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
3512 return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
3514 #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
3515 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
3516 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
3517 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val)
3519 return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
3521 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
3522 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
3523 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3525 return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
3527 #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000
3528 #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000
3530 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
3532 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
3534 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
3535 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
3536 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
3537 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
3539 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
3541 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
3542 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
3543 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
3545 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
3548 #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
3550 #define REG_A6XX_SP_PRIMITIVE_CNTL 0x0000a802
3551 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
3552 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
3553 static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
3555 return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
3558 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
3560 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
3561 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
3562 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
3563 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
3565 return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
3567 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
3568 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
3569 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
3571 return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
3573 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
3574 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
3575 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
3577 return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
3579 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
3580 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
3581 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
3583 return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
3586 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
3588 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
3589 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
3590 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
3591 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
3593 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
3595 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
3596 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
3597 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
3599 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
3601 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
3602 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
3603 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
3605 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
3607 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
3608 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
3609 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
3611 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
3614 #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
3615 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
3616 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
3617 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3619 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3621 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
3622 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
3623 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3625 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3627 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
3628 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
3629 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
3631 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
3633 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
3634 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
3635 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
3637 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
3639 #define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
3640 #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
3641 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
3643 #define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c
3645 #define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d
3647 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
3649 #define REG_A6XX_SP_VS_CONFIG 0x0000a823
3650 #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100
3651 #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00
3652 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9
3653 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
3655 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
3657 #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x01fe0000
3658 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
3659 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
3661 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
3664 #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
3666 #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
3667 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
3668 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
3669 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3671 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3673 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
3674 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
3675 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3677 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3679 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
3680 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
3681 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
3683 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
3685 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000
3686 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20
3687 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
3689 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
3691 #define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000
3692 #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000
3693 #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000
3695 #define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831
3697 #define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834
3699 #define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835
3701 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
3703 #define REG_A6XX_SP_HS_CONFIG 0x0000a83b
3704 #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100
3705 #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00
3706 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9
3707 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
3709 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
3711 #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x01fe0000
3712 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
3713 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
3715 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
3718 #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
3720 #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
3721 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
3722 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
3723 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3725 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3727 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
3728 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
3729 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3731 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3733 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
3734 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
3735 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
3737 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
3739 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000
3740 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20
3741 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
3743 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
3745 #define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000
3746 #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
3747 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
3749 #define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c
3751 #define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d
3753 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
3755 #define REG_A6XX_SP_DS_CONFIG 0x0000a863
3756 #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100
3757 #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00
3758 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9
3759 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
3761 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
3763 #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x01fe0000
3764 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
3765 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
3767 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
3770 #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
3772 #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
3773 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
3774 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
3775 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3777 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3779 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
3780 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
3781 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3783 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3785 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
3786 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
3787 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
3789 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
3791 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000
3792 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20
3793 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
3795 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
3797 #define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000
3798 #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000
3799 #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000
3801 #define REG_A6XX_SP_GS_UNKNOWN_A871 0x0000a871
3803 #define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d
3805 #define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e
3807 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
3809 #define REG_A6XX_SP_GS_CONFIG 0x0000a894
3810 #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100
3811 #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00
3812 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9
3813 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
3815 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
3817 #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x01fe0000
3818 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
3819 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
3821 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
3824 #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
3826 #define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0
3828 #define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1
3830 #define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2
3832 #define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3
3834 #define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4
3836 #define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5
3838 #define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6
3840 #define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7
3842 #define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8
3844 #define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9
3846 #define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa
3848 #define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab
3850 #define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac
3852 #define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad
3854 #define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae
3856 #define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af
3858 #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
3859 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
3860 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
3861 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3863 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3865 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
3866 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
3867 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3869 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3871 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
3872 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
3873 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
3875 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
3877 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
3878 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
3879 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
3881 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
3883 #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
3884 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
3885 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
3887 #define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983
3889 #define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984
3891 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989
3892 #define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
3893 #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
3895 #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
3896 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
3897 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
3898 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004
3899 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008
3900 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010
3901 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020
3902 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040
3903 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080
3905 #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b
3906 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f
3907 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0
3908 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
3910 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
3912 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0
3913 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4
3914 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
3916 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
3918 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3919 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8
3920 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
3922 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
3924 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3925 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12
3926 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
3928 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
3930 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3931 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16
3932 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
3934 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
3936 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3937 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20
3938 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
3940 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
3942 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3943 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24
3944 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
3946 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
3948 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3949 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28
3950 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
3952 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
3955 #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c
3956 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00
3957 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8
3958 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
3960 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
3963 #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
3964 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
3965 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
3966 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
3968 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
3971 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
3973 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
3974 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
3975 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
3976 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
3978 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
3980 #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
3981 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
3982 #define A6XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
3984 #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
3986 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
3988 #define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0
3990 #define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1
3992 #define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2
3994 #define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3
3996 #define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4
3998 #define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5
4000 #define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6
4002 #define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7
4004 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
4006 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
4007 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
4008 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
4009 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4011 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
4013 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
4015 #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
4016 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4017 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4018 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4020 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4022 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
4023 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
4024 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4026 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4028 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4029 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4030 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4032 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4034 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
4035 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
4036 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4038 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4040 #define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000
4041 #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000
4042 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
4044 #define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4
4046 #define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5
4048 #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
4050 #define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00
4052 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04
4053 #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
4054 #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
4055 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
4056 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
4058 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
4060 #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x01fe0000
4061 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
4062 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
4064 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
4067 #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
4069 #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
4071 #define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04
4073 #define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f
4075 #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
4077 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
4078 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
4079 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
4080 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4082 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4085 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
4086 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
4087 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
4088 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4090 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4092 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
4094 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302
4096 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303
4098 #define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304
4100 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
4101 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
4102 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
4103 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
4105 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
4107 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
4108 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
4109 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
4111 return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
4113 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
4114 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
4115 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4117 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
4119 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
4121 #define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
4123 #define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
4125 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
4127 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
4129 #define REG_A6XX_SP_UNKNOWN_B600 0x0000b600
4131 #define REG_A6XX_SP_UNKNOWN_B605 0x0000b605
4133 #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
4134 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
4135 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
4136 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
4138 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
4141 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
4142 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
4143 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
4144 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
4146 return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
4149 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
4150 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
4151 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
4152 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
4154 return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
4157 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
4158 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
4159 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
4160 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
4162 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
4165 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
4167 #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
4168 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
4169 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
4170 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4172 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4174 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
4175 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
4176 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
4178 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
4180 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
4181 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
4182 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
4184 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
4187 #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
4188 #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
4189 #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
4190 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
4192 return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
4195 #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
4196 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
4197 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
4198 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4200 return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4202 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
4203 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
4204 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4206 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4209 #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
4211 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
4212 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
4213 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
4214 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4216 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4218 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
4219 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
4220 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4222 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4224 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
4225 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
4226 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4228 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4230 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
4231 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
4232 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4234 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4237 #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991
4238 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
4239 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
4240 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
4242 return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
4245 #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992
4246 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
4247 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
4248 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
4250 return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
4253 #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993
4254 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
4255 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
4256 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
4258 return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
4261 #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994
4262 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
4263 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
4264 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
4266 return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
4269 #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995
4270 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
4271 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
4272 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
4274 return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
4277 #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996
4278 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
4279 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
4280 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
4282 return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
4285 #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
4286 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
4287 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
4288 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
4290 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
4292 #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
4293 #define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
4294 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
4296 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
4298 #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
4299 #define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
4300 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
4302 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
4304 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
4305 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
4306 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
4308 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
4311 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
4313 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
4315 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
4317 #define REG_A6XX_HLSQ_UPDATE_CNTL 0x0000bb08
4319 #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
4320 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
4321 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
4322 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
4324 return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
4327 #define REG_A6XX_HLSQ_UNKNOWN_BB11 0x0000bb11
4329 #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
4331 #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
4333 #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
4335 #define REG_A6XX_TEX_SAMP_0 0x00000000
4336 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
4337 #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
4338 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1
4339 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
4341 return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
4343 #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
4344 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3
4345 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
4347 return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
4349 #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
4350 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5
4351 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
4353 return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
4355 #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
4356 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8
4357 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
4359 return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
4361 #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
4362 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11
4363 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
4365 return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
4367 #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
4368 #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14
4369 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
4371 return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
4373 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
4374 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
4375 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
4377 return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
4380 #define REG_A6XX_TEX_SAMP_1 0x00000001
4381 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
4382 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
4383 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
4385 return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
4387 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
4388 #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
4389 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
4390 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
4391 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
4392 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
4394 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
4396 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
4397 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
4398 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
4400 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
4403 #define REG_A6XX_TEX_SAMP_2 0x00000002
4404 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
4405 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
4406 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
4408 return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
4411 #define REG_A6XX_TEX_SAMP_3 0x00000003
4413 #define REG_A6XX_TEX_CONST_0 0x00000000
4414 #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
4415 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
4416 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
4418 return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
4420 #define A6XX_TEX_CONST_0_SRGB 0x00000004
4421 #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
4422 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4
4423 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
4425 return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
4427 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
4428 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
4429 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
4431 return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
4433 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
4434 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
4435 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
4437 return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
4439 #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
4440 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13
4441 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
4443 return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
4445 #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
4446 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16
4447 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
4449 return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
4451 #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
4452 #define A6XX_TEX_CONST_0_FMT__SHIFT 22
4453 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val)
4455 return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
4457 #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000
4458 #define A6XX_TEX_CONST_0_SWAP__SHIFT 30
4459 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
4461 return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
4464 #define REG_A6XX_TEX_CONST_1 0x00000001
4465 #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
4466 #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0
4467 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
4469 return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
4471 #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
4472 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15
4473 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
4475 return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
4478 #define REG_A6XX_TEX_CONST_2 0x00000002
4479 #define A6XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
4480 #define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
4481 static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val)
4483 return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK;
4485 #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
4486 #define A6XX_TEX_CONST_2_PITCH__SHIFT 7
4487 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
4489 return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
4491 #define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000
4492 #define A6XX_TEX_CONST_2_TYPE__SHIFT 29
4493 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
4495 return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
4498 #define REG_A6XX_TEX_CONST_3 0x00000003
4499 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
4500 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
4501 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
4503 return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
4505 #define A6XX_TEX_CONST_3_FLAG 0x10000000
4507 #define REG_A6XX_TEX_CONST_4 0x00000004
4508 #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
4509 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5
4510 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
4512 return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
4515 #define REG_A6XX_TEX_CONST_5 0x00000005
4516 #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
4517 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0
4518 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
4520 return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
4522 #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
4523 #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17
4524 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
4526 return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
4529 #define REG_A6XX_TEX_CONST_6 0x00000006
4531 #define REG_A6XX_TEX_CONST_7 0x00000007
4532 #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0
4533 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5
4534 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
4536 return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
4539 #define REG_A6XX_TEX_CONST_8 0x00000008
4540 #define A6XX_TEX_CONST_8_BASE_HI__MASK 0x0001ffff
4541 #define A6XX_TEX_CONST_8_BASE_HI__SHIFT 0
4542 static inline uint32_t A6XX_TEX_CONST_8_BASE_HI(uint32_t val)
4544 return ((val) << A6XX_TEX_CONST_8_BASE_HI__SHIFT) & A6XX_TEX_CONST_8_BASE_HI__MASK;
4547 #define REG_A6XX_TEX_CONST_9 0x00000009
4549 #define REG_A6XX_TEX_CONST_10 0x0000000a
4551 #define REG_A6XX_TEX_CONST_11 0x0000000b
4553 #define REG_A6XX_TEX_CONST_12 0x0000000c
4555 #define REG_A6XX_TEX_CONST_13 0x0000000d
4557 #define REG_A6XX_TEX_CONST_14 0x0000000e
4559 #define REG_A6XX_TEX_CONST_15 0x0000000f
4562 #endif /* A6XX_XML */