1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
9 #include "adreno_gpu.h"
13 bool hang_debug = false;
14 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
15 module_param_named(hang_debug, hang_debug, bool, 0600);
17 static const struct adreno_info gpulist[] = {
19 .rev = ADRENO_REV(2, 0, 0, 0),
23 [ADRENO_FW_PM4] = "yamato_pm4.fw",
24 [ADRENO_FW_PFP] = "yamato_pfp.fw",
27 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
28 .init = a2xx_gpu_init,
29 }, { /* a200 on i.mx51 has only 128kib gmem */
30 .rev = ADRENO_REV(2, 0, 0, 1),
34 [ADRENO_FW_PM4] = "yamato_pm4.fw",
35 [ADRENO_FW_PFP] = "yamato_pfp.fw",
38 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
39 .init = a2xx_gpu_init,
41 .rev = ADRENO_REV(2, 2, 0, ANY_ID),
45 [ADRENO_FW_PM4] = "leia_pm4_470.fw",
46 [ADRENO_FW_PFP] = "leia_pfp_470.fw",
49 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
50 .init = a2xx_gpu_init,
52 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
56 [ADRENO_FW_PM4] = "a300_pm4.fw",
57 [ADRENO_FW_PFP] = "a300_pfp.fw",
60 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
61 .init = a3xx_gpu_init,
63 .rev = ADRENO_REV(3, 0, 6, 0),
64 .revn = 307, /* because a305c is revn==306 */
67 [ADRENO_FW_PM4] = "a300_pm4.fw",
68 [ADRENO_FW_PFP] = "a300_pfp.fw",
71 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
72 .init = a3xx_gpu_init,
74 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
78 [ADRENO_FW_PM4] = "a300_pm4.fw",
79 [ADRENO_FW_PFP] = "a300_pfp.fw",
82 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
83 .init = a3xx_gpu_init,
85 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
89 [ADRENO_FW_PM4] = "a330_pm4.fw",
90 [ADRENO_FW_PFP] = "a330_pfp.fw",
93 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
94 .init = a3xx_gpu_init,
96 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
100 [ADRENO_FW_PM4] = "a420_pm4.fw",
101 [ADRENO_FW_PFP] = "a420_pfp.fw",
103 .gmem = (SZ_1M + SZ_512K),
104 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
105 .init = a4xx_gpu_init,
107 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
111 [ADRENO_FW_PM4] = "a420_pm4.fw",
112 [ADRENO_FW_PFP] = "a420_pfp.fw",
114 .gmem = (SZ_1M + SZ_512K),
115 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
116 .init = a4xx_gpu_init,
118 .rev = ADRENO_REV(5, 3, 0, 2),
122 [ADRENO_FW_PM4] = "a530_pm4.fw",
123 [ADRENO_FW_PFP] = "a530_pfp.fw",
124 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
128 * Increase inactive period to 250 to avoid bouncing
129 * the GDSC which appears to make it grumpy
131 .inactive_period = 250,
132 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
133 ADRENO_QUIRK_FAULT_DETECT_MASK,
134 .init = a5xx_gpu_init,
135 .zapfw = "a530_zap.mdt",
137 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
141 [ADRENO_FW_SQE] = "a630_sqe.fw",
142 [ADRENO_FW_GMU] = "a630_gmu.bin",
145 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
146 .init = a6xx_gpu_init,
147 .zapfw = "a630_zap.mdt",
151 MODULE_FIRMWARE("qcom/a300_pm4.fw");
152 MODULE_FIRMWARE("qcom/a300_pfp.fw");
153 MODULE_FIRMWARE("qcom/a330_pm4.fw");
154 MODULE_FIRMWARE("qcom/a330_pfp.fw");
155 MODULE_FIRMWARE("qcom/a420_pm4.fw");
156 MODULE_FIRMWARE("qcom/a420_pfp.fw");
157 MODULE_FIRMWARE("qcom/a530_pm4.fw");
158 MODULE_FIRMWARE("qcom/a530_pfp.fw");
159 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
160 MODULE_FIRMWARE("qcom/a530_zap.mdt");
161 MODULE_FIRMWARE("qcom/a530_zap.b00");
162 MODULE_FIRMWARE("qcom/a530_zap.b01");
163 MODULE_FIRMWARE("qcom/a530_zap.b02");
164 MODULE_FIRMWARE("qcom/a630_sqe.fw");
165 MODULE_FIRMWARE("qcom/a630_gmu.bin");
167 static inline bool _rev_match(uint8_t entry, uint8_t id)
169 return (entry == ANY_ID) || (entry == id);
172 const struct adreno_info *adreno_info(struct adreno_rev rev)
177 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
178 const struct adreno_info *info = &gpulist[i];
179 if (_rev_match(info->rev.core, rev.core) &&
180 _rev_match(info->rev.major, rev.major) &&
181 _rev_match(info->rev.minor, rev.minor) &&
182 _rev_match(info->rev.patchid, rev.patchid))
189 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
191 struct msm_drm_private *priv = dev->dev_private;
192 struct platform_device *pdev = priv->gpu_pdev;
193 struct msm_gpu *gpu = NULL;
194 struct adreno_gpu *adreno_gpu;
198 gpu = platform_get_drvdata(pdev);
201 dev_err_once(dev->dev, "no GPU device was found\n");
205 adreno_gpu = to_adreno_gpu(gpu);
208 * The number one reason for HW init to fail is if the firmware isn't
209 * loaded yet. Try that first and don't bother continuing on
213 ret = adreno_load_fw(adreno_gpu);
217 /* Make sure pm runtime is active and reset any previous errors */
218 pm_runtime_set_active(&pdev->dev);
220 ret = pm_runtime_get_sync(&pdev->dev);
222 pm_runtime_put_sync(&pdev->dev);
223 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
227 mutex_lock(&dev->struct_mutex);
228 ret = msm_gpu_hw_init(gpu);
229 mutex_unlock(&dev->struct_mutex);
230 pm_runtime_put_autosuspend(&pdev->dev);
232 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
236 #ifdef CONFIG_DEBUG_FS
237 if (gpu->funcs->debugfs_init) {
238 gpu->funcs->debugfs_init(gpu, dev->primary);
239 gpu->funcs->debugfs_init(gpu, dev->render);
246 static void set_gpu_pdev(struct drm_device *dev,
247 struct platform_device *pdev)
249 struct msm_drm_private *priv = dev->dev_private;
250 priv->gpu_pdev = pdev;
253 static int find_chipid(struct device *dev, struct adreno_rev *rev)
255 struct device_node *node = dev->of_node;
260 /* first search the compat strings for qcom,adreno-XYZ.W: */
261 ret = of_property_read_string_index(node, "compatible", 0, &compat);
263 unsigned int r, patch;
265 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
266 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
272 rev->patchid = patch;
278 /* and if that fails, fall back to legacy "qcom,chipid" property: */
279 ret = of_property_read_u32(node, "qcom,chipid", &chipid);
281 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
285 rev->core = (chipid >> 24) & 0xff;
286 rev->major = (chipid >> 16) & 0xff;
287 rev->minor = (chipid >> 8) & 0xff;
288 rev->patchid = (chipid & 0xff);
290 dev_warn(dev, "Using legacy qcom,chipid binding!\n");
291 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
292 rev->core, rev->major, rev->minor, rev->patchid);
297 static int adreno_bind(struct device *dev, struct device *master, void *data)
299 static struct adreno_platform_config config = {};
300 const struct adreno_info *info;
301 struct drm_device *drm = dev_get_drvdata(master);
302 struct msm_drm_private *priv = drm->dev_private;
306 ret = find_chipid(dev, &config.rev);
310 dev->platform_data = &config;
311 set_gpu_pdev(drm, to_platform_device(dev));
313 info = adreno_info(config.rev);
316 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
317 config.rev.core, config.rev.major,
318 config.rev.minor, config.rev.patchid);
322 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
323 config.rev.minor, config.rev.patchid);
325 priv->is_a2xx = config.rev.core == 2;
327 gpu = info->init(drm);
329 dev_warn(drm->dev, "failed to load adreno gpu\n");
333 dev_set_drvdata(dev, gpu);
338 static void adreno_unbind(struct device *dev, struct device *master,
341 struct msm_gpu *gpu = dev_get_drvdata(dev);
343 gpu->funcs->pm_suspend(gpu);
344 gpu->funcs->destroy(gpu);
346 set_gpu_pdev(dev_get_drvdata(master), NULL);
349 static const struct component_ops a3xx_ops = {
351 .unbind = adreno_unbind,
354 static void adreno_device_register_headless(void)
356 /* on imx5, we don't have a top-level mdp/dpu node
357 * this creates a dummy node for the driver for that case
359 struct platform_device_info dummy_info = {
369 platform_device_register_full(&dummy_info);
372 static int adreno_probe(struct platform_device *pdev)
377 ret = component_add(&pdev->dev, &a3xx_ops);
381 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
382 adreno_device_register_headless();
387 static int adreno_remove(struct platform_device *pdev)
389 component_del(&pdev->dev, &a3xx_ops);
393 static const struct of_device_id dt_match[] = {
394 { .compatible = "qcom,adreno" },
395 { .compatible = "qcom,adreno-3xx" },
396 /* for compatibility with imx5 gpu: */
397 { .compatible = "amd,imageon" },
398 /* for backwards compat w/ downstream kgsl DT files: */
399 { .compatible = "qcom,kgsl-3d0" },
404 static int adreno_resume(struct device *dev)
406 struct platform_device *pdev = to_platform_device(dev);
407 struct msm_gpu *gpu = platform_get_drvdata(pdev);
409 return gpu->funcs->pm_resume(gpu);
412 static int adreno_suspend(struct device *dev)
414 struct platform_device *pdev = to_platform_device(dev);
415 struct msm_gpu *gpu = platform_get_drvdata(pdev);
417 return gpu->funcs->pm_suspend(gpu);
421 static const struct dev_pm_ops adreno_pm_ops = {
422 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
423 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
426 static struct platform_driver adreno_driver = {
427 .probe = adreno_probe,
428 .remove = adreno_remove,
431 .of_match_table = dt_match,
432 .pm = &adreno_pm_ops,
436 void __init adreno_register(void)
438 platform_driver_register(&adreno_driver);
441 void __exit adreno_unregister(void)
443 platform_driver_unregister(&adreno_driver);