drivers/gpu/drm/msm/adreno/adreno_device.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-2014 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
   7  */
   8
   9 #include "adreno_gpu.h"
  10
  11 #define ANY_ID 0xff
  12
  13 bool hang_debug = false;
  14 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  15 module_param_named(hang_debug, hang_debug, bool, 0600);
  16
  17 static const struct adreno_info gpulist[] = {
  18         {
  19                 .rev   = ADRENO_REV(2, 0, 0, 0),
  20                 .revn  = 200,
  21                 .name  = "A200",
  22                 .fw = {
  23                         [ADRENO_FW_PM4] = "yamato_pm4.fw",
  24                         [ADRENO_FW_PFP] = "yamato_pfp.fw",
  25                 },
  26                 .gmem  = SZ_256K,
  27                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  28                 .init  = a2xx_gpu_init,
  29         }, { /* a200 on i.mx51 has only 128kib gmem */
  30                 .rev   = ADRENO_REV(2, 0, 0, 1),
  31                 .revn  = 201,
  32                 .name  = "A200",
  33                 .fw = {
  34                         [ADRENO_FW_PM4] = "yamato_pm4.fw",
  35                         [ADRENO_FW_PFP] = "yamato_pfp.fw",
  36                 },
  37                 .gmem  = SZ_128K,
  38                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  39                 .init  = a2xx_gpu_init,
  40         }, {
  41                 .rev   = ADRENO_REV(2, 2, 0, ANY_ID),
  42                 .revn  = 220,
  43                 .name  = "A220",
  44                 .fw = {
  45                         [ADRENO_FW_PM4] = "leia_pm4_470.fw",
  46                         [ADRENO_FW_PFP] = "leia_pfp_470.fw",
  47                 },
  48                 .gmem  = SZ_512K,
  49                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  50                 .init  = a2xx_gpu_init,
  51         }, {
  52                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  53                 .revn  = 305,
  54                 .name  = "A305",
  55                 .fw = {
  56                         [ADRENO_FW_PM4] = "a300_pm4.fw",
  57                         [ADRENO_FW_PFP] = "a300_pfp.fw",
  58                 },
  59                 .gmem  = SZ_256K,
  60                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  61                 .init  = a3xx_gpu_init,
  62         }, {
  63                 .rev   = ADRENO_REV(3, 0, 6, 0),
  64                 .revn  = 307,        /* because a305c is revn==306 */
  65                 .name  = "A306",
  66                 .fw = {
  67                         [ADRENO_FW_PM4] = "a300_pm4.fw",
  68                         [ADRENO_FW_PFP] = "a300_pfp.fw",
  69                 },
  70                 .gmem  = SZ_128K,
  71                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  72                 .init  = a3xx_gpu_init,
  73         }, {
  74                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  75                 .revn  = 320,
  76                 .name  = "A320",
  77                 .fw = {
  78                         [ADRENO_FW_PM4] = "a300_pm4.fw",
  79                         [ADRENO_FW_PFP] = "a300_pfp.fw",
  80                 },
  81                 .gmem  = SZ_512K,
  82                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  83                 .init  = a3xx_gpu_init,
  84         }, {
  85                 .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
  86                 .revn  = 330,
  87                 .name  = "A330",
  88                 .fw = {
  89                         [ADRENO_FW_PM4] = "a330_pm4.fw",
  90                         [ADRENO_FW_PFP] = "a330_pfp.fw",
  91                 },
  92                 .gmem  = SZ_1M,
  93                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  94                 .init  = a3xx_gpu_init,
  95         }, {
  96                 .rev   = ADRENO_REV(4, 2, 0, ANY_ID),
  97                 .revn  = 420,
  98                 .name  = "A420",
  99                 .fw = {
 100                         [ADRENO_FW_PM4] = "a420_pm4.fw",
 101                         [ADRENO_FW_PFP] = "a420_pfp.fw",
 102                 },
 103                 .gmem  = (SZ_1M + SZ_512K),
 104                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 105                 .init  = a4xx_gpu_init,
 106         }, {
 107                 .rev   = ADRENO_REV(4, 3, 0, ANY_ID),
 108                 .revn  = 430,
 109                 .name  = "A430",
 110                 .fw = {
 111                         [ADRENO_FW_PM4] = "a420_pm4.fw",
 112                         [ADRENO_FW_PFP] = "a420_pfp.fw",
 113                 },
 114                 .gmem  = (SZ_1M + SZ_512K),
 115                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 116                 .init  = a4xx_gpu_init,
 117         }, {
 118                 .rev   = ADRENO_REV(5, 1, 0, ANY_ID),
 119                 .revn = 510,
 120                 .name = "A510",
 121                 .fw = {
 122                         [ADRENO_FW_PM4] = "a530_pm4.fw",
 123                         [ADRENO_FW_PFP] = "a530_pfp.fw",
 124                 },
 125                 .gmem = SZ_256K,
 126                 /*
 127                  * Increase inactive period to 250 to avoid bouncing
 128                  * the GDSC which appears to make it grumpy
 129                  */
 130                 .inactive_period = 250,
 131                 .init = a5xx_gpu_init,
 132         }, {
 133                 .rev = ADRENO_REV(5, 3, 0, 2),
 134                 .revn = 530,
 135                 .name = "A530",
 136                 .fw = {
 137                         [ADRENO_FW_PM4] = "a530_pm4.fw",
 138                         [ADRENO_FW_PFP] = "a530_pfp.fw",
 139                         [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
 140                 },
 141                 .gmem = SZ_1M,
 142                 /*
 143                  * Increase inactive period to 250 to avoid bouncing
 144                  * the GDSC which appears to make it grumpy
 145                  */
 146                 .inactive_period = 250,
 147                 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
 148                         ADRENO_QUIRK_FAULT_DETECT_MASK,
 149                 .init = a5xx_gpu_init,
 150                 .zapfw = "a530_zap.mdt",
 151         }, {
 152                 .rev = ADRENO_REV(5, 4, 0, 2),
 153                 .revn = 540,
 154                 .name = "A540",
 155                 .fw = {
 156                         [ADRENO_FW_PM4] = "a530_pm4.fw",
 157                         [ADRENO_FW_PFP] = "a530_pfp.fw",
 158                         [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
 159                 },
 160                 .gmem = SZ_1M,
 161                 /*
 162                  * Increase inactive period to 250 to avoid bouncing
 163                  * the GDSC which appears to make it grumpy
 164                  */
 165                 .inactive_period = 250,
 166                 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
 167                 .init = a5xx_gpu_init,
 168                 .zapfw = "a540_zap.mdt",
 169         }, {
 170                 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
 171                 .revn = 630,
 172                 .name = "A630",
 173                 .fw = {
 174                         [ADRENO_FW_SQE] = "a630_sqe.fw",
 175                         [ADRENO_FW_GMU] = "a630_gmu.bin",
 176                 },
 177                 .gmem = SZ_1M,
 178                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 179                 .init = a6xx_gpu_init,
 180                 .zapfw = "a630_zap.mdt",
 181         },
 182 };
 183
 184 MODULE_FIRMWARE("qcom/a300_pm4.fw");
 185 MODULE_FIRMWARE("qcom/a300_pfp.fw");
 186 MODULE_FIRMWARE("qcom/a330_pm4.fw");
 187 MODULE_FIRMWARE("qcom/a330_pfp.fw");
 188 MODULE_FIRMWARE("qcom/a420_pm4.fw");
 189 MODULE_FIRMWARE("qcom/a420_pfp.fw");
 190 MODULE_FIRMWARE("qcom/a530_pm4.fw");
 191 MODULE_FIRMWARE("qcom/a530_pfp.fw");
 192 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
 193 MODULE_FIRMWARE("qcom/a530_zap.mdt");
 194 MODULE_FIRMWARE("qcom/a530_zap.b00");
 195 MODULE_FIRMWARE("qcom/a530_zap.b01");
 196 MODULE_FIRMWARE("qcom/a530_zap.b02");
 197 MODULE_FIRMWARE("qcom/a630_sqe.fw");
 198 MODULE_FIRMWARE("qcom/a630_gmu.bin");
 199 MODULE_FIRMWARE("qcom/a630_zap.mbn");
 200
 201 static inline bool _rev_match(uint8_t entry, uint8_t id)
 202 {
 203         return (entry == ANY_ID) || (entry == id);
 204 }
 205
 206 const struct adreno_info *adreno_info(struct adreno_rev rev)
 207 {
 208         int i;
 209
 210         /* identify gpu: */
 211         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
 212                 const struct adreno_info *info = &gpulist[i];
 213                 if (_rev_match(info->rev.core, rev.core) &&
 214                                 _rev_match(info->rev.major, rev.major) &&
 215                                 _rev_match(info->rev.minor, rev.minor) &&
 216                                 _rev_match(info->rev.patchid, rev.patchid))
 217                         return info;
 218         }
 219
 220         return NULL;
 221 }
 222
 223 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
 224 {
 225         struct msm_drm_private *priv = dev->dev_private;
 226         struct platform_device *pdev = priv->gpu_pdev;
 227         struct msm_gpu *gpu = NULL;
 228         struct adreno_gpu *adreno_gpu;
 229         int ret;
 230
 231         if (pdev)
 232                 gpu = platform_get_drvdata(pdev);
 233
 234         if (!gpu) {
 235                 dev_err_once(dev->dev, "no GPU device was found\n");
 236                 return NULL;
 237         }
 238
 239         adreno_gpu = to_adreno_gpu(gpu);
 240
 241         /*
 242          * The number one reason for HW init to fail is if the firmware isn't
 243          * loaded yet. Try that first and don't bother continuing on
 244          * otherwise
 245          */
 246
 247         ret = adreno_load_fw(adreno_gpu);
 248         if (ret)
 249                 return NULL;
 250
 251         /* Make sure pm runtime is active and reset any previous errors */
 252         pm_runtime_set_active(&pdev->dev);
 253
 254         ret = pm_runtime_get_sync(&pdev->dev);
 255         if (ret < 0) {
 256                 pm_runtime_put_sync(&pdev->dev);
 257                 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
 258                 return NULL;
 259         }
 260
 261         mutex_lock(&dev->struct_mutex);
 262         ret = msm_gpu_hw_init(gpu);
 263         mutex_unlock(&dev->struct_mutex);
 264         pm_runtime_put_autosuspend(&pdev->dev);
 265         if (ret) {
 266                 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
 267                 return NULL;
 268         }
 269
 270 #ifdef CONFIG_DEBUG_FS
 271         if (gpu->funcs->debugfs_init) {
 272                 gpu->funcs->debugfs_init(gpu, dev->primary);
 273                 gpu->funcs->debugfs_init(gpu, dev->render);
 274         }
 275 #endif
 276
 277         return gpu;
 278 }
 279
 280 static void set_gpu_pdev(struct drm_device *dev,
 281                 struct platform_device *pdev)
 282 {
 283         struct msm_drm_private *priv = dev->dev_private;
 284         priv->gpu_pdev = pdev;
 285 }
 286
 287 static int find_chipid(struct device *dev, struct adreno_rev *rev)
 288 {
 289         struct device_node *node = dev->of_node;
 290         const char *compat;
 291         int ret;
 292         u32 chipid;
 293
 294         /* first search the compat strings for qcom,adreno-XYZ.W: */
 295         ret = of_property_read_string_index(node, "compatible", 0, &compat);
 296         if (ret == 0) {
 297                 unsigned int r, patch;
 298
 299                 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
 300                     sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
 301                         rev->core = r / 100;
 302                         r %= 100;
 303                         rev->major = r / 10;
 304                         r %= 10;
 305                         rev->minor = r;
 306                         rev->patchid = patch;
 307
 308                         return 0;
 309                 }
 310         }
 311
 312         /* and if that fails, fall back to legacy "qcom,chipid" property: */
 313         ret = of_property_read_u32(node, "qcom,chipid", &chipid);
 314         if (ret) {
 315                 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
 316                 return ret;
 317         }
 318
 319         rev->core = (chipid >> 24) & 0xff;
 320         rev->major = (chipid >> 16) & 0xff;
 321         rev->minor = (chipid >> 8) & 0xff;
 322         rev->patchid = (chipid & 0xff);
 323
 324         dev_warn(dev, "Using legacy qcom,chipid binding!\n");
 325         dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
 326                 rev->core, rev->major, rev->minor, rev->patchid);
 327
 328         return 0;
 329 }
 330
 331 static int adreno_bind(struct device *dev, struct device *master, void *data)
 332 {
 333         static struct adreno_platform_config config = {};
 334         const struct adreno_info *info;
 335         struct drm_device *drm = dev_get_drvdata(master);
 336         struct msm_drm_private *priv = drm->dev_private;
 337         struct msm_gpu *gpu;
 338         int ret;
 339
 340         ret = find_chipid(dev, &config.rev);
 341         if (ret)
 342                 return ret;
 343
 344         dev->platform_data = &config;
 345         set_gpu_pdev(drm, to_platform_device(dev));
 346
 347         info = adreno_info(config.rev);
 348
 349         if (!info) {
 350                 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 351                         config.rev.core, config.rev.major,
 352                         config.rev.minor, config.rev.patchid);
 353                 return -ENXIO;
 354         }
 355
 356         DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
 357                 config.rev.minor, config.rev.patchid);
 358
 359         priv->is_a2xx = config.rev.core == 2;
 360
 361         gpu = info->init(drm);
 362         if (IS_ERR(gpu)) {
 363                 dev_warn(drm->dev, "failed to load adreno gpu\n");
 364                 return PTR_ERR(gpu);
 365         }
 366
 367         dev_set_drvdata(dev, gpu);
 368
 369         return 0;
 370 }
 371
 372 static void adreno_unbind(struct device *dev, struct device *master,
 373                 void *data)
 374 {
 375         struct msm_gpu *gpu = dev_get_drvdata(dev);
 376
 377         pm_runtime_force_suspend(dev);
 378         gpu->funcs->destroy(gpu);
 379
 380         set_gpu_pdev(dev_get_drvdata(master), NULL);
 381 }
 382
 383 static const struct component_ops a3xx_ops = {
 384                 .bind   = adreno_bind,
 385                 .unbind = adreno_unbind,
 386 };
 387
 388 static void adreno_device_register_headless(void)
 389 {
 390         /* on imx5, we don't have a top-level mdp/dpu node
 391          * this creates a dummy node for the driver for that case
 392          */
 393         struct platform_device_info dummy_info = {
 394                 .parent = NULL,
 395                 .name = "msm",
 396                 .id = -1,
 397                 .res = NULL,
 398                 .num_res = 0,
 399                 .data = NULL,
 400                 .size_data = 0,
 401                 .dma_mask = ~0,
 402         };
 403         platform_device_register_full(&dummy_info);
 404 }
 405
 406 static int adreno_probe(struct platform_device *pdev)
 407 {
 408
 409         int ret;
 410
 411         ret = component_add(&pdev->dev, &a3xx_ops);
 412         if (ret)
 413                 return ret;
 414
 415         if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
 416                 adreno_device_register_headless();
 417
 418         return 0;
 419 }
 420
 421 static int adreno_remove(struct platform_device *pdev)
 422 {
 423         component_del(&pdev->dev, &a3xx_ops);
 424         return 0;
 425 }
 426
 427 static const struct of_device_id dt_match[] = {
 428         { .compatible = "qcom,adreno" },
 429         { .compatible = "qcom,adreno-3xx" },
 430         /* for compatibility with imx5 gpu: */
 431         { .compatible = "amd,imageon" },
 432         /* for backwards compat w/ downstream kgsl DT files: */
 433         { .compatible = "qcom,kgsl-3d0" },
 434         {}
 435 };
 436
 437 #ifdef CONFIG_PM
 438 static int adreno_resume(struct device *dev)
 439 {
 440         struct platform_device *pdev = to_platform_device(dev);
 441         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 442
 443         return gpu->funcs->pm_resume(gpu);
 444 }
 445
 446 static int adreno_suspend(struct device *dev)
 447 {
 448         struct platform_device *pdev = to_platform_device(dev);
 449         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 450
 451         return gpu->funcs->pm_suspend(gpu);
 452 }
 453 #endif
 454
 455 static const struct dev_pm_ops adreno_pm_ops = {
 456         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
 457         SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
 458 };
 459
 460 static struct platform_driver adreno_driver = {
 461         .probe = adreno_probe,
 462         .remove = adreno_remove,
 463         .driver = {
 464                 .name = "adreno",
 465                 .of_match_table = dt_match,
 466                 .pm = &adreno_pm_ops,
 467         },
 468 };
 469
 470 void __init adreno_register(void)
 471 {
 472         platform_driver_register(&adreno_driver);
 473 }
 474
 475 void __exit adreno_unregister(void)
 476 {
 477         platform_driver_unregister(&adreno_driver);
 478 }