drivers/gpu/drm/msm/adreno/adreno_gpu.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/ascii85.h>
  21 #include <linux/interconnect.h>
  22 #include <linux/kernel.h>
  23 #include <linux/pm_opp.h>
  24 #include <linux/slab.h>
  25 #include "adreno_gpu.h"
  26 #include "msm_gem.h"
  27 #include "msm_mmu.h"
  28
  29 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
  30 {
  31         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
  32
  33         switch (param) {
  34         case MSM_PARAM_GPU_ID:
  35                 *value = adreno_gpu->info->revn;
  36                 return 0;
  37         case MSM_PARAM_GMEM_SIZE:
  38                 *value = adreno_gpu->gmem;
  39                 return 0;
  40         case MSM_PARAM_GMEM_BASE:
  41                 *value = 0x100000;
  42                 return 0;
  43         case MSM_PARAM_CHIP_ID:
  44                 *value = adreno_gpu->rev.patchid |
  45                                 (adreno_gpu->rev.minor << 8) |
  46                                 (adreno_gpu->rev.major << 16) |
  47                                 (adreno_gpu->rev.core << 24);
  48                 return 0;
  49         case MSM_PARAM_MAX_FREQ:
  50                 *value = adreno_gpu->base.fast_rate;
  51                 return 0;
  52         case MSM_PARAM_TIMESTAMP:
  53                 if (adreno_gpu->funcs->get_timestamp) {
  54                         int ret;
  55
  56                         pm_runtime_get_sync(&gpu->pdev->dev);
  57                         ret = adreno_gpu->funcs->get_timestamp(gpu, value);
  58                         pm_runtime_put_autosuspend(&gpu->pdev->dev);
  59
  60                         return ret;
  61                 }
  62                 return -EINVAL;
  63         case MSM_PARAM_NR_RINGS:
  64                 *value = gpu->nr_rings;
  65                 return 0;
  66         case MSM_PARAM_PP_PGTABLE:
  67                 *value = 0;
  68                 return 0;
  69         case MSM_PARAM_FAULTS:
  70                 *value = gpu->global_faults;
  71                 return 0;
  72         default:
  73                 DBG("%s: invalid param: %u", gpu->name, param);
  74                 return -EINVAL;
  75         }
  76 }
  77
  78 const struct firmware *
  79 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
  80 {
  81         struct drm_device *drm = adreno_gpu->base.dev;
  82         const struct firmware *fw = NULL;
  83         char *newname;
  84         int ret;
  85
  86         newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
  87         if (!newname)
  88                 return ERR_PTR(-ENOMEM);
  89
  90         /*
  91          * Try first to load from qcom/$fwfile using a direct load (to avoid
  92          * a potential timeout waiting for usermode helper)
  93          */
  94         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
  95             (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
  96
  97                 ret = request_firmware_direct(&fw, newname, drm->dev);
  98                 if (!ret) {
  99                         DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
 100                                 newname);
 101                         adreno_gpu->fwloc = FW_LOCATION_NEW;
 102                         goto out;
 103                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 104                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 105                                 newname, ret);
 106                         fw = ERR_PTR(ret);
 107                         goto out;
 108                 }
 109         }
 110
 111         /*
 112          * Then try the legacy location without qcom/ prefix
 113          */
 114         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 115             (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
 116
 117                 ret = request_firmware_direct(&fw, fwname, drm->dev);
 118                 if (!ret) {
 119                         DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
 120                                 newname);
 121                         adreno_gpu->fwloc = FW_LOCATION_LEGACY;
 122                         goto out;
 123                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 124                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 125                                 fwname, ret);
 126                         fw = ERR_PTR(ret);
 127                         goto out;
 128                 }
 129         }
 130
 131         /*
 132          * Finally fall back to request_firmware() for cases where the
 133          * usermode helper is needed (I think mainly android)
 134          */
 135         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 136             (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
 137
 138                 ret = request_firmware(&fw, newname, drm->dev);
 139                 if (!ret) {
 140                         DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
 141                                 newname);
 142                         adreno_gpu->fwloc = FW_LOCATION_HELPER;
 143                         goto out;
 144                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 145                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 146                                 newname, ret);
 147                         fw = ERR_PTR(ret);
 148                         goto out;
 149                 }
 150         }
 151
 152         DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
 153         fw = ERR_PTR(-ENOENT);
 154 out:
 155         kfree(newname);
 156         return fw;
 157 }
 158
 159 int adreno_load_fw(struct adreno_gpu *adreno_gpu)
 160 {
 161         int i;
 162
 163         for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
 164                 const struct firmware *fw;
 165
 166                 if (!adreno_gpu->info->fw[i])
 167                         continue;
 168
 169                 /* Skip if the firmware has already been loaded */
 170                 if (adreno_gpu->fw[i])
 171                         continue;
 172
 173                 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
 174                 if (IS_ERR(fw))
 175                         return PTR_ERR(fw);
 176
 177                 adreno_gpu->fw[i] = fw;
 178         }
 179
 180         return 0;
 181 }
 182
 183 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
 184                 const struct firmware *fw, u64 *iova)
 185 {
 186         struct drm_gem_object *bo;
 187         void *ptr;
 188
 189         ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,
 190                 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
 191
 192         if (IS_ERR(ptr))
 193                 return ERR_CAST(ptr);
 194
 195         memcpy(ptr, &fw->data[4], fw->size - 4);
 196
 197         msm_gem_put_vaddr(bo);
 198
 199         return bo;
 200 }
 201
 202 int adreno_hw_init(struct msm_gpu *gpu)
 203 {
 204         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 205         int ret, i;
 206
 207         DBG("%s", gpu->name);
 208
 209         ret = adreno_load_fw(adreno_gpu);
 210         if (ret)
 211                 return ret;
 212
 213         for (i = 0; i < gpu->nr_rings; i++) {
 214                 struct msm_ringbuffer *ring = gpu->rb[i];
 215
 216                 if (!ring)
 217                         continue;
 218
 219                 ring->cur = ring->start;
 220                 ring->next = ring->start;
 221
 222                 /* reset completed fence seqno: */
 223                 ring->memptrs->fence = ring->seqno;
 224                 ring->memptrs->rptr = 0;
 225         }
 226
 227         /*
 228          * Setup REG_CP_RB_CNTL.  The same value is used across targets (with
 229          * the excpetion of A430 that disables the RPTR shadow) - the cacluation
 230          * for the ringbuffer size and block size is moved to msm_gpu.h for the
 231          * pre-processor to deal with and the A430 variant is ORed in here
 232          */
 233         adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
 234                 MSM_GPU_RB_CNTL_DEFAULT |
 235                 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
 236
 237         /* Setup ringbuffer address - use ringbuffer[0] for GPU init */
 238         adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
 239                 REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);
 240
 241         if (!adreno_is_a430(adreno_gpu)) {
 242                 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
 243                         REG_ADRENO_CP_RB_RPTR_ADDR_HI,
 244                         rbmemptr(gpu->rb[0], rptr));
 245         }
 246
 247         return 0;
 248 }
 249
 250 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
 251 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
 252                 struct msm_ringbuffer *ring)
 253 {
 254         if (adreno_is_a430(adreno_gpu))
 255                 return ring->memptrs->rptr = adreno_gpu_read(
 256                         adreno_gpu, REG_ADRENO_CP_RB_RPTR);
 257         else
 258                 return ring->memptrs->rptr;
 259 }
 260
 261 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
 262 {
 263         return gpu->rb[0];
 264 }
 265
 266 void adreno_recover(struct msm_gpu *gpu)
 267 {
 268         struct drm_device *dev = gpu->dev;
 269         int ret;
 270
 271         // XXX pm-runtime??  we *need* the device to be off after this
 272         // so maybe continuing to call ->pm_suspend/resume() is better?
 273
 274         gpu->funcs->pm_suspend(gpu);
 275         gpu->funcs->pm_resume(gpu);
 276
 277         ret = msm_gpu_hw_init(gpu);
 278         if (ret) {
 279                 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
 280                 /* hmm, oh well? */
 281         }
 282 }
 283
 284 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 285                 struct msm_file_private *ctx)
 286 {
 287         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 288         struct msm_drm_private *priv = gpu->dev->dev_private;
 289         struct msm_ringbuffer *ring = submit->ring;
 290         unsigned i;
 291
 292         for (i = 0; i < submit->nr_cmds; i++) {
 293                 switch (submit->cmd[i].type) {
 294                 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
 295                         /* ignore IB-targets */
 296                         break;
 297                 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
 298                         /* ignore if there has not been a ctx switch: */
 299                         if (priv->lastctx == ctx)
 300                                 break;
 301                 case MSM_SUBMIT_CMD_BUF:
 302                         OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
 303                                 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 304                         OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
 305                         OUT_RING(ring, submit->cmd[i].size);
 306                         OUT_PKT2(ring);
 307                         break;
 308                 }
 309         }
 310
 311         OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
 312         OUT_RING(ring, submit->seqno);
 313
 314         if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
 315                 /* Flush HLSQ lazy updates to make sure there is nothing
 316                  * pending for indirect loads after the timestamp has
 317                  * passed:
 318                  */
 319                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 320                 OUT_RING(ring, HLSQ_FLUSH);
 321         }
 322
 323         /* wait for idle before cache flush/interrupt */
 324         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 325         OUT_RING(ring, 0x00000000);
 326
 327         if (!adreno_is_a2xx(adreno_gpu)) {
 328                 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
 329                 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
 330                 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
 331                 OUT_RING(ring, rbmemptr(ring, fence));
 332                 OUT_RING(ring, submit->seqno);
 333         } else {
 334                 /* BIT(31) means something else on a2xx */
 335                 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
 336                 OUT_RING(ring, CACHE_FLUSH_TS);
 337                 OUT_RING(ring, rbmemptr(ring, fence));
 338                 OUT_RING(ring, submit->seqno);
 339                 OUT_PKT3(ring, CP_INTERRUPT, 1);
 340                 OUT_RING(ring, 0x80000000);
 341         }
 342
 343 #if 0
 344         if (adreno_is_a3xx(adreno_gpu)) {
 345                 /* Dummy set-constant to trigger context rollover */
 346                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 347                 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
 348                 OUT_RING(ring, 0x00000000);
 349         }
 350 #endif
 351
 352         gpu->funcs->flush(gpu, ring);
 353 }
 354
 355 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 356 {
 357         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 358         uint32_t wptr;
 359
 360         /* Copy the shadow to the actual register */
 361         ring->cur = ring->next;
 362
 363         /*
 364          * Mask wptr value that we calculate to fit in the HW range. This is
 365          * to account for the possibility that the last command fit exactly into
 366          * the ringbuffer and rb->next hasn't wrapped to zero yet
 367          */
 368         wptr = get_wptr(ring);
 369
 370         /* ensure writes to ringbuffer have hit system memory: */
 371         mb();
 372
 373         adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
 374 }
 375
 376 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 377 {
 378         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 379         uint32_t wptr = get_wptr(ring);
 380
 381         /* wait for CP to drain ringbuffer: */
 382         if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
 383                 return true;
 384
 385         /* TODO maybe we need to reset GPU here to recover from hang? */
 386         DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
 387                 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
 388
 389         return false;
 390 }
 391
 392 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
 393 {
 394         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 395         int i, count = 0;
 396
 397         kref_init(&state->ref);
 398
 399         ktime_get_real_ts64(&state->time);
 400
 401         for (i = 0; i < gpu->nr_rings; i++) {
 402                 int size = 0, j;
 403
 404                 state->ring[i].fence = gpu->rb[i]->memptrs->fence;
 405                 state->ring[i].iova = gpu->rb[i]->iova;
 406                 state->ring[i].seqno = gpu->rb[i]->seqno;
 407                 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
 408                 state->ring[i].wptr = get_wptr(gpu->rb[i]);
 409
 410                 /* Copy at least 'wptr' dwords of the data */
 411                 size = state->ring[i].wptr;
 412
 413                 /* After wptr find the last non zero dword to save space */
 414                 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
 415                         if (gpu->rb[i]->start[j])
 416                                 size = j + 1;
 417
 418                 if (size) {
 419                         state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL);
 420                         if (state->ring[i].data) {
 421                                 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
 422                                 state->ring[i].data_size = size << 2;
 423                         }
 424                 }
 425         }
 426
 427         /* Some targets prefer to collect their own registers */
 428         if (!adreno_gpu->registers)
 429                 return 0;
 430
 431         /* Count the number of registers */
 432         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
 433                 count += adreno_gpu->registers[i + 1] -
 434                         adreno_gpu->registers[i] + 1;
 435
 436         state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
 437         if (state->registers) {
 438                 int pos = 0;
 439
 440                 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 441                         u32 start = adreno_gpu->registers[i];
 442                         u32 end   = adreno_gpu->registers[i + 1];
 443                         u32 addr;
 444
 445                         for (addr = start; addr <= end; addr++) {
 446                                 state->registers[pos++] = addr;
 447                                 state->registers[pos++] = gpu_read(gpu, addr);
 448                         }
 449                 }
 450
 451                 state->nr_registers = count;
 452         }
 453
 454         return 0;
 455 }
 456
 457 void adreno_gpu_state_destroy(struct msm_gpu_state *state)
 458 {
 459         int i;
 460
 461         for (i = 0; i < ARRAY_SIZE(state->ring); i++)
 462                 kvfree(state->ring[i].data);
 463
 464         for (i = 0; state->bos && i < state->nr_bos; i++)
 465                 kvfree(state->bos[i].data);
 466
 467         kfree(state->bos);
 468         kfree(state->comm);
 469         kfree(state->cmd);
 470         kfree(state->registers);
 471 }
 472
 473 static void adreno_gpu_state_kref_destroy(struct kref *kref)
 474 {
 475         struct msm_gpu_state *state = container_of(kref,
 476                 struct msm_gpu_state, ref);
 477
 478         adreno_gpu_state_destroy(state);
 479         kfree(state);
 480 }
 481
 482 int adreno_gpu_state_put(struct msm_gpu_state *state)
 483 {
 484         if (IS_ERR_OR_NULL(state))
 485                 return 1;
 486
 487         return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
 488 }
 489
 490 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
 491
 492 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
 493 {
 494         void *buf;
 495         size_t buf_itr = 0, buffer_size;
 496         char out[ASCII85_BUFSZ];
 497         long l;
 498         int i;
 499
 500         if (!src || !len)
 501                 return NULL;
 502
 503         l = ascii85_encode_len(len);
 504
 505         /*
 506          * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
 507          * account for the worst case of 5 bytes per dword plus the 1 for '\0'
 508          */
 509         buffer_size = (l * 5) + 1;
 510
 511         buf = kvmalloc(buffer_size, GFP_KERNEL);
 512         if (!buf)
 513                 return NULL;
 514
 515         for (i = 0; i < l; i++)
 516                 buf_itr += snprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
 517                                 ascii85_encode(src[i], out));
 518
 519         return buf;
 520 }
 521
 522 /* len is expected to be in bytes */
 523 static void adreno_show_object(struct drm_printer *p, void **ptr, int len,
 524                 bool *encoded)
 525 {
 526         if (!*ptr || !len)
 527                 return;
 528
 529         if (!*encoded) {
 530                 long datalen, i;
 531                 u32 *buf = *ptr;
 532
 533                 /*
 534                  * Only dump the non-zero part of the buffer - rarely will
 535                  * any data completely fill the entire allocated size of
 536                  * the buffer.
 537                  */
 538                 for (datalen = 0, i = 0; i < len >> 2; i++)
 539                         if (buf[i])
 540                                 datalen = ((i + 1) << 2);
 541
 542                 /*
 543                  * If we reach here, then the originally captured binary buffer
 544                  * will be replaced with the ascii85 encoded string
 545                  */
 546                 *ptr = adreno_gpu_ascii85_encode(buf, datalen);
 547
 548                 kvfree(buf);
 549
 550                 *encoded = true;
 551         }
 552
 553         if (!*ptr)
 554                 return;
 555
 556         drm_puts(p, "    data: !!ascii85 |\n");
 557         drm_puts(p, "     ");
 558
 559         drm_puts(p, *ptr);
 560
 561         drm_puts(p, "\n");
 562 }
 563
 564 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
 565                 struct drm_printer *p)
 566 {
 567         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 568         int i;
 569
 570         if (IS_ERR_OR_NULL(state))
 571                 return;
 572
 573         drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
 574                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 575                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 576                         adreno_gpu->rev.patchid);
 577
 578         drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
 579
 580         drm_puts(p, "ringbuffer:\n");
 581
 582         for (i = 0; i < gpu->nr_rings; i++) {
 583                 drm_printf(p, "  - id: %d\n", i);
 584                 drm_printf(p, "    iova: 0x%016llx\n", state->ring[i].iova);
 585                 drm_printf(p, "    last-fence: %d\n", state->ring[i].seqno);
 586                 drm_printf(p, "    retired-fence: %d\n", state->ring[i].fence);
 587                 drm_printf(p, "    rptr: %d\n", state->ring[i].rptr);
 588                 drm_printf(p, "    wptr: %d\n", state->ring[i].wptr);
 589                 drm_printf(p, "    size: %d\n", MSM_GPU_RINGBUFFER_SZ);
 590
 591                 adreno_show_object(p, &state->ring[i].data,
 592                         state->ring[i].data_size, &state->ring[i].encoded);
 593         }
 594
 595         if (state->bos) {
 596                 drm_puts(p, "bos:\n");
 597
 598                 for (i = 0; i < state->nr_bos; i++) {
 599                         drm_printf(p, "  - iova: 0x%016llx\n",
 600                                 state->bos[i].iova);
 601                         drm_printf(p, "    size: %zd\n", state->bos[i].size);
 602
 603                         adreno_show_object(p, &state->bos[i].data,
 604                                 state->bos[i].size, &state->bos[i].encoded);
 605                 }
 606         }
 607
 608         if (state->nr_registers) {
 609                 drm_puts(p, "registers:\n");
 610
 611                 for (i = 0; i < state->nr_registers; i++) {
 612                         drm_printf(p, "  - { offset: 0x%04x, value: 0x%08x }\n",
 613                                 state->registers[i * 2] << 2,
 614                                 state->registers[(i * 2) + 1]);
 615                 }
 616         }
 617 }
 618 #endif
 619
 620 /* Dump common gpu status and scratch registers on any hang, to make
 621  * the hangcheck logs more useful.  The scratch registers seem always
 622  * safe to read when GPU has hung (unlike some other regs, depending
 623  * on how the GPU hung), and they are useful to match up to cmdstream
 624  * dumps when debugging hangs:
 625  */
 626 void adreno_dump_info(struct msm_gpu *gpu)
 627 {
 628         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 629         int i;
 630
 631         printk("revision: %d (%d.%d.%d.%d)\n",
 632                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 633                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 634                         adreno_gpu->rev.patchid);
 635
 636         for (i = 0; i < gpu->nr_rings; i++) {
 637                 struct msm_ringbuffer *ring = gpu->rb[i];
 638
 639                 printk("rb %d: fence:    %d/%d\n", i,
 640                         ring->memptrs->fence,
 641                         ring->seqno);
 642
 643                 printk("rptr:     %d\n", get_rptr(adreno_gpu, ring));
 644                 printk("rb wptr:  %d\n", get_wptr(ring));
 645         }
 646 }
 647
 648 /* would be nice to not have to duplicate the _show() stuff with printk(): */
 649 void adreno_dump(struct msm_gpu *gpu)
 650 {
 651         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 652         int i;
 653
 654         if (!adreno_gpu->registers)
 655                 return;
 656
 657         /* dump these out in a form that can be parsed by demsm: */
 658         printk("IO:region %s 00000000 00020000\n", gpu->name);
 659         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 660                 uint32_t start = adreno_gpu->registers[i];
 661                 uint32_t end   = adreno_gpu->registers[i+1];
 662                 uint32_t addr;
 663
 664                 for (addr = start; addr <= end; addr++) {
 665                         uint32_t val = gpu_read(gpu, addr);
 666                         printk("IO:R %08x %08x\n", addr<<2, val);
 667                 }
 668         }
 669 }
 670
 671 static uint32_t ring_freewords(struct msm_ringbuffer *ring)
 672 {
 673         struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
 674         uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
 675         /* Use ring->next to calculate free size */
 676         uint32_t wptr = ring->next - ring->start;
 677         uint32_t rptr = get_rptr(adreno_gpu, ring);
 678         return (rptr + (size - 1) - wptr) % size;
 679 }
 680
 681 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
 682 {
 683         if (spin_until(ring_freewords(ring) >= ndwords))
 684                 DRM_DEV_ERROR(ring->gpu->dev->dev,
 685                         "timeout waiting for space in ringbuffer %d\n",
 686                         ring->id);
 687 }
 688
 689 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
 690 static int adreno_get_legacy_pwrlevels(struct device *dev)
 691 {
 692         struct device_node *child, *node;
 693         int ret;
 694
 695         node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
 696         if (!node) {
 697                 DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n");
 698                 return -ENXIO;
 699         }
 700
 701         for_each_child_of_node(node, child) {
 702                 unsigned int val;
 703
 704                 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
 705                 if (ret)
 706                         continue;
 707
 708                 /*
 709                  * Skip the intentionally bogus clock value found at the bottom
 710                  * of most legacy frequency tables
 711                  */
 712                 if (val != 27000000)
 713                         dev_pm_opp_add(dev, val, 0);
 714         }
 715
 716         of_node_put(node);
 717
 718         return 0;
 719 }
 720
 721 static int adreno_get_pwrlevels(struct device *dev,
 722                 struct msm_gpu *gpu)
 723 {
 724         unsigned long freq = ULONG_MAX;
 725         struct dev_pm_opp *opp;
 726         int ret;
 727
 728         gpu->fast_rate = 0;
 729
 730         /* You down with OPP? */
 731         if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
 732                 ret = adreno_get_legacy_pwrlevels(dev);
 733         else {
 734                 ret = dev_pm_opp_of_add_table(dev);
 735                 if (ret)
 736                         DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
 737         }
 738
 739         if (!ret) {
 740                 /* Find the fastest defined rate */
 741                 opp = dev_pm_opp_find_freq_floor(dev, &freq);
 742                 if (!IS_ERR(opp)) {
 743                         gpu->fast_rate = freq;
 744                         dev_pm_opp_put(opp);
 745                 }
 746         }
 747
 748         if (!gpu->fast_rate) {
 749                 dev_warn(dev,
 750                         "Could not find a clock rate. Using a reasonable default\n");
 751                 /* Pick a suitably safe clock speed for any target */
 752                 gpu->fast_rate = 200000000;
 753         }
 754
 755         DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
 756
 757         /* Check for an interconnect path for the bus */
 758         gpu->icc_path = of_icc_get(dev, NULL);
 759         if (IS_ERR(gpu->icc_path))
 760                 gpu->icc_path = NULL;
 761
 762         return 0;
 763 }
 764
 765 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 766                 struct adreno_gpu *adreno_gpu,
 767                 const struct adreno_gpu_funcs *funcs, int nr_rings)
 768 {
 769         struct adreno_platform_config *config = pdev->dev.platform_data;
 770         struct msm_gpu_config adreno_gpu_config  = { 0 };
 771         struct msm_gpu *gpu = &adreno_gpu->base;
 772
 773         adreno_gpu->funcs = funcs;
 774         adreno_gpu->info = adreno_info(config->rev);
 775         adreno_gpu->gmem = adreno_gpu->info->gmem;
 776         adreno_gpu->revn = adreno_gpu->info->revn;
 777         adreno_gpu->rev = config->rev;
 778
 779         adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
 780
 781         adreno_gpu_config.va_start = SZ_16M;
 782         adreno_gpu_config.va_end = 0xffffffff;
 783         /* maximum range of a2xx mmu */
 784         if (adreno_is_a2xx(adreno_gpu))
 785                 adreno_gpu_config.va_end = SZ_16M + 0xfff * SZ_64K;
 786
 787         adreno_gpu_config.nr_rings = nr_rings;
 788
 789         adreno_get_pwrlevels(&pdev->dev, gpu);
 790
 791         pm_runtime_set_autosuspend_delay(&pdev->dev,
 792                 adreno_gpu->info->inactive_period);
 793         pm_runtime_use_autosuspend(&pdev->dev);
 794         pm_runtime_enable(&pdev->dev);
 795
 796         return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
 797                         adreno_gpu->info->name, &adreno_gpu_config);
 798 }
 799
 800 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
 801 {
 802         struct msm_gpu *gpu = &adreno_gpu->base;
 803         unsigned int i;
 804
 805         for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
 806                 release_firmware(adreno_gpu->fw[i]);
 807
 808         icc_put(gpu->icc_path);
 809
 810         msm_gpu_cleanup(&adreno_gpu->base);
 811 }