2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "adreno_gpu.h"
24 #define RB_SIZE SZ_32K
27 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
29 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
32 case MSM_PARAM_GPU_ID:
33 *value = adreno_gpu->info->revn;
35 case MSM_PARAM_GMEM_SIZE:
36 *value = adreno_gpu->gmem;
38 case MSM_PARAM_GMEM_BASE:
41 case MSM_PARAM_CHIP_ID:
42 *value = adreno_gpu->rev.patchid |
43 (adreno_gpu->rev.minor << 8) |
44 (adreno_gpu->rev.major << 16) |
45 (adreno_gpu->rev.core << 24);
47 case MSM_PARAM_MAX_FREQ:
48 *value = adreno_gpu->base.fast_rate;
50 case MSM_PARAM_TIMESTAMP:
51 if (adreno_gpu->funcs->get_timestamp) {
54 pm_runtime_get_sync(&gpu->pdev->dev);
55 ret = adreno_gpu->funcs->get_timestamp(gpu, value);
56 pm_runtime_put_autosuspend(&gpu->pdev->dev);
62 DBG("%s: invalid param: %u", gpu->name, param);
67 static int adreno_load_fw(struct adreno_gpu *adreno_gpu)
69 struct drm_device *drm = adreno_gpu->base.dev;
75 ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
77 dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
78 adreno_gpu->info->pm4fw, ret);
82 ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
84 dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
85 adreno_gpu->info->pfpfw, ret);
86 release_firmware(adreno_gpu->pm4);
87 adreno_gpu->pm4 = NULL;
94 int adreno_hw_init(struct msm_gpu *gpu)
96 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
101 ret = adreno_load_fw(adreno_gpu);
105 ret = msm_gem_get_iova(gpu->rb->bo, gpu->aspace, &gpu->rb_iova);
108 dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
112 /* reset ringbuffer: */
113 gpu->rb->cur = gpu->rb->start;
115 /* reset completed fence seqno: */
116 adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
117 adreno_gpu->memptrs->rptr = 0;
119 /* Setup REG_CP_RB_CNTL: */
120 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
121 /* size is log2(quad-words): */
122 AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
123 AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
124 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
126 /* Setup ringbuffer address: */
127 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
128 REG_ADRENO_CP_RB_BASE_HI, gpu->rb_iova);
130 if (!adreno_is_a430(adreno_gpu)) {
131 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
132 REG_ADRENO_CP_RB_RPTR_ADDR_HI,
133 rbmemptr(adreno_gpu, rptr));
139 static uint32_t get_wptr(struct msm_ringbuffer *ring)
141 return ring->cur - ring->start;
144 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
145 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
147 if (adreno_is_a430(adreno_gpu))
148 return adreno_gpu->memptrs->rptr = adreno_gpu_read(
149 adreno_gpu, REG_ADRENO_CP_RB_RPTR);
151 return adreno_gpu->memptrs->rptr;
154 uint32_t adreno_last_fence(struct msm_gpu *gpu)
156 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
157 return adreno_gpu->memptrs->fence;
160 void adreno_recover(struct msm_gpu *gpu)
162 struct drm_device *dev = gpu->dev;
165 // XXX pm-runtime?? we *need* the device to be off after this
166 // so maybe continuing to call ->pm_suspend/resume() is better?
168 gpu->funcs->pm_suspend(gpu);
169 gpu->funcs->pm_resume(gpu);
171 ret = msm_gpu_hw_init(gpu);
173 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
178 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
179 struct msm_file_private *ctx)
181 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
182 struct msm_drm_private *priv = gpu->dev->dev_private;
183 struct msm_ringbuffer *ring = gpu->rb;
186 for (i = 0; i < submit->nr_cmds; i++) {
187 switch (submit->cmd[i].type) {
188 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
189 /* ignore IB-targets */
191 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
192 /* ignore if there has not been a ctx switch: */
193 if (priv->lastctx == ctx)
195 case MSM_SUBMIT_CMD_BUF:
196 OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
197 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
198 OUT_RING(ring, submit->cmd[i].iova);
199 OUT_RING(ring, submit->cmd[i].size);
205 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
206 OUT_RING(ring, submit->fence->seqno);
208 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
209 /* Flush HLSQ lazy updates to make sure there is nothing
210 * pending for indirect loads after the timestamp has
213 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
214 OUT_RING(ring, HLSQ_FLUSH);
216 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
217 OUT_RING(ring, 0x00000000);
220 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
221 OUT_RING(ring, CACHE_FLUSH_TS);
222 OUT_RING(ring, rbmemptr(adreno_gpu, fence));
223 OUT_RING(ring, submit->fence->seqno);
225 /* we could maybe be clever and only CP_COND_EXEC the interrupt: */
226 OUT_PKT3(ring, CP_INTERRUPT, 1);
227 OUT_RING(ring, 0x80000000);
229 /* Workaround for missing irq issue on 8x16/a306. Unsure if the
230 * root cause is a platform issue or some a306 quirk, but this
231 * keeps things humming along:
233 if (adreno_is_a306(adreno_gpu)) {
234 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
235 OUT_RING(ring, 0x00000000);
236 OUT_PKT3(ring, CP_INTERRUPT, 1);
237 OUT_RING(ring, 0x80000000);
241 if (adreno_is_a3xx(adreno_gpu)) {
242 /* Dummy set-constant to trigger context rollover */
243 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
244 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
245 OUT_RING(ring, 0x00000000);
249 gpu->funcs->flush(gpu);
252 void adreno_flush(struct msm_gpu *gpu)
254 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
258 * Mask wptr value that we calculate to fit in the HW range. This is
259 * to account for the possibility that the last command fit exactly into
260 * the ringbuffer and rb->next hasn't wrapped to zero yet
262 wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1);
264 /* ensure writes to ringbuffer have hit system memory: */
267 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
270 bool adreno_idle(struct msm_gpu *gpu)
272 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
273 uint32_t wptr = get_wptr(gpu->rb);
275 /* wait for CP to drain ringbuffer: */
276 if (!spin_until(get_rptr(adreno_gpu) == wptr))
279 /* TODO maybe we need to reset GPU here to recover from hang? */
280 DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
284 #ifdef CONFIG_DEBUG_FS
285 void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
287 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
290 seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
291 adreno_gpu->info->revn, adreno_gpu->rev.core,
292 adreno_gpu->rev.major, adreno_gpu->rev.minor,
293 adreno_gpu->rev.patchid);
295 seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence,
296 gpu->fctx->last_fence);
297 seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
298 seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
300 /* dump these out in a form that can be parsed by demsm: */
301 seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
302 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
303 uint32_t start = adreno_gpu->registers[i];
304 uint32_t end = adreno_gpu->registers[i+1];
307 for (addr = start; addr <= end; addr++) {
308 uint32_t val = gpu_read(gpu, addr);
309 seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
315 /* Dump common gpu status and scratch registers on any hang, to make
316 * the hangcheck logs more useful. The scratch registers seem always
317 * safe to read when GPU has hung (unlike some other regs, depending
318 * on how the GPU hung), and they are useful to match up to cmdstream
319 * dumps when debugging hangs:
321 void adreno_dump_info(struct msm_gpu *gpu)
323 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
325 printk("revision: %d (%d.%d.%d.%d)\n",
326 adreno_gpu->info->revn, adreno_gpu->rev.core,
327 adreno_gpu->rev.major, adreno_gpu->rev.minor,
328 adreno_gpu->rev.patchid);
330 printk("fence: %d/%d\n", adreno_gpu->memptrs->fence,
331 gpu->fctx->last_fence);
332 printk("rptr: %d\n", get_rptr(adreno_gpu));
333 printk("rb wptr: %d\n", get_wptr(gpu->rb));
336 /* would be nice to not have to duplicate the _show() stuff with printk(): */
337 void adreno_dump(struct msm_gpu *gpu)
339 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
342 /* dump these out in a form that can be parsed by demsm: */
343 printk("IO:region %s 00000000 00020000\n", gpu->name);
344 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
345 uint32_t start = adreno_gpu->registers[i];
346 uint32_t end = adreno_gpu->registers[i+1];
349 for (addr = start; addr <= end; addr++) {
350 uint32_t val = gpu_read(gpu, addr);
351 printk("IO:R %08x %08x\n", addr<<2, val);
356 static uint32_t ring_freewords(struct msm_gpu *gpu)
358 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
359 uint32_t size = gpu->rb->size / 4;
360 uint32_t wptr = get_wptr(gpu->rb);
361 uint32_t rptr = get_rptr(adreno_gpu);
362 return (rptr + (size - 1) - wptr) % size;
365 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
367 if (spin_until(ring_freewords(gpu) >= ndwords))
368 DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
371 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
372 struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
374 struct adreno_platform_config *config = pdev->dev.platform_data;
375 struct msm_gpu_config adreno_gpu_config = { 0 };
376 struct msm_gpu *gpu = &adreno_gpu->base;
379 adreno_gpu->funcs = funcs;
380 adreno_gpu->info = adreno_info(config->rev);
381 adreno_gpu->gmem = adreno_gpu->info->gmem;
382 adreno_gpu->revn = adreno_gpu->info->revn;
383 adreno_gpu->rev = config->rev;
385 gpu->fast_rate = config->fast_rate;
386 gpu->bus_freq = config->bus_freq;
387 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
388 gpu->bus_scale_table = config->bus_scale_table;
391 DBG("fast_rate=%u, slow_rate=27000000, bus_freq=%u",
392 gpu->fast_rate, gpu->bus_freq);
394 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
395 adreno_gpu_config.irqname = "kgsl_3d0_irq";
397 adreno_gpu_config.va_start = SZ_16M;
398 adreno_gpu_config.va_end = 0xffffffff;
400 adreno_gpu_config.ringsz = RB_SIZE;
402 pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD);
403 pm_runtime_use_autosuspend(&pdev->dev);
404 pm_runtime_enable(&pdev->dev);
406 ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
407 adreno_gpu->info->name, &adreno_gpu_config);
411 adreno_gpu->memptrs = msm_gem_kernel_new(drm,
412 sizeof(*adreno_gpu->memptrs), MSM_BO_UNCACHED, gpu->aspace,
413 &adreno_gpu->memptrs_bo, &adreno_gpu->memptrs_iova);
415 if (IS_ERR(adreno_gpu->memptrs)) {
416 ret = PTR_ERR(adreno_gpu->memptrs);
417 adreno_gpu->memptrs = NULL;
418 dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
424 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
426 struct msm_gpu *gpu = &adreno_gpu->base;
428 if (adreno_gpu->memptrs_bo) {
429 if (adreno_gpu->memptrs)
430 msm_gem_put_vaddr(adreno_gpu->memptrs_bo);
432 if (adreno_gpu->memptrs_iova)
433 msm_gem_put_iova(adreno_gpu->memptrs_bo, gpu->aspace);
435 drm_gem_object_unreference_unlocked(adreno_gpu->memptrs_bo);
437 release_firmware(adreno_gpu->pm4);
438 release_firmware(adreno_gpu->pfp);
440 msm_gpu_cleanup(gpu);