drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

   1 /*
   2  * SPDX-License-Identifier: GPL-2.0
   3  * Copyright (c) 2018, The Linux Foundation
   4  */
   5
   6 #include <linux/irq.h>
   7 #include <linux/irqchip.h>
   8 #include <linux/irqdesc.h>
   9 #include <linux/irqchip/chained_irq.h>
  10 #include "dpu_kms.h"
  11 #include <linux/interconnect.h>
  12
  13 #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
  14
  15 #define HW_INTR_STATUS                  0x0010
  16
  17 /* Max BW defined in KBps */
  18 #define MAX_BW                          6800000
  19
  20 struct dpu_irq_controller {
  21         unsigned long enabled_mask;
  22         struct irq_domain *domain;
  23 };
  24
  25 struct dpu_mdss {
  26         struct msm_mdss base;
  27         void __iomem *mmio;
  28         unsigned long mmio_len;
  29         struct dss_module_power mp;
  30         struct dpu_irq_controller irq_controller;
  31         struct icc_path *path[2];
  32         u32 num_paths;
  33 };
  34
  35 static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
  36                                                 struct dpu_mdss *dpu_mdss)
  37 {
  38         struct icc_path *path0 = of_icc_get(dev->dev, "mdp0-mem");
  39         struct icc_path *path1 = of_icc_get(dev->dev, "mdp1-mem");
  40
  41         if (IS_ERR_OR_NULL(path0))
  42                 return PTR_ERR_OR_ZERO(path0);
  43
  44         dpu_mdss->path[0] = path0;
  45         dpu_mdss->num_paths = 1;
  46
  47         if (!IS_ERR_OR_NULL(path1)) {
  48                 dpu_mdss->path[1] = path1;
  49                 dpu_mdss->num_paths++;
  50         }
  51
  52         return 0;
  53 }
  54
  55 static void dpu_mdss_icc_request_bw(struct msm_mdss *mdss)
  56 {
  57         struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
  58         int i;
  59         u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0;
  60
  61         for (i = 0; i < dpu_mdss->num_paths; i++)
  62                 icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW));
  63 }
  64
  65 static void dpu_mdss_irq(struct irq_desc *desc)
  66 {
  67         struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc);
  68         struct irq_chip *chip = irq_desc_get_chip(desc);
  69         u32 interrupts;
  70
  71         chained_irq_enter(chip, desc);
  72
  73         interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS);
  74
  75         while (interrupts) {
  76                 irq_hw_number_t hwirq = fls(interrupts) - 1;
  77                 unsigned int mapping;
  78                 int rc;
  79
  80                 mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
  81                                            hwirq);
  82                 if (mapping == 0) {
  83                         DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
  84                         break;
  85                 }
  86
  87                 rc = generic_handle_irq(mapping);
  88                 if (rc < 0) {
  89                         DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
  90                                   hwirq, mapping, rc);
  91                         break;
  92                 }
  93
  94                 interrupts &= ~(1 << hwirq);
  95         }
  96
  97         chained_irq_exit(chip, desc);
  98 }
  99
 100 static void dpu_mdss_irq_mask(struct irq_data *irqd)
 101 {
 102         struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
 103
 104         /* memory barrier */
 105         smp_mb__before_atomic();
 106         clear_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
 107         /* memory barrier */
 108         smp_mb__after_atomic();
 109 }
 110
 111 static void dpu_mdss_irq_unmask(struct irq_data *irqd)
 112 {
 113         struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
 114
 115         /* memory barrier */
 116         smp_mb__before_atomic();
 117         set_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
 118         /* memory barrier */
 119         smp_mb__after_atomic();
 120 }
 121
 122 static struct irq_chip dpu_mdss_irq_chip = {
 123         .name = "dpu_mdss",
 124         .irq_mask = dpu_mdss_irq_mask,
 125         .irq_unmask = dpu_mdss_irq_unmask,
 126 };
 127
 128 static struct lock_class_key dpu_mdss_lock_key, dpu_mdss_request_key;
 129
 130 static int dpu_mdss_irqdomain_map(struct irq_domain *domain,
 131                 unsigned int irq, irq_hw_number_t hwirq)
 132 {
 133         struct dpu_mdss *dpu_mdss = domain->host_data;
 134
 135         irq_set_lockdep_class(irq, &dpu_mdss_lock_key, &dpu_mdss_request_key);
 136         irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
 137         return irq_set_chip_data(irq, dpu_mdss);
 138 }
 139
 140 static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {
 141         .map = dpu_mdss_irqdomain_map,
 142         .xlate = irq_domain_xlate_onecell,
 143 };
 144
 145 static int _dpu_mdss_irq_domain_add(struct dpu_mdss *dpu_mdss)
 146 {
 147         struct device *dev;
 148         struct irq_domain *domain;
 149
 150         dev = dpu_mdss->base.dev->dev;
 151
 152         domain = irq_domain_add_linear(dev->of_node, 32,
 153                         &dpu_mdss_irqdomain_ops, dpu_mdss);
 154         if (!domain) {
 155                 DPU_ERROR("failed to add irq_domain\n");
 156                 return -EINVAL;
 157         }
 158
 159         dpu_mdss->irq_controller.enabled_mask = 0;
 160         dpu_mdss->irq_controller.domain = domain;
 161
 162         return 0;
 163 }
 164
 165 static void _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
 166 {
 167         if (dpu_mdss->irq_controller.domain) {
 168                 irq_domain_remove(dpu_mdss->irq_controller.domain);
 169                 dpu_mdss->irq_controller.domain = NULL;
 170         }
 171 }
 172 static int dpu_mdss_enable(struct msm_mdss *mdss)
 173 {
 174         struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
 175         struct dss_module_power *mp = &dpu_mdss->mp;
 176         int ret;
 177
 178         dpu_mdss_icc_request_bw(mdss);
 179
 180         ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
 181         if (ret)
 182                 DPU_ERROR("clock enable failed, ret:%d\n", ret);
 183
 184         return ret;
 185 }
 186
 187 static int dpu_mdss_disable(struct msm_mdss *mdss)
 188 {
 189         struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
 190         struct dss_module_power *mp = &dpu_mdss->mp;
 191         int ret, i;
 192
 193         ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
 194         if (ret)
 195                 DPU_ERROR("clock disable failed, ret:%d\n", ret);
 196
 197         for (i = 0; i < dpu_mdss->num_paths; i++)
 198                 icc_set_bw(dpu_mdss->path[i], 0, 0);
 199
 200         return ret;
 201 }
 202
 203 static void dpu_mdss_destroy(struct drm_device *dev)
 204 {
 205         struct platform_device *pdev = to_platform_device(dev->dev);
 206         struct msm_drm_private *priv = dev->dev_private;
 207         struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
 208         struct dss_module_power *mp = &dpu_mdss->mp;
 209         int irq;
 210         int i;
 211
 212         pm_runtime_suspend(dev->dev);
 213         pm_runtime_disable(dev->dev);
 214         _dpu_mdss_irq_domain_fini(dpu_mdss);
 215         irq = platform_get_irq(pdev, 0);
 216         irq_set_chained_handler_and_data(irq, NULL, NULL);
 217         msm_dss_put_clk(mp->clk_config, mp->num_clk);
 218         devm_kfree(&pdev->dev, mp->clk_config);
 219
 220         for (i = 0; i < dpu_mdss->num_paths; i++)
 221                 icc_put(dpu_mdss->path[i]);
 222
 223         if (dpu_mdss->mmio)
 224                 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
 225         dpu_mdss->mmio = NULL;
 226         priv->mdss = NULL;
 227 }
 228
 229 static const struct msm_mdss_funcs mdss_funcs = {
 230         .enable = dpu_mdss_enable,
 231         .disable = dpu_mdss_disable,
 232         .destroy = dpu_mdss_destroy,
 233 };
 234
 235 int dpu_mdss_init(struct drm_device *dev)
 236 {
 237         struct platform_device *pdev = to_platform_device(dev->dev);
 238         struct msm_drm_private *priv = dev->dev_private;
 239         struct resource *res;
 240         struct dpu_mdss *dpu_mdss;
 241         struct dss_module_power *mp;
 242         int ret = 0;
 243         int irq;
 244
 245         dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
 246         if (!dpu_mdss)
 247                 return -ENOMEM;
 248
 249         dpu_mdss->mmio = msm_ioremap(pdev, "mdss", "mdss");
 250         if (IS_ERR(dpu_mdss->mmio))
 251                 return PTR_ERR(dpu_mdss->mmio);
 252
 253         DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
 254
 255         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mdss");
 256         if (!res) {
 257                 DRM_ERROR("failed to get memory resource for mdss\n");
 258                 return -ENOMEM;
 259         }
 260         dpu_mdss->mmio_len = resource_size(res);
 261
 262         ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
 263         if (ret)
 264                 return ret;
 265
 266         mp = &dpu_mdss->mp;
 267         ret = msm_dss_parse_clock(pdev, mp);
 268         if (ret) {
 269                 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
 270                 goto clk_parse_err;
 271         }
 272
 273         dpu_mdss->base.dev = dev;
 274         dpu_mdss->base.funcs = &mdss_funcs;
 275
 276         ret = _dpu_mdss_irq_domain_add(dpu_mdss);
 277         if (ret)
 278                 goto irq_domain_error;
 279
 280         irq = platform_get_irq(pdev, 0);
 281         if (irq < 0)
 282                 goto irq_error;
 283
 284         irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
 285                                          dpu_mdss);
 286
 287         priv->mdss = &dpu_mdss->base;
 288
 289         pm_runtime_enable(dev->dev);
 290
 291         dpu_mdss_icc_request_bw(priv->mdss);
 292
 293         return ret;
 294
 295 irq_error:
 296         _dpu_mdss_irq_domain_fini(dpu_mdss);
 297 irq_domain_error:
 298         msm_dss_put_clk(mp->clk_config, mp->num_clk);
 299 clk_parse_err:
 300         devm_kfree(&pdev->dev, mp->clk_config);
 301         if (dpu_mdss->mmio)
 302                 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
 303         dpu_mdss->mmio = NULL;
 304         return ret;
 305 }