1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/interconnect.h>
9 #include <linux/of_irq.h>
16 static const char *iommu_ports[] = {
20 static int mdp5_hw_init(struct msm_kms *kms)
22 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
23 struct device *dev = &mdp5_kms->pdev->dev;
26 pm_runtime_get_sync(dev);
28 /* Magic unknown register writes:
30 * W VBIF:0x004 00000001 (mdss_mdp.c:839)
31 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
32 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
33 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
34 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
35 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
36 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
37 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
38 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
40 * Downstream fbdev driver gets these register offsets/values
41 * from DT.. not really sure what these registers are or if
42 * different values for different boards/SoC's, etc. I guess
43 * they are the golden registers.
45 * Not setting these does not seem to cause any problem. But
46 * we may be getting lucky with the bootloader initializing
47 * them for us. OTOH, if we can always count on the bootloader
48 * setting the golden registers, then perhaps we don't need to
52 spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
53 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
54 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
56 mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
58 pm_runtime_put_sync(dev);
63 /* Global/shared object state funcs */
66 * This is a helper that returns the private state currently in operation.
67 * Note that this would return the "old_state" if called in the atomic check
68 * path, and the "new_state" after the atomic swap has been done.
70 struct mdp5_global_state *
71 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms)
73 return to_mdp5_global_state(mdp5_kms->glob_state.state);
77 * This acquires the modeset lock set aside for global state, creates
78 * a new duplicated private object state.
80 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s)
82 struct msm_drm_private *priv = s->dev->dev_private;
83 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
84 struct drm_private_state *priv_state;
87 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx);
91 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);
92 if (IS_ERR(priv_state))
93 return ERR_CAST(priv_state);
95 return to_mdp5_global_state(priv_state);
98 static struct drm_private_state *
99 mdp5_global_duplicate_state(struct drm_private_obj *obj)
101 struct mdp5_global_state *state;
103 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
107 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
112 static void mdp5_global_destroy_state(struct drm_private_obj *obj,
113 struct drm_private_state *state)
115 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state);
120 static const struct drm_private_state_funcs mdp5_global_state_funcs = {
121 .atomic_duplicate_state = mdp5_global_duplicate_state,
122 .atomic_destroy_state = mdp5_global_destroy_state,
125 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
127 struct mdp5_global_state *state;
129 drm_modeset_lock_init(&mdp5_kms->glob_state_lock);
131 state = kzalloc(sizeof(*state), GFP_KERNEL);
135 state->mdp5_kms = mdp5_kms;
137 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state,
139 &mdp5_global_state_funcs);
143 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
145 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
146 struct device *dev = &mdp5_kms->pdev->dev;
147 struct mdp5_global_state *global_state;
149 global_state = mdp5_get_existing_global_state(mdp5_kms);
151 pm_runtime_get_sync(dev);
154 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp);
157 static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
160 struct device *dev = &mdp5_kms->pdev->dev;
161 struct mdp5_global_state *global_state;
163 drm_atomic_helper_wait_for_vblanks(mdp5_kms->dev, state);
165 global_state = mdp5_get_existing_global_state(mdp5_kms);
168 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp);
170 pm_runtime_put_sync(dev);
173 static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms,
174 struct drm_crtc *crtc)
176 mdp5_crtc_wait_for_commit_done(crtc);
179 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
180 struct drm_encoder *encoder)
185 static int mdp5_set_split_display(struct msm_kms *kms,
186 struct drm_encoder *encoder,
187 struct drm_encoder *slave_encoder,
191 return mdp5_cmd_encoder_set_split_display(encoder,
194 return mdp5_vid_encoder_set_split_display(encoder,
198 static void mdp5_set_encoder_mode(struct msm_kms *kms,
199 struct drm_encoder *encoder,
202 mdp5_encoder_set_intf_mode(encoder, cmd_mode);
205 static void mdp5_kms_destroy(struct msm_kms *kms)
207 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
208 struct msm_gem_address_space *aspace = kms->aspace;
211 for (i = 0; i < mdp5_kms->num_hwmixers; i++)
212 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]);
214 for (i = 0; i < mdp5_kms->num_hwpipes; i++)
215 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);
218 aspace->mmu->funcs->detach(aspace->mmu,
219 iommu_ports, ARRAY_SIZE(iommu_ports));
220 msm_gem_address_space_put(aspace);
224 #ifdef CONFIG_DEBUG_FS
225 static int smp_show(struct seq_file *m, void *arg)
227 struct drm_info_node *node = (struct drm_info_node *) m->private;
228 struct drm_device *dev = node->minor->dev;
229 struct msm_drm_private *priv = dev->dev_private;
230 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
231 struct drm_printer p = drm_seq_file_printer(m);
233 if (!mdp5_kms->smp) {
234 drm_printf(&p, "no SMP pool\n");
238 mdp5_smp_dump(mdp5_kms->smp, &p);
243 static struct drm_info_list mdp5_debugfs_list[] = {
247 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
249 struct drm_device *dev = minor->dev;
252 ret = drm_debugfs_create_files(mdp5_debugfs_list,
253 ARRAY_SIZE(mdp5_debugfs_list),
254 minor->debugfs_root, minor);
257 DRM_DEV_ERROR(dev->dev, "could not install mdp5_debugfs_list\n");
265 static const struct mdp_kms_funcs kms_funcs = {
267 .hw_init = mdp5_hw_init,
268 .irq_preinstall = mdp5_irq_preinstall,
269 .irq_postinstall = mdp5_irq_postinstall,
270 .irq_uninstall = mdp5_irq_uninstall,
272 .enable_vblank = mdp5_enable_vblank,
273 .disable_vblank = mdp5_disable_vblank,
274 .prepare_commit = mdp5_prepare_commit,
275 .complete_commit = mdp5_complete_commit,
276 .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done,
277 .get_format = mdp_get_format,
278 .round_pixclk = mdp5_round_pixclk,
279 .set_split_display = mdp5_set_split_display,
280 .set_encoder_mode = mdp5_set_encoder_mode,
281 .destroy = mdp5_kms_destroy,
282 #ifdef CONFIG_DEBUG_FS
283 .debugfs_init = mdp5_kms_debugfs_init,
286 .set_irqmask = mdp5_set_irqmask,
289 int mdp5_disable(struct mdp5_kms *mdp5_kms)
293 mdp5_kms->enable_count--;
294 WARN_ON(mdp5_kms->enable_count < 0);
296 clk_disable_unprepare(mdp5_kms->ahb_clk);
297 clk_disable_unprepare(mdp5_kms->axi_clk);
298 clk_disable_unprepare(mdp5_kms->core_clk);
299 if (mdp5_kms->lut_clk)
300 clk_disable_unprepare(mdp5_kms->lut_clk);
305 int mdp5_enable(struct mdp5_kms *mdp5_kms)
309 mdp5_kms->enable_count++;
311 clk_prepare_enable(mdp5_kms->ahb_clk);
312 clk_prepare_enable(mdp5_kms->axi_clk);
313 clk_prepare_enable(mdp5_kms->core_clk);
314 if (mdp5_kms->lut_clk)
315 clk_prepare_enable(mdp5_kms->lut_clk);
320 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
321 struct mdp5_interface *intf,
322 struct mdp5_ctl *ctl)
324 struct drm_device *dev = mdp5_kms->dev;
325 struct msm_drm_private *priv = dev->dev_private;
326 struct drm_encoder *encoder;
328 encoder = mdp5_encoder_init(dev, intf, ctl);
329 if (IS_ERR(encoder)) {
330 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n");
334 priv->encoders[priv->num_encoders++] = encoder;
339 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
341 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
342 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
345 for (i = 0; i < intf_cnt; i++) {
346 if (intfs[i] == INTF_DSI) {
357 static int modeset_init_intf(struct mdp5_kms *mdp5_kms,
358 struct mdp5_interface *intf)
360 struct drm_device *dev = mdp5_kms->dev;
361 struct msm_drm_private *priv = dev->dev_private;
362 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
363 struct mdp5_ctl *ctl;
364 struct drm_encoder *encoder;
367 switch (intf->type) {
372 ctl = mdp5_ctlm_request(ctlm, intf->num);
378 encoder = construct_encoder(mdp5_kms, intf, ctl);
379 if (IS_ERR(encoder)) {
380 ret = PTR_ERR(encoder);
384 ret = msm_edp_modeset_init(priv->edp, dev, encoder);
390 ctl = mdp5_ctlm_request(ctlm, intf->num);
396 encoder = construct_encoder(mdp5_kms, intf, ctl);
397 if (IS_ERR(encoder)) {
398 ret = PTR_ERR(encoder);
402 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
406 const struct mdp5_cfg_hw *hw_cfg =
407 mdp5_cfg_get_hw_config(mdp5_kms->cfg);
408 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num);
410 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {
411 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n",
417 if (!priv->dsi[dsi_id])
420 ctl = mdp5_ctlm_request(ctlm, intf->num);
426 encoder = construct_encoder(mdp5_kms, intf, ctl);
427 if (IS_ERR(encoder)) {
428 ret = PTR_ERR(encoder);
432 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
436 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type);
444 static int modeset_init(struct mdp5_kms *mdp5_kms)
446 struct drm_device *dev = mdp5_kms->dev;
447 struct msm_drm_private *priv = dev->dev_private;
448 const struct mdp5_cfg_hw *hw_cfg;
449 unsigned int num_crtcs;
450 int i, ret, pi = 0, ci = 0;
451 struct drm_plane *primary[MAX_BASES] = { NULL };
452 struct drm_plane *cursor[MAX_BASES] = { NULL };
454 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
457 * Construct encoders and modeset initialize connector devices
458 * for each external display interface.
460 for (i = 0; i < mdp5_kms->num_intfs; i++) {
461 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]);
467 * We should ideally have less number of encoders (set up by parsing
468 * the MDP5 interfaces) than the number of layer mixers present in HW,
469 * but let's be safe here anyway
471 num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers);
474 * Construct planes equaling the number of hw pipes, and CRTCs for the
475 * N encoders set up by the driver. The first N planes become primary
476 * planes for the CRTCs, with the remainder as overlay planes:
478 for (i = 0; i < mdp5_kms->num_hwpipes; i++) {
479 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];
480 struct drm_plane *plane;
481 enum drm_plane_type type;
484 type = DRM_PLANE_TYPE_PRIMARY;
485 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR)
486 type = DRM_PLANE_TYPE_CURSOR;
488 type = DRM_PLANE_TYPE_OVERLAY;
490 plane = mdp5_plane_init(dev, type);
492 ret = PTR_ERR(plane);
493 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret);
496 priv->planes[priv->num_planes++] = plane;
498 if (type == DRM_PLANE_TYPE_PRIMARY)
499 primary[pi++] = plane;
500 if (type == DRM_PLANE_TYPE_CURSOR)
501 cursor[ci++] = plane;
504 for (i = 0; i < num_crtcs; i++) {
505 struct drm_crtc *crtc;
507 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i);
510 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
513 priv->crtcs[priv->num_crtcs++] = crtc;
517 * Now that we know the number of crtcs we've created, set the possible
518 * crtcs for the encoders
520 for (i = 0; i < priv->num_encoders; i++) {
521 struct drm_encoder *encoder = priv->encoders[i];
523 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
532 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,
533 u32 *major, u32 *minor)
535 struct device *dev = &mdp5_kms->pdev->dev;
538 pm_runtime_get_sync(dev);
539 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);
540 pm_runtime_put_sync(dev);
542 *major = FIELD(version, MDP5_HW_VERSION_MAJOR);
543 *minor = FIELD(version, MDP5_HW_VERSION_MINOR);
545 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor);
548 static int get_clk(struct platform_device *pdev, struct clk **clkp,
549 const char *name, bool mandatory)
551 struct device *dev = &pdev->dev;
552 struct clk *clk = msm_clk_get(pdev, name);
553 if (IS_ERR(clk) && mandatory) {
554 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
558 DBG("skipping %s", name);
565 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
567 struct drm_device *dev = crtc->dev;
568 struct drm_encoder *encoder;
570 drm_for_each_encoder(encoder, dev)
571 if (encoder->crtc == crtc)
577 static bool mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe,
578 bool in_vblank_irq, int *vpos, int *hpos,
579 ktime_t *stime, ktime_t *etime,
580 const struct drm_display_mode *mode)
582 struct msm_drm_private *priv = dev->dev_private;
583 struct drm_crtc *crtc;
584 struct drm_encoder *encoder;
585 int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
587 crtc = priv->crtcs[pipe];
589 DRM_ERROR("Invalid crtc %d\n", pipe);
593 encoder = get_encoder_from_crtc(crtc);
595 DRM_ERROR("no encoder found for crtc %d\n", pipe);
599 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
600 vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
603 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
604 * the end of VFP. Translate the porch values relative to the line
608 vactive_start = vsw + vbp + 1;
610 vactive_end = vactive_start + mode->crtc_vdisplay;
612 /* last scan line before VSYNC */
613 vfp_end = mode->crtc_vtotal;
616 *stime = ktime_get();
618 line = mdp5_encoder_get_linecount(encoder);
620 if (line < vactive_start) {
621 line -= vactive_start;
622 } else if (line > vactive_end) {
623 line = line - vfp_end - vactive_start;
625 line -= vactive_start;
632 *etime = ktime_get();
637 static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
639 struct msm_drm_private *priv = dev->dev_private;
640 struct drm_crtc *crtc;
641 struct drm_encoder *encoder;
643 if (pipe >= priv->num_crtcs)
646 crtc = priv->crtcs[pipe];
650 encoder = get_encoder_from_crtc(crtc);
654 return mdp5_encoder_get_framecount(encoder);
657 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
659 struct msm_drm_private *priv = dev->dev_private;
660 struct platform_device *pdev;
661 struct mdp5_kms *mdp5_kms;
662 struct mdp5_cfg *config;
664 struct msm_gem_address_space *aspace;
667 /* priv->kms would have been populated by the MDP5 driver */
672 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
674 mdp_kms_init(&mdp5_kms->base, &kms_funcs);
676 pdev = mdp5_kms->pdev;
678 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
681 DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret);
687 config = mdp5_cfg_get_config(mdp5_kms->cfg);
689 /* make sure things are off before attaching iommu (bootloader could
690 * have left things on, in which case we'll start getting faults if
693 pm_runtime_get_sync(&pdev->dev);
694 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
695 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
696 !config->hw->intf.base[i])
698 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
700 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);
704 if (config->platform.iommu) {
705 aspace = msm_gem_address_space_create(&pdev->dev,
706 config->platform.iommu, "mdp5");
707 if (IS_ERR(aspace)) {
708 ret = PTR_ERR(aspace);
712 kms->aspace = aspace;
714 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
715 ARRAY_SIZE(iommu_ports));
717 DRM_DEV_ERROR(&pdev->dev, "failed to attach iommu: %d\n",
722 DRM_DEV_INFO(&pdev->dev,
723 "no iommu, fallback to phys contig buffers for scanout\n");
727 pm_runtime_put_sync(&pdev->dev);
729 ret = modeset_init(mdp5_kms);
731 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret);
735 dev->mode_config.min_width = 0;
736 dev->mode_config.min_height = 0;
737 dev->mode_config.max_width = 0xffff;
738 dev->mode_config.max_height = 0xffff;
740 dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
741 dev->driver->get_scanout_position = mdp5_get_scanoutpos;
742 dev->driver->get_vblank_counter = mdp5_get_vblank_counter;
743 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */
744 dev->vblank_disable_immediate = true;
749 mdp5_kms_destroy(kms);
753 static void mdp5_destroy(struct platform_device *pdev)
755 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
759 mdp5_ctlm_destroy(mdp5_kms->ctlm);
761 mdp5_smp_destroy(mdp5_kms->smp);
763 mdp5_cfg_destroy(mdp5_kms->cfg);
765 for (i = 0; i < mdp5_kms->num_intfs; i++)
766 kfree(mdp5_kms->intfs[i]);
768 if (mdp5_kms->rpm_enabled)
769 pm_runtime_disable(&pdev->dev);
771 drm_atomic_private_obj_fini(&mdp5_kms->glob_state);
772 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock);
775 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
776 const enum mdp5_pipe *pipes, const uint32_t *offsets,
779 struct drm_device *dev = mdp5_kms->dev;
782 for (i = 0; i < cnt; i++) {
783 struct mdp5_hw_pipe *hwpipe;
785 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps);
786 if (IS_ERR(hwpipe)) {
787 ret = PTR_ERR(hwpipe);
788 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n",
789 pipe2name(pipes[i]), ret);
792 hwpipe->idx = mdp5_kms->num_hwpipes;
793 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;
799 static int hwpipe_init(struct mdp5_kms *mdp5_kms)
801 static const enum mdp5_pipe rgb_planes[] = {
802 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
804 static const enum mdp5_pipe vig_planes[] = {
805 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
807 static const enum mdp5_pipe dma_planes[] = {
808 SSPP_DMA0, SSPP_DMA1,
810 static const enum mdp5_pipe cursor_planes[] = {
811 SSPP_CURSOR0, SSPP_CURSOR1,
813 const struct mdp5_cfg_hw *hw_cfg;
816 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
818 /* Construct RGB pipes: */
819 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,
820 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);
824 /* Construct video (VIG) pipes: */
825 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
826 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);
830 /* Construct DMA pipes: */
831 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,
832 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);
836 /* Construct cursor pipes: */
837 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,
838 cursor_planes, hw_cfg->pipe_cursor.base,
839 hw_cfg->pipe_cursor.caps);
846 static int hwmixer_init(struct mdp5_kms *mdp5_kms)
848 struct drm_device *dev = mdp5_kms->dev;
849 const struct mdp5_cfg_hw *hw_cfg;
852 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
854 for (i = 0; i < hw_cfg->lm.count; i++) {
855 struct mdp5_hw_mixer *mixer;
857 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]);
859 ret = PTR_ERR(mixer);
860 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n",
865 mixer->idx = mdp5_kms->num_hwmixers;
866 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer;
872 static int interface_init(struct mdp5_kms *mdp5_kms)
874 struct drm_device *dev = mdp5_kms->dev;
875 const struct mdp5_cfg_hw *hw_cfg;
876 const enum mdp5_intf_type *intf_types;
879 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
880 intf_types = hw_cfg->intf.connect;
882 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
883 struct mdp5_interface *intf;
885 if (intf_types[i] == INTF_DISABLED)
888 intf = kzalloc(sizeof(*intf), GFP_KERNEL);
890 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i);
895 intf->type = intf_types[i];
896 intf->mode = MDP5_INTF_MODE_NONE;
897 intf->idx = mdp5_kms->num_intfs;
898 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf;
904 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
906 struct msm_drm_private *priv = dev->dev_private;
907 struct mdp5_kms *mdp5_kms;
908 struct mdp5_cfg *config;
912 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);
918 platform_set_drvdata(pdev, mdp5_kms);
920 spin_lock_init(&mdp5_kms->resource_lock);
923 mdp5_kms->pdev = pdev;
925 ret = mdp5_global_obj_init(mdp5_kms);
929 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
930 if (IS_ERR(mdp5_kms->mmio)) {
931 ret = PTR_ERR(mdp5_kms->mmio);
935 /* mandatory clocks: */
936 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true);
939 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true);
942 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true);
945 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true);
949 /* optional clocks: */
950 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);
952 /* we need to set a default rate before enabling. Set a safe
953 * rate first, then figure out hw revision, and then set a
956 clk_set_rate(mdp5_kms->core_clk, 200000000);
958 pm_runtime_enable(&pdev->dev);
959 mdp5_kms->rpm_enabled = true;
961 read_mdp_hw_revision(mdp5_kms, &major, &minor);
963 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
964 if (IS_ERR(mdp5_kms->cfg)) {
965 ret = PTR_ERR(mdp5_kms->cfg);
966 mdp5_kms->cfg = NULL;
970 config = mdp5_cfg_get_config(mdp5_kms->cfg);
971 mdp5_kms->caps = config->hw->mdp.caps;
973 /* TODO: compute core clock rate at runtime */
974 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
977 * Some chipsets have a Shared Memory Pool (SMP), while others
978 * have dedicated latency buffering per source pipe instead;
979 * this section initializes the SMP:
981 if (mdp5_kms->caps & MDP_CAP_SMP) {
982 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);
983 if (IS_ERR(mdp5_kms->smp)) {
984 ret = PTR_ERR(mdp5_kms->smp);
985 mdp5_kms->smp = NULL;
990 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
991 if (IS_ERR(mdp5_kms->ctlm)) {
992 ret = PTR_ERR(mdp5_kms->ctlm);
993 mdp5_kms->ctlm = NULL;
997 ret = hwpipe_init(mdp5_kms);
1001 ret = hwmixer_init(mdp5_kms);
1005 ret = interface_init(mdp5_kms);
1009 /* set uninit-ed kms */
1010 priv->kms = &mdp5_kms->base.base;
1018 static int mdp5_bind(struct device *dev, struct device *master, void *data)
1020 struct drm_device *ddev = dev_get_drvdata(master);
1021 struct platform_device *pdev = to_platform_device(dev);
1025 return mdp5_init(pdev, ddev);
1028 static void mdp5_unbind(struct device *dev, struct device *master,
1031 struct platform_device *pdev = to_platform_device(dev);
1036 static const struct component_ops mdp5_ops = {
1038 .unbind = mdp5_unbind,
1041 static int mdp5_setup_interconnect(struct platform_device *pdev)
1043 struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem");
1044 struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem");
1045 struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem");
1048 return PTR_ERR(path0);
1051 /* no interconnect support is not necessarily a fatal
1052 * condition, the platform may simply not have an
1053 * interconnect driver yet. But warn about it in case
1054 * bootloader didn't setup bus clocks high enough for
1057 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n");
1061 icc_set_bw(path0, 0, MBps_to_icc(6400));
1063 if (!IS_ERR_OR_NULL(path1))
1064 icc_set_bw(path1, 0, MBps_to_icc(6400));
1065 if (!IS_ERR_OR_NULL(path_rot))
1066 icc_set_bw(path_rot, 0, MBps_to_icc(6400));
1071 static int mdp5_dev_probe(struct platform_device *pdev)
1077 ret = mdp5_setup_interconnect(pdev);
1081 return component_add(&pdev->dev, &mdp5_ops);
1084 static int mdp5_dev_remove(struct platform_device *pdev)
1087 component_del(&pdev->dev, &mdp5_ops);
1091 static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
1093 struct platform_device *pdev = to_platform_device(dev);
1094 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1098 return mdp5_disable(mdp5_kms);
1101 static __maybe_unused int mdp5_runtime_resume(struct device *dev)
1103 struct platform_device *pdev = to_platform_device(dev);
1104 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1108 return mdp5_enable(mdp5_kms);
1111 static const struct dev_pm_ops mdp5_pm_ops = {
1112 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL)
1115 static const struct of_device_id mdp5_dt_match[] = {
1116 { .compatible = "qcom,mdp5", },
1117 /* to support downstream DT files */
1118 { .compatible = "qcom,mdss_mdp", },
1121 MODULE_DEVICE_TABLE(of, mdp5_dt_match);
1123 static struct platform_driver mdp5_driver = {
1124 .probe = mdp5_dev_probe,
1125 .remove = mdp5_dev_remove,
1128 .of_match_table = mdp5_dt_match,
1133 void __init msm_mdp_register(void)
1136 platform_driver_register(&mdp5_driver);
1139 void __exit msm_mdp_unregister(void)
1142 platform_driver_unregister(&mdp5_driver);