drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

   1 /*
   2  * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <drm/drm_print.h>
  20 #include "mdp5_kms.h"
  21
  22 struct mdp5_plane {
  23         struct drm_plane base;
  24
  25         uint32_t nformats;
  26         uint32_t formats[32];
  27 };
  28 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
  29
  30 static int mdp5_plane_mode_set(struct drm_plane *plane,
  31                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
  32                 struct drm_rect *src, struct drm_rect *dest);
  33
  34 static struct mdp5_kms *get_kms(struct drm_plane *plane)
  35 {
  36         struct msm_drm_private *priv = plane->dev->dev_private;
  37         return to_mdp5_kms(to_mdp_kms(priv->kms));
  38 }
  39
  40 static bool plane_enabled(struct drm_plane_state *state)
  41 {
  42         return state->visible;
  43 }
  44
  45 static void mdp5_plane_destroy(struct drm_plane *plane)
  46 {
  47         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
  48
  49         drm_plane_helper_disable(plane);
  50         drm_plane_cleanup(plane);
  51
  52         kfree(mdp5_plane);
  53 }
  54
  55 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
  56                 struct drm_plane *plane)
  57 {
  58         drm_plane_create_rotation_property(plane,
  59                                            DRM_MODE_ROTATE_0,
  60                                            DRM_MODE_ROTATE_0 |
  61                                            DRM_MODE_ROTATE_180 |
  62                                            DRM_MODE_REFLECT_X |
  63                                            DRM_MODE_REFLECT_Y);
  64 }
  65
  66 /* helper to install properties which are common to planes and crtcs */
  67 static void mdp5_plane_install_properties(struct drm_plane *plane,
  68                 struct drm_mode_object *obj)
  69 {
  70         struct drm_device *dev = plane->dev;
  71         struct msm_drm_private *dev_priv = dev->dev_private;
  72         struct drm_property *prop;
  73
  74 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
  75                 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
  76                 if (!prop) { \
  77                         prop = drm_property_##fnc(dev, 0, #name, \
  78                                 ##__VA_ARGS__); \
  79                         if (!prop) { \
  80                                 dev_warn(dev->dev, \
  81                                         "Create property %s failed\n", \
  82                                         #name); \
  83                                 return; \
  84                         } \
  85                         dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
  86                 } \
  87                 drm_object_attach_property(&plane->base, prop, init_val); \
  88         } while (0)
  89
  90 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
  91                 INSTALL_PROPERTY(name, NAME, init_val, \
  92                                 create_range, min, max)
  93
  94 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
  95                 INSTALL_PROPERTY(name, NAME, init_val, \
  96                                 create_enum, name##_prop_enum_list, \
  97                                 ARRAY_SIZE(name##_prop_enum_list))
  98
  99         INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
 100
 101         mdp5_plane_install_rotation_property(dev, plane);
 102
 103 #undef INSTALL_RANGE_PROPERTY
 104 #undef INSTALL_ENUM_PROPERTY
 105 #undef INSTALL_PROPERTY
 106 }
 107
 108 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
 109                 struct drm_plane_state *state, struct drm_property *property,
 110                 uint64_t val)
 111 {
 112         struct drm_device *dev = plane->dev;
 113         struct mdp5_plane_state *pstate;
 114         struct msm_drm_private *dev_priv = dev->dev_private;
 115         int ret = 0;
 116
 117         pstate = to_mdp5_plane_state(state);
 118
 119 #define SET_PROPERTY(name, NAME, type) do { \
 120                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 121                         pstate->name = (type)val; \
 122                         DBG("Set property %s %d", #name, (type)val); \
 123                         goto done; \
 124                 } \
 125         } while (0)
 126
 127         SET_PROPERTY(zpos, ZPOS, uint8_t);
 128
 129         dev_err(dev->dev, "Invalid property\n");
 130         ret = -EINVAL;
 131 done:
 132         return ret;
 133 #undef SET_PROPERTY
 134 }
 135
 136 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
 137                 const struct drm_plane_state *state,
 138                 struct drm_property *property, uint64_t *val)
 139 {
 140         struct drm_device *dev = plane->dev;
 141         struct mdp5_plane_state *pstate;
 142         struct msm_drm_private *dev_priv = dev->dev_private;
 143         int ret = 0;
 144
 145         pstate = to_mdp5_plane_state(state);
 146
 147 #define GET_PROPERTY(name, NAME, type) do { \
 148                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 149                         *val = pstate->name; \
 150                         DBG("Get property %s %lld", #name, *val); \
 151                         goto done; \
 152                 } \
 153         } while (0)
 154
 155         GET_PROPERTY(zpos, ZPOS, uint8_t);
 156
 157         dev_err(dev->dev, "Invalid property\n");
 158         ret = -EINVAL;
 159 done:
 160         return ret;
 161 #undef SET_PROPERTY
 162 }
 163
 164 static void
 165 mdp5_plane_atomic_print_state(struct drm_printer *p,
 166                 const struct drm_plane_state *state)
 167 {
 168         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 169         struct mdp5_kms *mdp5_kms = get_kms(state->plane);
 170
 171         drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
 172                         pstate->hwpipe->name : "(null)");
 173         if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
 174                 drm_printf(p, "\tright-hwpipe=%s\n",
 175                            pstate->r_hwpipe ? pstate->r_hwpipe->name :
 176                                               "(null)");
 177         drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
 178         drm_printf(p, "\tzpos=%u\n", pstate->zpos);
 179         drm_printf(p, "\talpha=%u\n", pstate->alpha);
 180         drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
 181 }
 182
 183 static void mdp5_plane_reset(struct drm_plane *plane)
 184 {
 185         struct mdp5_plane_state *mdp5_state;
 186
 187         if (plane->state && plane->state->fb)
 188                 drm_framebuffer_unreference(plane->state->fb);
 189
 190         kfree(to_mdp5_plane_state(plane->state));
 191         mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
 192
 193         /* assign default blend parameters */
 194         mdp5_state->alpha = 255;
 195         mdp5_state->premultiplied = 0;
 196
 197         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 198                 mdp5_state->zpos = STAGE_BASE;
 199         else
 200                 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
 201
 202         mdp5_state->base.plane = plane;
 203
 204         plane->state = &mdp5_state->base;
 205 }
 206
 207 static struct drm_plane_state *
 208 mdp5_plane_duplicate_state(struct drm_plane *plane)
 209 {
 210         struct mdp5_plane_state *mdp5_state;
 211
 212         if (WARN_ON(!plane->state))
 213                 return NULL;
 214
 215         mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
 216                         sizeof(*mdp5_state), GFP_KERNEL);
 217         if (!mdp5_state)
 218                 return NULL;
 219
 220         __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
 221
 222         return &mdp5_state->base;
 223 }
 224
 225 static void mdp5_plane_destroy_state(struct drm_plane *plane,
 226                 struct drm_plane_state *state)
 227 {
 228         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 229
 230         if (state->fb)
 231                 drm_framebuffer_unreference(state->fb);
 232
 233         kfree(pstate);
 234 }
 235
 236 static const struct drm_plane_funcs mdp5_plane_funcs = {
 237                 .update_plane = drm_atomic_helper_update_plane,
 238                 .disable_plane = drm_atomic_helper_disable_plane,
 239                 .destroy = mdp5_plane_destroy,
 240                 .atomic_set_property = mdp5_plane_atomic_set_property,
 241                 .atomic_get_property = mdp5_plane_atomic_get_property,
 242                 .reset = mdp5_plane_reset,
 243                 .atomic_duplicate_state = mdp5_plane_duplicate_state,
 244                 .atomic_destroy_state = mdp5_plane_destroy_state,
 245                 .atomic_print_state = mdp5_plane_atomic_print_state,
 246 };
 247
 248 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
 249                                  struct drm_plane_state *new_state)
 250 {
 251         struct mdp5_kms *mdp5_kms = get_kms(plane);
 252         struct msm_kms *kms = &mdp5_kms->base.base;
 253         struct drm_framebuffer *fb = new_state->fb;
 254
 255         if (!new_state->fb)
 256                 return 0;
 257
 258         DBG("%s: prepare: FB[%u]", plane->name, fb->base.id);
 259         return msm_framebuffer_prepare(fb, kms->aspace);
 260 }
 261
 262 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
 263                                   struct drm_plane_state *old_state)
 264 {
 265         struct mdp5_kms *mdp5_kms = get_kms(plane);
 266         struct msm_kms *kms = &mdp5_kms->base.base;
 267         struct drm_framebuffer *fb = old_state->fb;
 268
 269         if (!fb)
 270                 return;
 271
 272         DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
 273         msm_framebuffer_cleanup(fb, kms->aspace);
 274 }
 275
 276 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
 277 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
 278                                               struct drm_plane_state *state)
 279 {
 280         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 281         struct drm_plane *plane = state->plane;
 282         struct drm_plane_state *old_state = plane->state;
 283         struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
 284         bool new_hwpipe = false;
 285         bool need_right_hwpipe = false;
 286         uint32_t max_width, max_height;
 287         bool out_of_bounds = false;
 288         uint32_t caps = 0;
 289         struct drm_rect clip = {};
 290         int min_scale, max_scale;
 291         int ret;
 292
 293         DBG("%s: check (%d -> %d)", plane->name,
 294                         plane_enabled(old_state), plane_enabled(state));
 295
 296         max_width = config->hw->lm.max_width << 16;
 297         max_height = config->hw->lm.max_height << 16;
 298
 299         /* Make sure source dimensions are within bounds. */
 300         if (state->src_h > max_height)
 301                 out_of_bounds = true;
 302
 303         if (state->src_w > max_width) {
 304                 /* If source split is supported, we can go up to 2x
 305                  * the max LM width, but we'd need to stage another
 306                  * hwpipe to the right LM. So, the drm_plane would
 307                  * consist of 2 hwpipes.
 308                  */
 309                 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
 310                     (state->src_w <= 2 * max_width))
 311                         need_right_hwpipe = true;
 312                 else
 313                         out_of_bounds = true;
 314         }
 315
 316         if (out_of_bounds) {
 317                 struct drm_rect src = drm_plane_state_src(state);
 318                 DBG("Invalid source size "DRM_RECT_FP_FMT,
 319                                 DRM_RECT_FP_ARG(&src));
 320                 return -ERANGE;
 321         }
 322
 323         min_scale = FRAC_16_16(1, 8);
 324         max_scale = FRAC_16_16(8, 1);
 325
 326         if (crtc_state->enable)
 327                 drm_mode_get_hv_timing(&crtc_state->mode,
 328                                        &clip.x2, &clip.y2);
 329
 330         ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
 331                                                   min_scale, max_scale,
 332                                                   true, true);
 333         if (ret)
 334                 return ret;
 335
 336         if (plane_enabled(state)) {
 337                 unsigned int rotation;
 338                 const struct mdp_format *format;
 339                 struct mdp5_kms *mdp5_kms = get_kms(plane);
 340                 uint32_t blkcfg = 0;
 341
 342                 format = to_mdp_format(msm_framebuffer_format(state->fb));
 343                 if (MDP_FORMAT_IS_YUV(format))
 344                         caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
 345
 346                 if (((state->src_w >> 16) != state->crtc_w) ||
 347                                 ((state->src_h >> 16) != state->crtc_h))
 348                         caps |= MDP_PIPE_CAP_SCALE;
 349
 350                 rotation = drm_rotation_simplify(state->rotation,
 351                                                  DRM_MODE_ROTATE_0 |
 352                                                  DRM_MODE_REFLECT_X |
 353                                                  DRM_MODE_REFLECT_Y);
 354
 355                 if (rotation & DRM_MODE_REFLECT_X)
 356                         caps |= MDP_PIPE_CAP_HFLIP;
 357
 358                 if (rotation & DRM_MODE_REFLECT_Y)
 359                         caps |= MDP_PIPE_CAP_VFLIP;
 360
 361                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 362                         caps |= MDP_PIPE_CAP_CURSOR;
 363
 364                 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
 365                 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
 366                         new_hwpipe = true;
 367
 368                 /*
 369                  * (re)allocte hw pipe if we're either requesting for 2 hw pipes
 370                  * or we're switching from 2 hw pipes to 1 hw pipe because the
 371                  * new src_w can be supported by 1 hw pipe itself.
 372                  */
 373                 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
 374                     (!need_right_hwpipe && mdp5_state->r_hwpipe))
 375                         new_hwpipe = true;
 376
 377                 if (mdp5_kms->smp) {
 378                         const struct mdp_format *format =
 379                                 to_mdp_format(msm_framebuffer_format(state->fb));
 380
 381                         blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
 382                                         state->src_w >> 16, false);
 383
 384                         if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
 385                                 new_hwpipe = true;
 386                 }
 387
 388                 /* (re)assign hwpipe if needed, otherwise keep old one: */
 389                 if (new_hwpipe) {
 390                         /* TODO maybe we want to re-assign hwpipe sometimes
 391                          * in cases when we no-longer need some caps to make
 392                          * it available for other planes?
 393                          */
 394                         struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
 395                         struct mdp5_hw_pipe *old_right_hwpipe =
 396                                                           mdp5_state->r_hwpipe;
 397                         struct mdp5_hw_pipe *new_hwpipe = NULL;
 398                         struct mdp5_hw_pipe *new_right_hwpipe = NULL;
 399
 400                         ret = mdp5_pipe_assign(state->state, plane, caps,
 401                                                blkcfg, &new_hwpipe,
 402                                                need_right_hwpipe ?
 403                                                &new_right_hwpipe : NULL);
 404                         if (ret) {
 405                                 DBG("%s: failed to assign hwpipe(s)!",
 406                                     plane->name);
 407                                 return ret;
 408                         }
 409
 410                         mdp5_state->hwpipe = new_hwpipe;
 411                         if (need_right_hwpipe)
 412                                 mdp5_state->r_hwpipe = new_right_hwpipe;
 413                         else
 414                                 /*
 415                                  * set it to NULL so that the driver knows we
 416                                  * don't have a right hwpipe when committing a
 417                                  * new state
 418                                  */
 419                                 mdp5_state->r_hwpipe = NULL;
 420
 421
 422                         mdp5_pipe_release(state->state, old_hwpipe);
 423                         mdp5_pipe_release(state->state, old_right_hwpipe);
 424                 }
 425         } else {
 426                 mdp5_pipe_release(state->state, mdp5_state->hwpipe);
 427                 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
 428                 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
 429         }
 430
 431         return 0;
 432 }
 433
 434 static int mdp5_plane_atomic_check(struct drm_plane *plane,
 435                                    struct drm_plane_state *state)
 436 {
 437         struct drm_crtc *crtc;
 438         struct drm_crtc_state *crtc_state;
 439
 440         crtc = state->crtc ? state->crtc : plane->state->crtc;
 441         if (!crtc)
 442                 return 0;
 443
 444         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 445         if (WARN_ON(!crtc_state))
 446                 return -EINVAL;
 447
 448         return mdp5_plane_atomic_check_with_state(crtc_state, state);
 449 }
 450
 451 static void mdp5_plane_atomic_update(struct drm_plane *plane,
 452                                      struct drm_plane_state *old_state)
 453 {
 454         struct drm_plane_state *state = plane->state;
 455
 456         DBG("%s: update", plane->name);
 457
 458         if (plane_enabled(state)) {
 459                 int ret;
 460
 461                 ret = mdp5_plane_mode_set(plane,
 462                                 state->crtc, state->fb,
 463                                 &state->src, &state->dst);
 464                 /* atomic_check should have ensured that this doesn't fail */
 465                 WARN_ON(ret < 0);
 466         }
 467 }
 468
 469 static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
 470                                          struct drm_plane_state *state)
 471 {
 472         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 473         struct drm_crtc_state *crtc_state;
 474         struct drm_rect clip = {};
 475         int min_scale, max_scale;
 476         int ret;
 477
 478         crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 479                                                         state->crtc);
 480         if (WARN_ON(!crtc_state))
 481                 return -EINVAL;
 482
 483         if (!crtc_state->active)
 484                 return -EINVAL;
 485
 486         mdp5_state = to_mdp5_plane_state(state);
 487
 488         /* don't use fast path if we don't have a hwpipe allocated yet */
 489         if (!mdp5_state->hwpipe)
 490                 return -EINVAL;
 491
 492         /* only allow changing of position(crtc x/y or src x/y) in fast path */
 493         if (plane->state->crtc != state->crtc ||
 494             plane->state->src_w != state->src_w ||
 495             plane->state->src_h != state->src_h ||
 496             plane->state->crtc_w != state->crtc_w ||
 497             plane->state->crtc_h != state->crtc_h ||
 498             !plane->state->fb ||
 499             plane->state->fb != state->fb)
 500                 return -EINVAL;
 501
 502         min_scale = FRAC_16_16(1, 8);
 503         max_scale = FRAC_16_16(8, 1);
 504
 505         if (crtc_state->enable)
 506                 drm_mode_get_hv_timing(&crtc_state->mode,
 507                                        &clip.x2, &clip.y2);
 508
 509         ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
 510                                                   min_scale, max_scale,
 511                                                   true, true);
 512         if (ret)
 513                 return ret;
 514
 515         /*
 516          * if the visibility of the plane changes (i.e, if the cursor is
 517          * clipped out completely, we can't take the async path because
 518          * we need to stage/unstage the plane from the Layer Mixer(s). We
 519          * also assign/unassign the hwpipe(s) tied to the plane. We avoid
 520          * taking the fast path for both these reasons.
 521          */
 522         if (state->visible != plane->state->visible)
 523                 return -EINVAL;
 524
 525         return 0;
 526 }
 527
 528 static void mdp5_plane_atomic_async_update(struct drm_plane *plane,
 529                                            struct drm_plane_state *new_state)
 530 {
 531         plane->state->src_x = new_state->src_x;
 532         plane->state->src_y = new_state->src_y;
 533         plane->state->crtc_x = new_state->crtc_x;
 534         plane->state->crtc_y = new_state->crtc_y;
 535
 536         if (plane_enabled(new_state)) {
 537                 struct mdp5_ctl *ctl;
 538                 struct mdp5_pipeline *pipeline =
 539                                         mdp5_crtc_get_pipeline(plane->crtc);
 540                 int ret;
 541
 542                 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb,
 543                                 &new_state->src, &new_state->dst);
 544                 WARN_ON(ret < 0);
 545
 546                 ctl = mdp5_crtc_get_ctl(new_state->crtc);
 547
 548                 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);
 549         }
 550
 551         *to_mdp5_plane_state(plane->state) =
 552                 *to_mdp5_plane_state(new_state);
 553 }
 554
 555 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
 556                 .prepare_fb = mdp5_plane_prepare_fb,
 557                 .cleanup_fb = mdp5_plane_cleanup_fb,
 558                 .atomic_check = mdp5_plane_atomic_check,
 559                 .atomic_update = mdp5_plane_atomic_update,
 560                 .atomic_async_check = mdp5_plane_atomic_async_check,
 561                 .atomic_async_update = mdp5_plane_atomic_async_update,
 562 };
 563
 564 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
 565                                enum mdp5_pipe pipe,
 566                                struct drm_framebuffer *fb)
 567 {
 568         struct msm_kms *kms = &mdp5_kms->base.base;
 569
 570         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
 571                         MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
 572                         MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
 573
 574         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
 575                         MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
 576                         MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
 577
 578         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
 579                         msm_framebuffer_iova(fb, kms->aspace, 0));
 580         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
 581                         msm_framebuffer_iova(fb, kms->aspace, 1));
 582         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
 583                         msm_framebuffer_iova(fb, kms->aspace, 2));
 584         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
 585                         msm_framebuffer_iova(fb, kms->aspace, 3));
 586 }
 587
 588 /* Note: mdp5_plane->pipe_lock must be locked */
 589 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
 590 {
 591         uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
 592                          ~MDP5_PIPE_OP_MODE_CSC_1_EN;
 593
 594         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
 595 }
 596
 597 /* Note: mdp5_plane->pipe_lock must be locked */
 598 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 599                 struct csc_cfg *csc)
 600 {
 601         uint32_t  i, mode = 0; /* RGB, no CSC */
 602         uint32_t *matrix;
 603
 604         if (unlikely(!csc))
 605                 return;
 606
 607         if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
 608                 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
 609         if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
 610                 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
 611         mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
 612         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
 613
 614         matrix = csc->matrix;
 615         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
 616                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
 617                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
 618         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
 619                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
 620                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
 621         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
 622                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
 623                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
 624         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
 625                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
 626                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
 627         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
 628                         MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
 629
 630         for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
 631                 uint32_t *pre_clamp = csc->pre_clamp;
 632                 uint32_t *post_clamp = csc->post_clamp;
 633
 634                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
 635                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
 636                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
 637
 638                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
 639                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
 640                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
 641
 642                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
 643                         MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
 644
 645                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
 646                         MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
 647         }
 648 }
 649
 650 #define PHASE_STEP_SHIFT        21
 651 #define DOWN_SCALE_RATIO_MAX    32      /* 2^(26-21) */
 652
 653 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
 654 {
 655         uint32_t unit;
 656
 657         if (src == 0 || dst == 0)
 658                 return -EINVAL;
 659
 660         /*
 661          * PHASE_STEP_X/Y is coded on 26 bits (25:0),
 662          * where 2^21 represents the unity "1" in fixed-point hardware design.
 663          * This leaves 5 bits for the integer part (downscale case):
 664          *      -> maximum downscale ratio = 0b1_1111 = 31
 665          */
 666         if (src > (dst * DOWN_SCALE_RATIO_MAX))
 667                 return -EOVERFLOW;
 668
 669         unit = 1 << PHASE_STEP_SHIFT;
 670         *out_phase = mult_frac(unit, src, dst);
 671
 672         return 0;
 673 }
 674
 675 static int calc_scalex_steps(struct drm_plane *plane,
 676                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 677                 uint32_t phasex_steps[COMP_MAX])
 678 {
 679         struct mdp5_kms *mdp5_kms = get_kms(plane);
 680         struct device *dev = mdp5_kms->dev->dev;
 681         uint32_t phasex_step;
 682         unsigned int hsub;
 683         int ret;
 684
 685         ret = calc_phase_step(src, dest, &phasex_step);
 686         if (ret) {
 687                 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
 688                 return ret;
 689         }
 690
 691         hsub = drm_format_horz_chroma_subsampling(pixel_format);
 692
 693         phasex_steps[COMP_0]   = phasex_step;
 694         phasex_steps[COMP_3]   = phasex_step;
 695         phasex_steps[COMP_1_2] = phasex_step / hsub;
 696
 697         return 0;
 698 }
 699
 700 static int calc_scaley_steps(struct drm_plane *plane,
 701                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 702                 uint32_t phasey_steps[COMP_MAX])
 703 {
 704         struct mdp5_kms *mdp5_kms = get_kms(plane);
 705         struct device *dev = mdp5_kms->dev->dev;
 706         uint32_t phasey_step;
 707         unsigned int vsub;
 708         int ret;
 709
 710         ret = calc_phase_step(src, dest, &phasey_step);
 711         if (ret) {
 712                 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
 713                 return ret;
 714         }
 715
 716         vsub = drm_format_vert_chroma_subsampling(pixel_format);
 717
 718         phasey_steps[COMP_0]   = phasey_step;
 719         phasey_steps[COMP_3]   = phasey_step;
 720         phasey_steps[COMP_1_2] = phasey_step / vsub;
 721
 722         return 0;
 723 }
 724
 725 static uint32_t get_scale_config(const struct mdp_format *format,
 726                 uint32_t src, uint32_t dst, bool horz)
 727 {
 728         bool scaling = format->is_yuv ? true : (src != dst);
 729         uint32_t sub, pix_fmt = format->base.pixel_format;
 730         uint32_t ya_filter, uv_filter;
 731         bool yuv = format->is_yuv;
 732
 733         if (!scaling)
 734                 return 0;
 735
 736         if (yuv) {
 737                 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
 738                              drm_format_vert_chroma_subsampling(pix_fmt);
 739                 uv_filter = ((src / sub) <= dst) ?
 740                                    SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 741         }
 742         ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 743
 744         if (horz)
 745                 return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
 746                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
 747                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
 748                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
 749         else
 750                 return  MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
 751                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
 752                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
 753                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
 754 }
 755
 756 static void calc_pixel_ext(const struct mdp_format *format,
 757                 uint32_t src, uint32_t dst, uint32_t phase_step[2],
 758                 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
 759                 bool horz)
 760 {
 761         bool scaling = format->is_yuv ? true : (src != dst);
 762         int i;
 763
 764         /*
 765          * Note:
 766          * We assume here that:
 767          *     1. PCMN filter is used for downscale
 768          *     2. bilinear filter is used for upscale
 769          *     3. we are in a single pipe configuration
 770          */
 771
 772         for (i = 0; i < COMP_MAX; i++) {
 773                 pix_ext_edge1[i] = 0;
 774                 pix_ext_edge2[i] = scaling ? 1 : 0;
 775         }
 776 }
 777
 778 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 779         const struct mdp_format *format,
 780         uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
 781         uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
 782 {
 783         uint32_t pix_fmt = format->base.pixel_format;
 784         uint32_t lr, tb, req;
 785         int i;
 786
 787         for (i = 0; i < COMP_MAX; i++) {
 788                 uint32_t roi_w = src_w;
 789                 uint32_t roi_h = src_h;
 790
 791                 if (format->is_yuv && i == COMP_1_2) {
 792                         roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
 793                         roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
 794                 }
 795
 796                 lr  = (pe_left[i] >= 0) ?
 797                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
 798                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
 799
 800                 lr |= (pe_right[i] >= 0) ?
 801                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
 802                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
 803
 804                 tb  = (pe_top[i] >= 0) ?
 805                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
 806                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
 807
 808                 tb |= (pe_bottom[i] >= 0) ?
 809                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
 810                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
 811
 812                 req  = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
 813                                 pe_left[i] + pe_right[i]);
 814
 815                 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
 816                                 pe_top[i] + pe_bottom[i]);
 817
 818                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
 819                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
 820                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
 821
 822                 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 823                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
 824                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
 825                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
 826                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
 827                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
 828
 829                 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 830                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
 831                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
 832                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
 833                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
 834                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
 835         }
 836 }
 837
 838 struct pixel_ext {
 839         int left[COMP_MAX];
 840         int right[COMP_MAX];
 841         int top[COMP_MAX];
 842         int bottom[COMP_MAX];
 843 };
 844
 845 struct phase_step {
 846         u32 x[COMP_MAX];
 847         u32 y[COMP_MAX];
 848 };
 849
 850 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
 851                                  struct mdp5_hw_pipe *hwpipe,
 852                                  struct drm_framebuffer *fb,
 853                                  struct phase_step *step,
 854                                  struct pixel_ext *pe,
 855                                  u32 scale_config, u32 hdecm, u32 vdecm,
 856                                  bool hflip, bool vflip,
 857                                  int crtc_x, int crtc_y,
 858                                  unsigned int crtc_w, unsigned int crtc_h,
 859                                  u32 src_img_w, u32 src_img_h,
 860                                  u32 src_x, u32 src_y,
 861                                  u32 src_w, u32 src_h)
 862 {
 863         enum mdp5_pipe pipe = hwpipe->pipe;
 864         bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
 865         const struct mdp_format *format =
 866                         to_mdp_format(msm_framebuffer_format(fb));
 867
 868         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
 869                         MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
 870                         MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
 871
 872         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
 873                         MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
 874                         MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
 875
 876         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
 877                         MDP5_PIPE_SRC_XY_X(src_x) |
 878                         MDP5_PIPE_SRC_XY_Y(src_y));
 879
 880         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
 881                         MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
 882                         MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
 883
 884         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
 885                         MDP5_PIPE_OUT_XY_X(crtc_x) |
 886                         MDP5_PIPE_OUT_XY_Y(crtc_y));
 887
 888         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
 889                         MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
 890                         MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
 891                         MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
 892                         MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
 893                         COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
 894                         MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
 895                         MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
 896                         COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
 897                         MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
 898                         MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
 899
 900         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
 901                         MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
 902                         MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
 903                         MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
 904                         MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
 905
 906         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
 907                         (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
 908                         (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
 909                         COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
 910                         MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
 911
 912         /* not using secure mode: */
 913         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
 914
 915         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
 916                 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
 917                                 src_w, pe->left, pe->right,
 918                                 src_h, pe->top, pe->bottom);
 919
 920         if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
 921                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
 922                                 step->x[COMP_0]);
 923                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
 924                                 step->y[COMP_0]);
 925                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
 926                                 step->x[COMP_1_2]);
 927                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
 928                                 step->y[COMP_1_2]);
 929                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
 930                                 MDP5_PIPE_DECIMATION_VERT(vdecm) |
 931                                 MDP5_PIPE_DECIMATION_HORZ(hdecm));
 932                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
 933                            scale_config);
 934         }
 935
 936         if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
 937                 if (MDP_FORMAT_IS_YUV(format))
 938                         csc_enable(mdp5_kms, pipe,
 939                                         mdp_get_default_csc_cfg(CSC_YUV2RGB));
 940                 else
 941                         csc_disable(mdp5_kms, pipe);
 942         }
 943
 944         set_scanout_locked(mdp5_kms, pipe, fb);
 945 }
 946
 947 static int mdp5_plane_mode_set(struct drm_plane *plane,
 948                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 949                 struct drm_rect *src, struct drm_rect *dest)
 950 {
 951         struct drm_plane_state *pstate = plane->state;
 952         struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
 953         struct mdp5_kms *mdp5_kms = get_kms(plane);
 954         enum mdp5_pipe pipe = hwpipe->pipe;
 955         struct mdp5_hw_pipe *right_hwpipe;
 956         const struct mdp_format *format;
 957         uint32_t nplanes, config = 0;
 958         struct phase_step step = { { 0 } };
 959         struct pixel_ext pe = { { 0 } };
 960         uint32_t hdecm = 0, vdecm = 0;
 961         uint32_t pix_format;
 962         unsigned int rotation;
 963         bool vflip, hflip;
 964         int crtc_x, crtc_y;
 965         unsigned int crtc_w, crtc_h;
 966         uint32_t src_x, src_y;
 967         uint32_t src_w, src_h;
 968         uint32_t src_img_w, src_img_h;
 969         int ret;
 970
 971         nplanes = fb->format->num_planes;
 972
 973         /* bad formats should already be rejected: */
 974         if (WARN_ON(nplanes > pipe2nclients(pipe)))
 975                 return -EINVAL;
 976
 977         format = to_mdp_format(msm_framebuffer_format(fb));
 978         pix_format = format->base.pixel_format;
 979
 980         src_x = src->x1;
 981         src_y = src->y1;
 982         src_w = drm_rect_width(src);
 983         src_h = drm_rect_height(src);
 984
 985         crtc_x = dest->x1;
 986         crtc_y = dest->y1;
 987         crtc_w = drm_rect_width(dest);
 988         crtc_h = drm_rect_height(dest);
 989
 990         /* src values are in Q16 fixed point, convert to integer: */
 991         src_x = src_x >> 16;
 992         src_y = src_y >> 16;
 993         src_w = src_w >> 16;
 994         src_h = src_h >> 16;
 995
 996         src_img_w = min(fb->width, src_w);
 997         src_img_h = min(fb->height, src_h);
 998
 999         DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
1000                         fb->base.id, src_x, src_y, src_w, src_h,
1001                         crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
1002
1003         right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
1004         if (right_hwpipe) {
1005                 /*
1006                  * if the plane comprises of 2 hw pipes, assume that the width
1007                  * is split equally across them. The only parameters that varies
1008                  * between the 2 pipes are src_x and crtc_x
1009                  */
1010                 crtc_w /= 2;
1011                 src_w /= 2;
1012                 src_img_w /= 2;
1013         }
1014
1015         ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
1016         if (ret)
1017                 return ret;
1018
1019         ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
1020         if (ret)
1021                 return ret;
1022
1023         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
1024                 calc_pixel_ext(format, src_w, crtc_w, step.x,
1025                                pe.left, pe.right, true);
1026                 calc_pixel_ext(format, src_h, crtc_h, step.y,
1027                                pe.top, pe.bottom, false);
1028         }
1029
1030         /* TODO calc hdecm, vdecm */
1031
1032         /* SCALE is used to both scale and up-sample chroma components */
1033         config |= get_scale_config(format, src_w, crtc_w, true);
1034         config |= get_scale_config(format, src_h, crtc_h, false);
1035         DBG("scale config = %x", config);
1036
1037         rotation = drm_rotation_simplify(pstate->rotation,
1038                                          DRM_MODE_ROTATE_0 |
1039                                          DRM_MODE_REFLECT_X |
1040                                          DRM_MODE_REFLECT_Y);
1041         hflip = !!(rotation & DRM_MODE_REFLECT_X);
1042         vflip = !!(rotation & DRM_MODE_REFLECT_Y);
1043
1044         mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
1045                              config, hdecm, vdecm, hflip, vflip,
1046                              crtc_x, crtc_y, crtc_w, crtc_h,
1047                              src_img_w, src_img_h,
1048                              src_x, src_y, src_w, src_h);
1049         if (right_hwpipe)
1050                 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
1051                                      config, hdecm, vdecm, hflip, vflip,
1052                                      crtc_x + crtc_w, crtc_y, crtc_w, crtc_h,
1053                                      src_img_w, src_img_h,
1054                                      src_x + src_w, src_y, src_w, src_h);
1055
1056         plane->fb = fb;
1057
1058         return ret;
1059 }
1060
1061 /*
1062  * Use this func and the one below only after the atomic state has been
1063  * successfully swapped
1064  */
1065 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1066 {
1067         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1068
1069         if (WARN_ON(!pstate->hwpipe))
1070                 return SSPP_NONE;
1071
1072         return pstate->hwpipe->pipe;
1073 }
1074
1075 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1076 {
1077         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1078
1079         if (!pstate->r_hwpipe)
1080                 return SSPP_NONE;
1081
1082         return pstate->r_hwpipe->pipe;
1083 }
1084
1085 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1086 {
1087         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1088         u32 mask;
1089
1090         if (WARN_ON(!pstate->hwpipe))
1091                 return 0;
1092
1093         mask = pstate->hwpipe->flush_mask;
1094
1095         if (pstate->r_hwpipe)
1096                 mask |= pstate->r_hwpipe->flush_mask;
1097
1098         return mask;
1099 }
1100
1101 /* initialize plane */
1102 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1103                                   enum drm_plane_type type)
1104 {
1105         struct drm_plane *plane = NULL;
1106         struct mdp5_plane *mdp5_plane;
1107         int ret;
1108
1109         mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1110         if (!mdp5_plane) {
1111                 ret = -ENOMEM;
1112                 goto fail;
1113         }
1114
1115         plane = &mdp5_plane->base;
1116
1117         mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1118                 ARRAY_SIZE(mdp5_plane->formats), false);
1119
1120         ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
1121                         mdp5_plane->formats, mdp5_plane->nformats,
1122                         NULL, type, NULL);
1123         if (ret)
1124                 goto fail;
1125
1126         drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1127
1128         mdp5_plane_install_properties(plane, &plane->base);
1129
1130         return plane;
1131
1132 fail:
1133         if (plane)
1134                 mdp5_plane_destroy(plane);
1135
1136         return ERR_PTR(ret);
1137 }