1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
9 static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
10 unsigned long int pixclock)
12 /* De-serializer delay D/C for non-lbk mode: */
13 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG0,
14 HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(3));
16 if (pixclock == 27000000) {
17 /* video_format == HDMI_VFRMT_720x480p60_16_9 */
18 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
19 HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
20 HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(3));
22 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
23 HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
24 HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(4));
27 /* No matter what, start from the power down mode: */
28 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
29 HDMI_8x60_PHY_REG2_PD_PWRGEN |
30 HDMI_8x60_PHY_REG2_PD_PLL |
31 HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
32 HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
33 HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
34 HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
35 HDMI_8x60_PHY_REG2_PD_DESER);
37 /* Turn PowerGen on: */
38 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
39 HDMI_8x60_PHY_REG2_PD_PLL |
40 HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
41 HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
42 HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
43 HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
44 HDMI_8x60_PHY_REG2_PD_DESER);
46 /* Turn PLL power on: */
47 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
48 HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
49 HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
50 HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
51 HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
52 HDMI_8x60_PHY_REG2_PD_DESER);
54 /* Write to HIGH after PLL power down de-assert: */
55 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3,
56 HDMI_8x60_PHY_REG3_PLL_ENABLE);
58 /* ASIC power on; PHY REG9 = 0 */
59 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
61 /* Enable PLL lock detect, PLL lock det will go high after lock
62 * Enable the re-time logic
64 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
65 HDMI_8x60_PHY_REG12_RETIMING_EN |
66 HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN);
69 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
70 HDMI_8x60_PHY_REG2_PD_DESER);
72 /* If the RX detector is needed: */
73 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
74 HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
75 HDMI_8x60_PHY_REG2_PD_DESER);
77 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG4, 0);
78 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG5, 0);
79 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG6, 0);
80 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG7, 0);
81 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG8, 0);
82 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
83 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG10, 0);
84 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG11, 0);
86 /* If we want to use lock enable based on counting: */
87 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
88 HDMI_8x60_PHY_REG12_RETIMING_EN |
89 HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN |
90 HDMI_8x60_PHY_REG12_FORCE_LOCK);
93 static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
95 /* Assert RESET PHY from controller */
96 hdmi_phy_write(phy, REG_HDMI_PHY_CTRL,
97 HDMI_PHY_CTRL_SW_RESET);
99 /* De-assert RESET PHY from controller */
100 hdmi_phy_write(phy, REG_HDMI_PHY_CTRL, 0);
101 /* Turn off Driver */
102 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
103 HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
104 HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
105 HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
106 HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
107 HDMI_8x60_PHY_REG2_PD_DESER);
110 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3, 0);
111 /* Power down PHY, but keep RX-sense: */
112 hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
113 HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
114 HDMI_8x60_PHY_REG2_PD_PWRGEN |
115 HDMI_8x60_PHY_REG2_PD_PLL |
116 HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
117 HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
118 HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
119 HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
120 HDMI_8x60_PHY_REG2_PD_DESER);
123 const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg = {
124 .type = MSM_HDMI_PHY_8x60,
125 .powerup = hdmi_phy_8x60_powerup,
126 .powerdown = hdmi_phy_8x60_powerdown,