drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c

   1 /*
   2  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include "mdp5_kms.h"
  15 #include "mdp5_cfg.h"
  16
  17 struct mdp5_cfg_handler {
  18         int revision;
  19         struct mdp5_cfg config;
  20 };
  21
  22 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
  23 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
  24
  25 const struct mdp5_cfg_hw msm8x74v1_config = {
  26         .name = "msm8x74v1",
  27         .mdp = {
  28                 .count = 1,
  29                 .caps = MDP_CAP_SMP |
  30                         0,
  31         },
  32         .smp = {
  33                 .mmb_count = 22,
  34                 .mmb_size = 4096,
  35                 .clients = {
  36                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
  37                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
  38                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
  39                 },
  40         },
  41         .ctl = {
  42                 .count = 5,
  43                 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
  44                 .flush_hw_mask = 0x0003ffff,
  45         },
  46         .pipe_vig = {
  47                 .count = 3,
  48                 .base = { 0x01100, 0x01500, 0x01900 },
  49                 .caps = MDP_PIPE_CAP_HFLIP |
  50                         MDP_PIPE_CAP_VFLIP |
  51                         MDP_PIPE_CAP_SCALE |
  52                         MDP_PIPE_CAP_CSC   |
  53                         0,
  54         },
  55         .pipe_rgb = {
  56                 .count = 3,
  57                 .base = { 0x01d00, 0x02100, 0x02500 },
  58                 .caps = MDP_PIPE_CAP_HFLIP |
  59                         MDP_PIPE_CAP_VFLIP |
  60                         MDP_PIPE_CAP_SCALE |
  61                         0,
  62         },
  63         .pipe_dma = {
  64                 .count = 2,
  65                 .base = { 0x02900, 0x02d00 },
  66                 .caps = MDP_PIPE_CAP_HFLIP |
  67                         MDP_PIPE_CAP_VFLIP |
  68                         0,
  69         },
  70         .lm = {
  71                 .count = 5,
  72                 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
  73                 .instances = {
  74                                 { .id = 0, .pp = 0, .dspp = 0,
  75                                   .caps = MDP_LM_CAP_DISPLAY, },
  76                                 { .id = 1, .pp = 1, .dspp = 1,
  77                                   .caps = MDP_LM_CAP_DISPLAY, },
  78                                 { .id = 2, .pp = 2, .dspp = 2,
  79                                   .caps = MDP_LM_CAP_DISPLAY, },
  80                                 { .id = 3, .pp = -1, .dspp = -1,
  81                                   .caps = MDP_LM_CAP_WB },
  82                                 { .id = 4, .pp = -1, .dspp = -1,
  83                                   .caps = MDP_LM_CAP_WB },
  84                              },
  85                 .nb_stages = 5,
  86         },
  87         .dspp = {
  88                 .count = 3,
  89                 .base = { 0x04500, 0x04900, 0x04d00 },
  90         },
  91         .pp = {
  92                 .count = 3,
  93                 .base = { 0x21a00, 0x21b00, 0x21c00 },
  94         },
  95         .intf = {
  96                 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
  97                 .connect = {
  98                         [0] = INTF_eDP,
  99                         [1] = INTF_DSI,
 100                         [2] = INTF_DSI,
 101                         [3] = INTF_HDMI,
 102                 },
 103         },
 104         .max_clk = 200000000,
 105 };
 106
 107 const struct mdp5_cfg_hw msm8x74v2_config = {
 108         .name = "msm8x74",
 109         .mdp = {
 110                 .count = 1,
 111                 .caps = MDP_CAP_SMP |
 112                         0,
 113         },
 114         .smp = {
 115                 .mmb_count = 22,
 116                 .mmb_size = 4096,
 117                 .clients = {
 118                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
 119                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 120                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
 121                 },
 122         },
 123         .ctl = {
 124                 .count = 5,
 125                 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
 126                 .flush_hw_mask = 0x0003ffff,
 127         },
 128         .pipe_vig = {
 129                 .count = 3,
 130                 .base = { 0x01100, 0x01500, 0x01900 },
 131                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 132                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 133                                 MDP_PIPE_CAP_DECIMATION,
 134         },
 135         .pipe_rgb = {
 136                 .count = 3,
 137                 .base = { 0x01d00, 0x02100, 0x02500 },
 138                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 139                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
 140         },
 141         .pipe_dma = {
 142                 .count = 2,
 143                 .base = { 0x02900, 0x02d00 },
 144                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 145         },
 146         .lm = {
 147                 .count = 5,
 148                 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
 149                 .instances = {
 150                                 { .id = 0, .pp = 0, .dspp = 0,
 151                                   .caps = MDP_LM_CAP_DISPLAY, },
 152                                 { .id = 1, .pp = 1, .dspp = 1,
 153                                   .caps = MDP_LM_CAP_DISPLAY, },
 154                                 { .id = 2, .pp = 2, .dspp = 2,
 155                                   .caps = MDP_LM_CAP_DISPLAY, },
 156                                 { .id = 3, .pp = -1, .dspp = -1,
 157                                   .caps = MDP_LM_CAP_WB, },
 158                                 { .id = 4, .pp = -1, .dspp = -1,
 159                                   .caps = MDP_LM_CAP_WB, },
 160                              },
 161                 .nb_stages = 5,
 162                 .max_width = 2048,
 163                 .max_height = 0xFFFF,
 164         },
 165         .dspp = {
 166                 .count = 3,
 167                 .base = { 0x04500, 0x04900, 0x04d00 },
 168         },
 169         .ad = {
 170                 .count = 2,
 171                 .base = { 0x13000, 0x13200 },
 172         },
 173         .pp = {
 174                 .count = 3,
 175                 .base = { 0x12c00, 0x12d00, 0x12e00 },
 176         },
 177         .intf = {
 178                 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
 179                 .connect = {
 180                         [0] = INTF_eDP,
 181                         [1] = INTF_DSI,
 182                         [2] = INTF_DSI,
 183                         [3] = INTF_HDMI,
 184                 },
 185         },
 186         .max_clk = 200000000,
 187 };
 188
 189 const struct mdp5_cfg_hw apq8084_config = {
 190         .name = "apq8084",
 191         .mdp = {
 192                 .count = 1,
 193                 .caps = MDP_CAP_SMP |
 194                         MDP_CAP_SRC_SPLIT |
 195                         0,
 196         },
 197         .smp = {
 198                 .mmb_count = 44,
 199                 .mmb_size = 8192,
 200                 .clients = {
 201                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
 202                         [SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
 203                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 204                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
 205                         [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
 206                 },
 207                 .reserved_state[0] = GENMASK(7, 0),     /* first 8 MMBs */
 208                 .reserved = {
 209                         /* Two SMP blocks are statically tied to RGB pipes: */
 210                         [16] = 2, [17] = 2, [18] = 2, [22] = 2,
 211                 },
 212         },
 213         .ctl = {
 214                 .count = 5,
 215                 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
 216                 .flush_hw_mask = 0x003fffff,
 217         },
 218         .pipe_vig = {
 219                 .count = 4,
 220                 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
 221                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 222                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 223                                 MDP_PIPE_CAP_DECIMATION,
 224         },
 225         .pipe_rgb = {
 226                 .count = 4,
 227                 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
 228                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 229                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
 230         },
 231         .pipe_dma = {
 232                 .count = 2,
 233                 .base = { 0x03100, 0x03500 },
 234                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 235         },
 236         .lm = {
 237                 .count = 6,
 238                 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
 239                 .instances = {
 240                                 { .id = 0, .pp = 0, .dspp = 0,
 241                                   .caps = MDP_LM_CAP_DISPLAY |
 242                                           MDP_LM_CAP_PAIR, },
 243                                 { .id = 1, .pp = 1, .dspp = 1,
 244                                   .caps = MDP_LM_CAP_DISPLAY, },
 245                                 { .id = 2, .pp = 2, .dspp = 2,
 246                                   .caps = MDP_LM_CAP_DISPLAY |
 247                                           MDP_LM_CAP_PAIR, },
 248                                 { .id = 3, .pp = -1, .dspp = -1,
 249                                   .caps = MDP_LM_CAP_WB, },
 250                                 { .id = 4, .pp = -1, .dspp = -1,
 251                                   .caps = MDP_LM_CAP_WB, },
 252                                 { .id = 5, .pp = 3, .dspp = 3,
 253                                   .caps = MDP_LM_CAP_DISPLAY, },
 254                              },
 255                 .nb_stages = 5,
 256                 .max_width = 2048,
 257                 .max_height = 0xFFFF,
 258         },
 259         .dspp = {
 260                 .count = 4,
 261                 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
 262
 263         },
 264         .ad = {
 265                 .count = 3,
 266                 .base = { 0x13400, 0x13600, 0x13800 },
 267         },
 268         .pp = {
 269                 .count = 4,
 270                 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
 271         },
 272         .intf = {
 273                 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
 274                 .connect = {
 275                         [0] = INTF_eDP,
 276                         [1] = INTF_DSI,
 277                         [2] = INTF_DSI,
 278                         [3] = INTF_HDMI,
 279                 },
 280         },
 281         .max_clk = 320000000,
 282 };
 283
 284 const struct mdp5_cfg_hw msm8x16_config = {
 285         .name = "msm8x16",
 286         .mdp = {
 287                 .count = 1,
 288                 .base = { 0x0 },
 289                 .caps = MDP_CAP_SMP |
 290                         0,
 291         },
 292         .smp = {
 293                 .mmb_count = 8,
 294                 .mmb_size = 8192,
 295                 .clients = {
 296                         [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
 297                         [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
 298                 },
 299         },
 300         .ctl = {
 301                 .count = 5,
 302                 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 303                 .flush_hw_mask = 0x4003ffff,
 304         },
 305         .pipe_vig = {
 306                 .count = 1,
 307                 .base = { 0x04000 },
 308                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 309                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 310                                 MDP_PIPE_CAP_DECIMATION,
 311         },
 312         .pipe_rgb = {
 313                 .count = 2,
 314                 .base = { 0x14000, 0x16000 },
 315                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 316                                 MDP_PIPE_CAP_DECIMATION,
 317         },
 318         .pipe_dma = {
 319                 .count = 1,
 320                 .base = { 0x24000 },
 321                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 322         },
 323         .lm = {
 324                 .count = 2, /* LM0 and LM3 */
 325                 .base = { 0x44000, 0x47000 },
 326                 .instances = {
 327                                 { .id = 0, .pp = 0, .dspp = 0,
 328                                   .caps = MDP_LM_CAP_DISPLAY, },
 329                                 { .id = 3, .pp = -1, .dspp = -1,
 330                                   .caps = MDP_LM_CAP_WB },
 331                              },
 332                 .nb_stages = 8,
 333                 .max_width = 2048,
 334                 .max_height = 0xFFFF,
 335         },
 336         .dspp = {
 337                 .count = 1,
 338                 .base = { 0x54000 },
 339
 340         },
 341         .intf = {
 342                 .base = { 0x00000, 0x6a800 },
 343                 .connect = {
 344                         [0] = INTF_DISABLED,
 345                         [1] = INTF_DSI,
 346                 },
 347         },
 348         .max_clk = 320000000,
 349 };
 350
 351 const struct mdp5_cfg_hw msm8x94_config = {
 352         .name = "msm8x94",
 353         .mdp = {
 354                 .count = 1,
 355                 .caps = MDP_CAP_SMP |
 356                         MDP_CAP_SRC_SPLIT |
 357                         0,
 358         },
 359         .smp = {
 360                 .mmb_count = 44,
 361                 .mmb_size = 8192,
 362                 .clients = {
 363                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
 364                         [SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
 365                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 366                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
 367                         [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
 368                 },
 369                 .reserved_state[0] = GENMASK(23, 0),    /* first 24 MMBs */
 370                 .reserved = {
 371                          [1] = 1,  [4] = 1,  [7] = 1, [19] = 1,
 372                         [16] = 5, [17] = 5, [18] = 5, [22] = 5,
 373                 },
 374         },
 375         .ctl = {
 376                 .count = 5,
 377                 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 378                 .flush_hw_mask = 0xf0ffffff,
 379         },
 380         .pipe_vig = {
 381                 .count = 4,
 382                 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
 383                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 384                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 385                                 MDP_PIPE_CAP_DECIMATION,
 386         },
 387         .pipe_rgb = {
 388                 .count = 4,
 389                 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
 390                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 391                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
 392         },
 393         .pipe_dma = {
 394                 .count = 2,
 395                 .base = { 0x24000, 0x26000 },
 396                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 397         },
 398         .lm = {
 399                 .count = 6,
 400                 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
 401                 .instances = {
 402                                 { .id = 0, .pp = 0, .dspp = 0,
 403                                   .caps = MDP_LM_CAP_DISPLAY |
 404                                           MDP_LM_CAP_PAIR, },
 405                                 { .id = 1, .pp = 1, .dspp = 1,
 406                                   .caps = MDP_LM_CAP_DISPLAY, },
 407                                 { .id = 2, .pp = 2, .dspp = 2,
 408                                   .caps = MDP_LM_CAP_DISPLAY |
 409                                           MDP_LM_CAP_PAIR, },
 410                                 { .id = 3, .pp = -1, .dspp = -1,
 411                                   .caps = MDP_LM_CAP_WB, },
 412                                 { .id = 4, .pp = -1, .dspp = -1,
 413                                   .caps = MDP_LM_CAP_WB, },
 414                                 { .id = 5, .pp = 3, .dspp = 3,
 415                                   .caps = MDP_LM_CAP_DISPLAY, },
 416                              },
 417                 .nb_stages = 8,
 418                 .max_width = 2048,
 419                 .max_height = 0xFFFF,
 420         },
 421         .dspp = {
 422                 .count = 4,
 423                 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
 424
 425         },
 426         .ad = {
 427                 .count = 3,
 428                 .base = { 0x78000, 0x78800, 0x79000 },
 429         },
 430         .pp = {
 431                 .count = 4,
 432                 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
 433         },
 434         .intf = {
 435                 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
 436                 .connect = {
 437                         [0] = INTF_DISABLED,
 438                         [1] = INTF_DSI,
 439                         [2] = INTF_DSI,
 440                         [3] = INTF_HDMI,
 441                 },
 442         },
 443         .max_clk = 400000000,
 444 };
 445
 446 const struct mdp5_cfg_hw msm8x96_config = {
 447         .name = "msm8x96",
 448         .mdp = {
 449                 .count = 1,
 450                 .caps = MDP_CAP_DSC |
 451                         MDP_CAP_CDM |
 452                         MDP_CAP_SRC_SPLIT |
 453                         0,
 454         },
 455         .ctl = {
 456                 .count = 5,
 457                 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 458                 .flush_hw_mask = 0xf4ffffff,
 459         },
 460         .pipe_vig = {
 461                 .count = 4,
 462                 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
 463                 .caps = MDP_PIPE_CAP_HFLIP      |
 464                         MDP_PIPE_CAP_VFLIP      |
 465                         MDP_PIPE_CAP_SCALE      |
 466                         MDP_PIPE_CAP_CSC        |
 467                         MDP_PIPE_CAP_DECIMATION |
 468                         MDP_PIPE_CAP_SW_PIX_EXT |
 469                         0,
 470         },
 471         .pipe_rgb = {
 472                 .count = 4,
 473                 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
 474                 .caps = MDP_PIPE_CAP_HFLIP      |
 475                         MDP_PIPE_CAP_VFLIP      |
 476                         MDP_PIPE_CAP_SCALE      |
 477                         MDP_PIPE_CAP_DECIMATION |
 478                         MDP_PIPE_CAP_SW_PIX_EXT |
 479                         0,
 480         },
 481         .pipe_dma = {
 482                 .count = 2,
 483                 .base = { 0x24000, 0x26000 },
 484                 .caps = MDP_PIPE_CAP_HFLIP      |
 485                         MDP_PIPE_CAP_VFLIP      |
 486                         MDP_PIPE_CAP_SW_PIX_EXT |
 487                         0,
 488         },
 489         .pipe_cursor = {
 490                 .count = 2,
 491                 .base = { 0x34000, 0x36000 },
 492                 .caps = MDP_PIPE_CAP_HFLIP      |
 493                         MDP_PIPE_CAP_VFLIP      |
 494                         MDP_PIPE_CAP_SW_PIX_EXT |
 495                         MDP_PIPE_CAP_CURSOR     |
 496                         0,
 497         },
 498
 499         .lm = {
 500                 .count = 6,
 501                 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
 502                 .instances = {
 503                                 { .id = 0, .pp = 0, .dspp = 0,
 504                                   .caps = MDP_LM_CAP_DISPLAY |
 505                                           MDP_LM_CAP_PAIR, },
 506                                 { .id = 1, .pp = 1, .dspp = 1,
 507                                   .caps = MDP_LM_CAP_DISPLAY, },
 508                                 { .id = 2, .pp = 2, .dspp = -1,
 509                                   .caps = MDP_LM_CAP_DISPLAY |
 510                                           MDP_LM_CAP_PAIR, },
 511                                 { .id = 3, .pp = -1, .dspp = -1,
 512                                   .caps = MDP_LM_CAP_WB, },
 513                                 { .id = 4, .pp = -1, .dspp = -1,
 514                                   .caps = MDP_LM_CAP_WB, },
 515                                 { .id = 5, .pp = 3, .dspp = -1,
 516                                   .caps = MDP_LM_CAP_DISPLAY, },
 517                              },
 518                 .nb_stages = 8,
 519                 .max_width = 2560,
 520                 .max_height = 0xFFFF,
 521         },
 522         .dspp = {
 523                 .count = 2,
 524                 .base = { 0x54000, 0x56000 },
 525         },
 526         .ad = {
 527                 .count = 3,
 528                 .base = { 0x78000, 0x78800, 0x79000 },
 529         },
 530         .pp = {
 531                 .count = 4,
 532                 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
 533         },
 534         .cdm = {
 535                 .count = 1,
 536                 .base = { 0x79200 },
 537         },
 538         .dsc = {
 539                 .count = 2,
 540                 .base = { 0x80000, 0x80400 },
 541         },
 542         .intf = {
 543                 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
 544                 .connect = {
 545                         [0] = INTF_DISABLED,
 546                         [1] = INTF_DSI,
 547                         [2] = INTF_DSI,
 548                         [3] = INTF_HDMI,
 549                 },
 550         },
 551         .max_clk = 412500000,
 552 };
 553
 554 static const struct mdp5_cfg_handler cfg_handlers[] = {
 555         { .revision = 0, .config = { .hw = &msm8x74v1_config } },
 556         { .revision = 2, .config = { .hw = &msm8x74v2_config } },
 557         { .revision = 3, .config = { .hw = &apq8084_config } },
 558         { .revision = 6, .config = { .hw = &msm8x16_config } },
 559         { .revision = 9, .config = { .hw = &msm8x94_config } },
 560         { .revision = 7, .config = { .hw = &msm8x96_config } },
 561 };
 562
 563 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
 564
 565 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
 566 {
 567         return cfg_handler->config.hw;
 568 }
 569
 570 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
 571 {
 572         return &cfg_handler->config;
 573 }
 574
 575 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
 576 {
 577         return cfg_handler->revision;
 578 }
 579
 580 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
 581 {
 582         kfree(cfg_handler);
 583 }
 584
 585 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
 586                 uint32_t major, uint32_t minor)
 587 {
 588         struct drm_device *dev = mdp5_kms->dev;
 589         struct platform_device *pdev = to_platform_device(dev->dev);
 590         struct mdp5_cfg_handler *cfg_handler;
 591         struct mdp5_cfg_platform *pconfig;
 592         int i, ret = 0;
 593
 594         cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
 595         if (unlikely(!cfg_handler)) {
 596                 ret = -ENOMEM;
 597                 goto fail;
 598         }
 599
 600         if (major != 1) {
 601                 dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
 602                                 major, minor);
 603                 ret = -ENXIO;
 604                 goto fail;
 605         }
 606
 607         /* only after mdp5_cfg global pointer's init can we access the hw */
 608         for (i = 0; i < ARRAY_SIZE(cfg_handlers); i++) {
 609                 if (cfg_handlers[i].revision != minor)
 610                         continue;
 611                 mdp5_cfg = cfg_handlers[i].config.hw;
 612
 613                 break;
 614         }
 615         if (unlikely(!mdp5_cfg)) {
 616                 dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
 617                                 major, minor);
 618                 ret = -ENXIO;
 619                 goto fail;
 620         }
 621
 622         cfg_handler->revision = minor;
 623         cfg_handler->config.hw = mdp5_cfg;
 624
 625         pconfig = mdp5_get_config(pdev);
 626         memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
 627
 628         DBG("MDP5: %s hw config selected", mdp5_cfg->name);
 629
 630         return cfg_handler;
 631
 632 fail:
 633         if (cfg_handler)
 634                 mdp5_cfg_destroy(cfg_handler);
 635
 636         return NULL;
 637 }
 638
 639 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
 640 {
 641         static struct mdp5_cfg_platform config = {};
 642
 643         config.iommu = iommu_domain_alloc(&platform_bus_type);
 644         if (config.iommu) {
 645                 config.iommu->geometry.aperture_start = 0x1000;
 646                 config.iommu->geometry.aperture_end = 0xffffffff;
 647         }
 648
 649         return &config;
 650 }