2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/of_irq.h>
26 static const char *iommu_ports[] = {
30 static int mdp5_hw_init(struct msm_kms *kms)
32 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
33 struct platform_device *pdev = mdp5_kms->pdev;
36 pm_runtime_get_sync(&pdev->dev);
37 mdp5_enable(mdp5_kms);
39 /* Magic unknown register writes:
41 * W VBIF:0x004 00000001 (mdss_mdp.c:839)
42 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
43 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
44 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
45 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
46 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
47 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
48 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
49 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
51 * Downstream fbdev driver gets these register offsets/values
52 * from DT.. not really sure what these registers are or if
53 * different values for different boards/SoC's, etc. I guess
54 * they are the golden registers.
56 * Not setting these does not seem to cause any problem. But
57 * we may be getting lucky with the bootloader initializing
58 * them for us. OTOH, if we can always count on the bootloader
59 * setting the golden registers, then perhaps we don't need to
63 spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
64 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
65 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
67 mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
69 mdp5_disable(mdp5_kms);
70 pm_runtime_put_sync(&pdev->dev);
75 struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s)
77 struct msm_drm_private *priv = s->dev->dev_private;
78 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
79 struct msm_kms_state *state = to_kms_state(s);
80 struct mdp5_state *new_state;
86 ret = drm_modeset_lock(&mdp5_kms->state_lock, s->acquire_ctx);
90 new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
92 return ERR_PTR(-ENOMEM);
95 new_state->hwpipe = mdp5_kms->state->hwpipe;
97 new_state->smp = mdp5_kms->state->smp;
99 state->state = new_state;
104 static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state *state)
106 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
107 swap(to_kms_state(state)->state, mdp5_kms->state);
110 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
112 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
114 mdp5_enable(mdp5_kms);
117 mdp5_smp_prepare_commit(mdp5_kms->smp, &mdp5_kms->state->smp);
120 static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
122 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
125 mdp5_smp_complete_commit(mdp5_kms->smp, &mdp5_kms->state->smp);
127 mdp5_disable(mdp5_kms);
130 static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms,
131 struct drm_crtc *crtc)
133 mdp5_crtc_wait_for_commit_done(crtc);
136 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
137 struct drm_encoder *encoder)
142 static int mdp5_set_split_display(struct msm_kms *kms,
143 struct drm_encoder *encoder,
144 struct drm_encoder *slave_encoder,
148 return mdp5_cmd_encoder_set_split_display(encoder,
151 return mdp5_encoder_set_split_display(encoder, slave_encoder);
154 static void mdp5_kms_destroy(struct msm_kms *kms)
156 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
157 struct msm_gem_address_space *aspace = mdp5_kms->aspace;
160 for (i = 0; i < mdp5_kms->num_hwpipes; i++)
161 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);
164 aspace->mmu->funcs->detach(aspace->mmu,
165 iommu_ports, ARRAY_SIZE(iommu_ports));
166 msm_gem_address_space_destroy(aspace);
170 #ifdef CONFIG_DEBUG_FS
171 static int smp_show(struct seq_file *m, void *arg)
173 struct drm_info_node *node = (struct drm_info_node *) m->private;
174 struct drm_device *dev = node->minor->dev;
175 struct msm_drm_private *priv = dev->dev_private;
176 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
177 struct drm_printer p = drm_seq_file_printer(m);
179 if (!mdp5_kms->smp) {
180 drm_printf(&p, "no SMP pool\n");
184 mdp5_smp_dump(mdp5_kms->smp, &p);
189 static struct drm_info_list mdp5_debugfs_list[] = {
193 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
195 struct drm_device *dev = minor->dev;
198 ret = drm_debugfs_create_files(mdp5_debugfs_list,
199 ARRAY_SIZE(mdp5_debugfs_list),
200 minor->debugfs_root, minor);
203 dev_err(dev->dev, "could not install mdp5_debugfs_list\n");
210 static void mdp5_kms_debugfs_cleanup(struct msm_kms *kms, struct drm_minor *minor)
212 drm_debugfs_remove_files(mdp5_debugfs_list,
213 ARRAY_SIZE(mdp5_debugfs_list), minor);
217 static const struct mdp_kms_funcs kms_funcs = {
219 .hw_init = mdp5_hw_init,
220 .irq_preinstall = mdp5_irq_preinstall,
221 .irq_postinstall = mdp5_irq_postinstall,
222 .irq_uninstall = mdp5_irq_uninstall,
224 .enable_vblank = mdp5_enable_vblank,
225 .disable_vblank = mdp5_disable_vblank,
226 .swap_state = mdp5_swap_state,
227 .prepare_commit = mdp5_prepare_commit,
228 .complete_commit = mdp5_complete_commit,
229 .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done,
230 .get_format = mdp_get_format,
231 .round_pixclk = mdp5_round_pixclk,
232 .set_split_display = mdp5_set_split_display,
233 .destroy = mdp5_kms_destroy,
234 #ifdef CONFIG_DEBUG_FS
235 .debugfs_init = mdp5_kms_debugfs_init,
236 .debugfs_cleanup = mdp5_kms_debugfs_cleanup,
239 .set_irqmask = mdp5_set_irqmask,
242 int mdp5_disable(struct mdp5_kms *mdp5_kms)
246 clk_disable_unprepare(mdp5_kms->ahb_clk);
247 clk_disable_unprepare(mdp5_kms->axi_clk);
248 clk_disable_unprepare(mdp5_kms->core_clk);
249 if (mdp5_kms->lut_clk)
250 clk_disable_unprepare(mdp5_kms->lut_clk);
255 int mdp5_enable(struct mdp5_kms *mdp5_kms)
259 clk_prepare_enable(mdp5_kms->ahb_clk);
260 clk_prepare_enable(mdp5_kms->axi_clk);
261 clk_prepare_enable(mdp5_kms->core_clk);
262 if (mdp5_kms->lut_clk)
263 clk_prepare_enable(mdp5_kms->lut_clk);
268 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
269 enum mdp5_intf_type intf_type, int intf_num,
270 enum mdp5_intf_mode intf_mode, struct mdp5_ctl *ctl)
272 struct drm_device *dev = mdp5_kms->dev;
273 struct msm_drm_private *priv = dev->dev_private;
274 struct drm_encoder *encoder;
275 struct mdp5_interface intf = {
281 if ((intf_type == INTF_DSI) &&
282 (intf_mode == MDP5_INTF_DSI_MODE_COMMAND))
283 encoder = mdp5_cmd_encoder_init(dev, &intf, ctl);
285 encoder = mdp5_encoder_init(dev, &intf, ctl);
287 if (IS_ERR(encoder)) {
288 dev_err(dev->dev, "failed to construct encoder\n");
292 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
293 priv->encoders[priv->num_encoders++] = encoder;
298 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
300 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
301 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
304 for (i = 0; i < intf_cnt; i++) {
305 if (intfs[i] == INTF_DSI) {
316 static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
318 struct drm_device *dev = mdp5_kms->dev;
319 struct msm_drm_private *priv = dev->dev_private;
320 const struct mdp5_cfg_hw *hw_cfg =
321 mdp5_cfg_get_hw_config(mdp5_kms->cfg);
322 enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num];
323 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
324 struct mdp5_ctl *ctl;
325 struct drm_encoder *encoder;
335 ctl = mdp5_ctlm_request(ctlm, intf_num);
341 encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num,
342 MDP5_INTF_MODE_NONE, ctl);
343 if (IS_ERR(encoder)) {
344 ret = PTR_ERR(encoder);
348 ret = msm_edp_modeset_init(priv->edp, dev, encoder);
354 ctl = mdp5_ctlm_request(ctlm, intf_num);
360 encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num,
361 MDP5_INTF_MODE_NONE, ctl);
362 if (IS_ERR(encoder)) {
363 ret = PTR_ERR(encoder);
367 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
371 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf_num);
372 struct drm_encoder *dsi_encs[MSM_DSI_ENCODER_NUM];
373 enum mdp5_intf_mode mode;
376 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {
377 dev_err(dev->dev, "failed to find dsi from intf %d\n",
383 if (!priv->dsi[dsi_id])
386 ctl = mdp5_ctlm_request(ctlm, intf_num);
392 for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) {
393 mode = (i == MSM_DSI_CMD_ENCODER_ID) ?
394 MDP5_INTF_DSI_MODE_COMMAND :
395 MDP5_INTF_DSI_MODE_VIDEO;
396 dsi_encs[i] = construct_encoder(mdp5_kms, INTF_DSI,
397 intf_num, mode, ctl);
398 if (IS_ERR(dsi_encs[i])) {
399 ret = PTR_ERR(dsi_encs[i]);
404 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, dsi_encs);
408 dev_err(dev->dev, "unknown intf: %d\n", intf_type);
416 static int modeset_init(struct mdp5_kms *mdp5_kms)
418 struct drm_device *dev = mdp5_kms->dev;
419 struct msm_drm_private *priv = dev->dev_private;
420 const struct mdp5_cfg_hw *hw_cfg;
423 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
425 /* Construct planes equaling the number of hw pipes, and CRTCs
426 * for the N layer-mixers (LM). The first N planes become primary
427 * planes for the CRTCs, with the remainder as overlay planes:
429 for (i = 0; i < mdp5_kms->num_hwpipes; i++) {
430 bool primary = i < mdp5_cfg->lm.count;
431 struct drm_plane *plane;
432 struct drm_crtc *crtc;
434 plane = mdp5_plane_init(dev, primary);
436 ret = PTR_ERR(plane);
437 dev_err(dev->dev, "failed to construct plane %d (%d)\n", i, ret);
440 priv->planes[priv->num_planes++] = plane;
445 crtc = mdp5_crtc_init(dev, plane, i);
448 dev_err(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
451 priv->crtcs[priv->num_crtcs++] = crtc;
454 /* Construct encoders and modeset initialize connector devices
455 * for each external display interface.
457 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
458 ret = modeset_init_intf(mdp5_kms, i);
469 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,
470 u32 *major, u32 *minor)
474 mdp5_enable(mdp5_kms);
475 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);
476 mdp5_disable(mdp5_kms);
478 *major = FIELD(version, MDP5_HW_VERSION_MAJOR);
479 *minor = FIELD(version, MDP5_HW_VERSION_MINOR);
481 DBG("MDP5 version v%d.%d", *major, *minor);
484 static int get_clk(struct platform_device *pdev, struct clk **clkp,
485 const char *name, bool mandatory)
487 struct device *dev = &pdev->dev;
488 struct clk *clk = devm_clk_get(dev, name);
489 if (IS_ERR(clk) && mandatory) {
490 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
494 DBG("skipping %s", name);
501 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
503 struct drm_device *dev = crtc->dev;
504 struct drm_encoder *encoder;
506 drm_for_each_encoder(encoder, dev)
507 if (encoder->crtc == crtc)
513 static int mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe,
514 unsigned int flags, int *vpos, int *hpos,
515 ktime_t *stime, ktime_t *etime,
516 const struct drm_display_mode *mode)
518 struct msm_drm_private *priv = dev->dev_private;
519 struct drm_crtc *crtc;
520 struct drm_encoder *encoder;
521 int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
524 crtc = priv->crtcs[pipe];
526 DRM_ERROR("Invalid crtc %d\n", pipe);
530 encoder = get_encoder_from_crtc(crtc);
532 DRM_ERROR("no encoder found for crtc %d\n", pipe);
536 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
538 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
539 vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
542 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
543 * the end of VFP. Translate the porch values relative to the line
547 vactive_start = vsw + vbp + 1;
549 vactive_end = vactive_start + mode->crtc_vdisplay;
551 /* last scan line before VSYNC */
552 vfp_end = mode->crtc_vtotal;
555 *stime = ktime_get();
557 line = mdp5_encoder_get_linecount(encoder);
559 if (line < vactive_start) {
560 line -= vactive_start;
561 ret |= DRM_SCANOUTPOS_IN_VBLANK;
562 } else if (line > vactive_end) {
563 line = line - vfp_end - vactive_start;
564 ret |= DRM_SCANOUTPOS_IN_VBLANK;
566 line -= vactive_start;
573 *etime = ktime_get();
578 static int mdp5_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
580 struct timeval *vblank_time,
583 struct msm_drm_private *priv = dev->dev_private;
584 struct drm_crtc *crtc;
586 if (pipe < 0 || pipe >= priv->num_crtcs) {
587 DRM_ERROR("Invalid crtc %d\n", pipe);
591 crtc = priv->crtcs[pipe];
593 DRM_ERROR("Invalid crtc %d\n", pipe);
597 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
602 static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
604 struct msm_drm_private *priv = dev->dev_private;
605 struct drm_crtc *crtc;
606 struct drm_encoder *encoder;
608 if (pipe < 0 || pipe >= priv->num_crtcs)
611 crtc = priv->crtcs[pipe];
615 encoder = get_encoder_from_crtc(crtc);
619 return mdp5_encoder_get_framecount(encoder);
622 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
624 struct msm_drm_private *priv = dev->dev_private;
625 struct platform_device *pdev;
626 struct mdp5_kms *mdp5_kms;
627 struct mdp5_cfg *config;
629 struct msm_gem_address_space *aspace;
632 /* priv->kms would have been populated by the MDP5 driver */
637 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
639 mdp_kms_init(&mdp5_kms->base, &kms_funcs);
641 pdev = mdp5_kms->pdev;
643 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
646 dev_err(&pdev->dev, "failed to get irq: %d\n", ret);
652 config = mdp5_cfg_get_config(mdp5_kms->cfg);
654 /* make sure things are off before attaching iommu (bootloader could
655 * have left things on, in which case we'll start getting faults if
658 mdp5_enable(mdp5_kms);
659 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
660 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
661 !config->hw->intf.base[i])
663 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
665 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);
667 mdp5_disable(mdp5_kms);
670 if (config->platform.iommu) {
671 aspace = msm_gem_address_space_create(&pdev->dev,
672 config->platform.iommu, "mdp5");
673 if (IS_ERR(aspace)) {
674 ret = PTR_ERR(aspace);
678 mdp5_kms->aspace = aspace;
680 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
681 ARRAY_SIZE(iommu_ports));
683 dev_err(&pdev->dev, "failed to attach iommu: %d\n",
689 "no iommu, fallback to phys contig buffers for scanout\n");
693 mdp5_kms->id = msm_register_address_space(dev, aspace);
694 if (mdp5_kms->id < 0) {
696 dev_err(&pdev->dev, "failed to register mdp5 iommu: %d\n", ret);
700 ret = modeset_init(mdp5_kms);
702 dev_err(&pdev->dev, "modeset_init failed: %d\n", ret);
706 dev->mode_config.min_width = 0;
707 dev->mode_config.min_height = 0;
708 dev->mode_config.max_width = 0xffff;
709 dev->mode_config.max_height = 0xffff;
711 dev->driver->get_vblank_timestamp = mdp5_get_vblank_timestamp;
712 dev->driver->get_scanout_position = mdp5_get_scanoutpos;
713 dev->driver->get_vblank_counter = mdp5_get_vblank_counter;
714 dev->max_vblank_count = 0xffffffff;
715 dev->vblank_disable_immediate = true;
720 mdp5_kms_destroy(kms);
724 static void mdp5_destroy(struct platform_device *pdev)
726 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
729 mdp5_ctlm_destroy(mdp5_kms->ctlm);
731 mdp5_smp_destroy(mdp5_kms->smp);
733 mdp5_cfg_destroy(mdp5_kms->cfg);
735 if (mdp5_kms->rpm_enabled)
736 pm_runtime_disable(&pdev->dev);
738 kfree(mdp5_kms->state);
741 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
742 const enum mdp5_pipe *pipes, const uint32_t *offsets,
745 struct drm_device *dev = mdp5_kms->dev;
748 for (i = 0; i < cnt; i++) {
749 struct mdp5_hw_pipe *hwpipe;
751 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps);
752 if (IS_ERR(hwpipe)) {
753 ret = PTR_ERR(hwpipe);
754 dev_err(dev->dev, "failed to construct pipe for %s (%d)\n",
755 pipe2name(pipes[i]), ret);
758 hwpipe->idx = mdp5_kms->num_hwpipes;
759 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;
765 static int hwpipe_init(struct mdp5_kms *mdp5_kms)
767 static const enum mdp5_pipe rgb_planes[] = {
768 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
770 static const enum mdp5_pipe vig_planes[] = {
771 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
773 static const enum mdp5_pipe dma_planes[] = {
774 SSPP_DMA0, SSPP_DMA1,
776 const struct mdp5_cfg_hw *hw_cfg;
779 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
781 /* Construct RGB pipes: */
782 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,
783 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);
787 /* Construct video (VIG) pipes: */
788 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
789 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);
793 /* Construct DMA pipes: */
794 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,
795 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);
802 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
804 struct msm_drm_private *priv = dev->dev_private;
805 struct mdp5_kms *mdp5_kms;
806 struct mdp5_cfg *config;
810 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);
816 platform_set_drvdata(pdev, mdp5_kms);
818 spin_lock_init(&mdp5_kms->resource_lock);
821 mdp5_kms->pdev = pdev;
823 drm_modeset_lock_init(&mdp5_kms->state_lock);
824 mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
825 if (!mdp5_kms->state) {
830 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
831 if (IS_ERR(mdp5_kms->mmio)) {
832 ret = PTR_ERR(mdp5_kms->mmio);
836 /* mandatory clocks: */
837 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk", true);
840 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true);
843 ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true);
846 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk", true);
850 /* optional clocks: */
851 get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk", false);
853 /* we need to set a default rate before enabling. Set a safe
854 * rate first, then figure out hw revision, and then set a
857 clk_set_rate(mdp5_kms->core_clk, 200000000);
859 pm_runtime_enable(&pdev->dev);
860 mdp5_kms->rpm_enabled = true;
862 read_mdp_hw_revision(mdp5_kms, &major, &minor);
864 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
865 if (IS_ERR(mdp5_kms->cfg)) {
866 ret = PTR_ERR(mdp5_kms->cfg);
867 mdp5_kms->cfg = NULL;
871 config = mdp5_cfg_get_config(mdp5_kms->cfg);
872 mdp5_kms->caps = config->hw->mdp.caps;
874 /* TODO: compute core clock rate at runtime */
875 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
878 * Some chipsets have a Shared Memory Pool (SMP), while others
879 * have dedicated latency buffering per source pipe instead;
880 * this section initializes the SMP:
882 if (mdp5_kms->caps & MDP_CAP_SMP) {
883 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);
884 if (IS_ERR(mdp5_kms->smp)) {
885 ret = PTR_ERR(mdp5_kms->smp);
886 mdp5_kms->smp = NULL;
891 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
892 if (IS_ERR(mdp5_kms->ctlm)) {
893 ret = PTR_ERR(mdp5_kms->ctlm);
894 mdp5_kms->ctlm = NULL;
898 ret = hwpipe_init(mdp5_kms);
902 /* set uninit-ed kms */
903 priv->kms = &mdp5_kms->base.base;
911 static int mdp5_bind(struct device *dev, struct device *master, void *data)
913 struct drm_device *ddev = dev_get_drvdata(master);
914 struct platform_device *pdev = to_platform_device(dev);
918 return mdp5_init(pdev, ddev);
921 static void mdp5_unbind(struct device *dev, struct device *master,
924 struct platform_device *pdev = to_platform_device(dev);
929 static const struct component_ops mdp5_ops = {
931 .unbind = mdp5_unbind,
934 static int mdp5_dev_probe(struct platform_device *pdev)
937 return component_add(&pdev->dev, &mdp5_ops);
940 static int mdp5_dev_remove(struct platform_device *pdev)
943 component_del(&pdev->dev, &mdp5_ops);
947 static const struct of_device_id mdp5_dt_match[] = {
948 { .compatible = "qcom,mdp5", },
949 /* to support downstream DT files */
950 { .compatible = "qcom,mdss_mdp", },
953 MODULE_DEVICE_TABLE(of, mdp5_dt_match);
955 static struct platform_driver mdp5_driver = {
956 .probe = mdp5_dev_probe,
957 .remove = mdp5_dev_remove,
960 .of_match_table = mdp5_dt_match,
964 void __init msm_mdp_register(void)
967 platform_driver_register(&mdp5_driver);
970 void __exit msm_mdp_unregister(void)
973 platform_driver_unregister(&mdp5_driver);