2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __MDP5_KMS_H__
19 #define __MDP5_KMS_H__
23 #include "mdp/mdp_kms.h"
24 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */
27 #include "mdp5_pipe.h"
35 struct drm_device *dev;
37 struct platform_device *pdev;
40 struct mdp5_hw_pipe *hwpipes[SSPP_MAX];
42 struct mdp5_cfg_handler *cfg;
43 uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */
46 * Global atomic state. Do not access directly, use mdp5_get_state()
48 struct mdp5_state *state;
49 struct drm_modeset_lock state_lock;
51 /* mapper-id used to request GEM buffer mapped for scanout: */
53 struct msm_gem_address_space *aspace;
56 struct mdp5_ctl_manager *ctlm;
58 /* io/register spaces: */
65 struct clk *vsync_clk;
68 * lock to protect access to global resources: ie., following register:
69 * - REG_MDP5_DISP_INTF_SEL
71 spinlock_t resource_lock;
75 struct mdp_irq error_handler;
77 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
79 /* Global atomic state for tracking resources that are shared across
80 * multiple kms objects (planes/crtcs/etc).
82 * For atomic updates which require modifying global state,
85 struct mdp5_hw_pipe_state hwpipe;
86 struct mdp5_smp_state smp;
89 struct mdp5_state *__must_check
90 mdp5_get_state(struct drm_atomic_state *s);
92 /* Atomic plane state. Subclasses the base drm_plane_state in order to
93 * track assigned hwpipe and hw specific state.
95 struct mdp5_plane_state {
96 struct drm_plane_state base;
98 struct mdp5_hw_pipe *hwpipe;
100 /* aligned with property */
101 uint8_t premultiplied;
105 /* assigned by crtc blender */
106 enum mdp_mixer_stage_id stage;
110 #define to_mdp5_plane_state(x) \
111 container_of(x, struct mdp5_plane_state, base)
113 enum mdp5_intf_mode {
114 MDP5_INTF_MODE_NONE = 0,
116 /* Modes used for DSI interface (INTF_DSI type): */
117 MDP5_INTF_DSI_MODE_VIDEO,
118 MDP5_INTF_DSI_MODE_COMMAND,
120 /* Modes used for WB interface (INTF_WB type): */
121 MDP5_INTF_WB_MODE_BLOCK,
122 MDP5_INTF_WB_MODE_LINE,
125 struct mdp5_interface {
126 int num; /* display interface number */
127 enum mdp5_intf_type type;
128 enum mdp5_intf_mode mode;
131 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
133 msm_writel(data, mdp5_kms->mmio + reg);
136 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
138 return msm_readl(mdp5_kms->mmio + reg);
141 static inline const char *stage2name(enum mdp_mixer_stage_id stage)
143 static const char *names[] = {
144 #define NAME(n) [n] = #n
145 NAME(STAGE_UNUSED), NAME(STAGE_BASE),
146 NAME(STAGE0), NAME(STAGE1), NAME(STAGE2),
147 NAME(STAGE3), NAME(STAGE4), NAME(STAGE6),
153 static inline const char *pipe2name(enum mdp5_pipe pipe)
155 static const char *names[] = {
156 #define NAME(n) [SSPP_ ## n] = #n
157 NAME(VIG0), NAME(VIG1), NAME(VIG2),
158 NAME(RGB0), NAME(RGB1), NAME(RGB2),
159 NAME(DMA0), NAME(DMA1),
160 NAME(VIG3), NAME(RGB3),
166 static inline int pipe2nclients(enum mdp5_pipe pipe)
179 static inline uint32_t intf2err(int intf_num)
182 case 0: return MDP5_IRQ_INTF0_UNDER_RUN;
183 case 1: return MDP5_IRQ_INTF1_UNDER_RUN;
184 case 2: return MDP5_IRQ_INTF2_UNDER_RUN;
185 case 3: return MDP5_IRQ_INTF3_UNDER_RUN;
190 #define GET_PING_PONG_ID(layer_mixer) ((layer_mixer == 5) ? 3 : layer_mixer)
191 static inline uint32_t intf2vblank(int lm, struct mdp5_interface *intf)
194 * In case of DSI Command Mode, the Ping Pong's read pointer IRQ
195 * acts as a Vblank signal. The Ping Pong buffer used is bound to
199 if ((intf->type == INTF_DSI) &&
200 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))
201 return MDP5_IRQ_PING_PONG_0_RD_PTR << GET_PING_PONG_ID(lm);
203 if (intf->type == INTF_WB)
204 return MDP5_IRQ_WB_2_DONE;
207 case 0: return MDP5_IRQ_INTF0_VSYNC;
208 case 1: return MDP5_IRQ_INTF1_VSYNC;
209 case 2: return MDP5_IRQ_INTF2_VSYNC;
210 case 3: return MDP5_IRQ_INTF3_VSYNC;
215 static inline uint32_t lm2ppdone(int lm)
217 return MDP5_IRQ_PING_PONG_0_DONE << GET_PING_PONG_ID(lm);
220 int mdp5_disable(struct mdp5_kms *mdp5_kms);
221 int mdp5_enable(struct mdp5_kms *mdp5_kms);
223 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
224 uint32_t old_irqmask);
225 void mdp5_irq_preinstall(struct msm_kms *kms);
226 int mdp5_irq_postinstall(struct msm_kms *kms);
227 void mdp5_irq_uninstall(struct msm_kms *kms);
228 irqreturn_t mdp5_irq(struct msm_kms *kms);
229 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
230 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
231 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
232 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
234 uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
235 void mdp5_plane_complete_commit(struct drm_plane *plane,
236 struct drm_plane_state *state);
237 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
238 struct drm_plane *mdp5_plane_init(struct drm_device *dev, bool primary);
240 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
242 int mdp5_crtc_get_lm(struct drm_crtc *crtc);
243 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
244 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
245 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
246 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
247 struct drm_plane *plane, int id);
249 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
250 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
251 int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
252 struct drm_encoder *slave_encoder);
253 int mdp5_encoder_get_linecount(struct drm_encoder *encoder);
254 u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);
256 #ifdef CONFIG_DRM_MSM_DSI
257 struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
258 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
259 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
260 struct drm_encoder *slave_encoder);
262 static inline struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
263 struct mdp5_interface *intf, struct mdp5_ctl *ctl)
265 return ERR_PTR(-EINVAL);
267 static inline int mdp5_cmd_encoder_set_split_display(
268 struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
274 #endif /* __MDP5_KMS_H__ */