2 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kthread.h>
20 #include <uapi/linux/sched/types.h>
21 #include <drm/drm_of.h>
24 #include "msm_debugfs.h"
25 #include "msm_fence.h"
33 * - 1.0.0 - initial interface
34 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
35 * - 1.2.0 - adds explicit fence support for submit ioctl
36 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
37 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
40 #define MSM_VERSION_MAJOR 1
41 #define MSM_VERSION_MINOR 3
42 #define MSM_VERSION_PATCHLEVEL 0
44 static const struct drm_mode_config_funcs mode_config_funcs = {
45 .fb_create = msm_framebuffer_create,
46 .output_poll_changed = drm_fb_helper_output_poll_changed,
47 .atomic_check = drm_atomic_helper_check,
48 .atomic_commit = drm_atomic_helper_commit,
51 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
52 .atomic_commit_tail = msm_atomic_commit_tail,
55 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
56 static bool reglog = false;
57 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
58 module_param(reglog, bool, 0600);
63 #ifdef CONFIG_DRM_FBDEV_EMULATION
64 static bool fbdev = true;
65 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
66 module_param(fbdev, bool, 0600);
69 static char *vram = "16m";
70 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
71 module_param(vram, charp, 0);
73 bool dumpstate = false;
74 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
75 module_param(dumpstate, bool, 0600);
77 static bool modeset = true;
78 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
79 module_param(modeset, bool, 0600);
85 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
87 struct property *prop;
89 struct clk_bulk_data *local;
90 int i = 0, ret, count;
92 count = of_property_count_strings(dev->of_node, "clock-names");
96 local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
101 of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
102 local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
104 devm_kfree(dev, local);
111 ret = devm_clk_bulk_get(dev, count, local);
114 for (i = 0; i < count; i++)
115 devm_kfree(dev, (void *) local[i].id);
116 devm_kfree(dev, local);
125 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
131 snprintf(n, sizeof(n), "%s_clk", name);
133 for (i = 0; bulk && i < count; i++) {
134 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
142 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
147 clk = devm_clk_get(&pdev->dev, name);
148 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
151 snprintf(name2, sizeof(name2), "%s_clk", name);
153 clk = devm_clk_get(&pdev->dev, name2);
155 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
156 "\"%s\" instead of \"%s\"\n", name, name2);
161 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
164 struct resource *res;
169 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
171 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
174 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
175 return ERR_PTR(-EINVAL);
178 size = resource_size(res);
180 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
182 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
183 return ERR_PTR(-ENOMEM);
187 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
192 void msm_writel(u32 data, void __iomem *addr)
195 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
199 u32 msm_readl(const void __iomem *addr)
201 u32 val = readl(addr);
203 pr_err("IO:R %p %08x\n", addr, val);
207 struct vblank_event {
208 struct list_head node;
213 static void vblank_ctrl_worker(struct kthread_work *work)
215 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
216 struct msm_vblank_ctrl, work);
217 struct msm_drm_private *priv = container_of(vbl_ctrl,
218 struct msm_drm_private, vblank_ctrl);
219 struct msm_kms *kms = priv->kms;
220 struct vblank_event *vbl_ev, *tmp;
223 spin_lock_irqsave(&vbl_ctrl->lock, flags);
224 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
225 list_del(&vbl_ev->node);
226 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
229 kms->funcs->enable_vblank(kms,
230 priv->crtcs[vbl_ev->crtc_id]);
232 kms->funcs->disable_vblank(kms,
233 priv->crtcs[vbl_ev->crtc_id]);
237 spin_lock_irqsave(&vbl_ctrl->lock, flags);
240 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
243 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
244 int crtc_id, bool enable)
246 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
247 struct vblank_event *vbl_ev;
250 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
254 vbl_ev->crtc_id = crtc_id;
255 vbl_ev->enable = enable;
257 spin_lock_irqsave(&vbl_ctrl->lock, flags);
258 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
259 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
261 kthread_queue_work(&priv->disp_thread[crtc_id].worker,
267 static int msm_drm_uninit(struct device *dev)
269 struct platform_device *pdev = to_platform_device(dev);
270 struct drm_device *ddev = platform_get_drvdata(pdev);
271 struct msm_drm_private *priv = ddev->dev_private;
272 struct msm_kms *kms = priv->kms;
273 struct msm_mdss *mdss = priv->mdss;
274 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
275 struct vblank_event *vbl_ev, *tmp;
278 /* We must cancel and cleanup any pending vblank enable/disable
279 * work before drm_irq_uninstall() to avoid work re-enabling an
280 * irq after uninstall has disabled it.
282 kthread_flush_work(&vbl_ctrl->work);
283 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
284 list_del(&vbl_ev->node);
288 /* clean up display commit/event worker threads */
289 for (i = 0; i < priv->num_crtcs; i++) {
290 if (priv->disp_thread[i].thread) {
291 kthread_flush_worker(&priv->disp_thread[i].worker);
292 kthread_stop(priv->disp_thread[i].thread);
293 priv->disp_thread[i].thread = NULL;
296 if (priv->event_thread[i].thread) {
297 kthread_flush_worker(&priv->event_thread[i].worker);
298 kthread_stop(priv->event_thread[i].thread);
299 priv->event_thread[i].thread = NULL;
303 msm_gem_shrinker_cleanup(ddev);
305 drm_kms_helper_poll_fini(ddev);
307 drm_dev_unregister(ddev);
309 msm_perf_debugfs_cleanup(priv);
310 msm_rd_debugfs_cleanup(priv);
312 #ifdef CONFIG_DRM_FBDEV_EMULATION
313 if (fbdev && priv->fbdev)
314 msm_fbdev_free(ddev);
316 drm_atomic_helper_shutdown(ddev);
317 drm_mode_config_cleanup(ddev);
319 pm_runtime_get_sync(dev);
320 drm_irq_uninstall(ddev);
321 pm_runtime_put_sync(dev);
323 flush_workqueue(priv->wq);
324 destroy_workqueue(priv->wq);
326 if (kms && kms->funcs)
327 kms->funcs->destroy(kms);
329 if (priv->vram.paddr) {
330 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
331 drm_mm_takedown(&priv->vram.mm);
332 dma_free_attrs(dev, priv->vram.size, NULL,
333 priv->vram.paddr, attrs);
336 component_unbind_all(dev, ddev);
338 if (mdss && mdss->funcs)
339 mdss->funcs->destroy(ddev);
341 ddev->dev_private = NULL;
353 static int get_mdp_ver(struct platform_device *pdev)
355 struct device *dev = &pdev->dev;
357 return (int) (unsigned long) of_device_get_match_data(dev);
360 #include <linux/of_address.h>
362 static int msm_init_vram(struct drm_device *dev)
364 struct msm_drm_private *priv = dev->dev_private;
365 struct device_node *node;
366 unsigned long size = 0;
369 /* In the device-tree world, we could have a 'memory-region'
370 * phandle, which gives us a link to our "vram". Allocating
371 * is all nicely abstracted behind the dma api, but we need
372 * to know the entire size to allocate it all in one go. There
374 * 1) device with no IOMMU, in which case we need exclusive
375 * access to a VRAM carveout big enough for all gpu
377 * 2) device with IOMMU, but where the bootloader puts up
378 * a splash screen. In this case, the VRAM carveout
379 * need only be large enough for fbdev fb. But we need
380 * exclusive access to the buffer to avoid the kernel
381 * using those pages for other purposes (which appears
382 * as corruption on screen before we have a chance to
383 * load and do initial modeset)
386 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
389 ret = of_address_to_resource(node, 0, &r);
393 size = r.end - r.start;
394 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
396 /* if we have no IOMMU, then we need to use carveout allocator.
397 * Grab the entire CMA chunk carved out in early startup in
400 } else if (!iommu_present(&platform_bus_type)) {
401 DRM_INFO("using %s VRAM carveout\n", vram);
402 size = memparse(vram, NULL);
406 unsigned long attrs = 0;
409 priv->vram.size = size;
411 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
412 spin_lock_init(&priv->vram.lock);
414 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
415 attrs |= DMA_ATTR_WRITE_COMBINE;
417 /* note that for no-kernel-mapping, the vaddr returned
418 * is bogus, but non-null if allocation succeeded:
420 p = dma_alloc_attrs(dev->dev, size,
421 &priv->vram.paddr, GFP_KERNEL, attrs);
423 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
424 priv->vram.paddr = 0;
428 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
429 (uint32_t)priv->vram.paddr,
430 (uint32_t)(priv->vram.paddr + size));
436 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
438 struct platform_device *pdev = to_platform_device(dev);
439 struct drm_device *ddev;
440 struct msm_drm_private *priv;
442 struct msm_mdss *mdss;
444 struct sched_param param;
446 ddev = drm_dev_alloc(drv, dev);
448 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
449 return PTR_ERR(ddev);
452 platform_set_drvdata(pdev, ddev);
454 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
457 goto err_put_drm_dev;
460 ddev->dev_private = priv;
463 switch (get_mdp_ver(pdev)) {
465 ret = mdp5_mdss_init(ddev);
468 ret = dpu_mdss_init(ddev);
479 priv->wq = alloc_ordered_workqueue("msm", 0);
481 INIT_LIST_HEAD(&priv->inactive_list);
482 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
483 kthread_init_work(&priv->vblank_ctrl.work, vblank_ctrl_worker);
484 spin_lock_init(&priv->vblank_ctrl.lock);
486 drm_mode_config_init(ddev);
488 /* Bind all our sub-components: */
489 ret = component_bind_all(dev, ddev);
491 goto err_destroy_mdss;
493 ret = msm_init_vram(ddev);
497 msm_gem_shrinker_init(ddev);
499 switch (get_mdp_ver(pdev)) {
501 kms = mdp4_kms_init(ddev);
505 kms = mdp5_kms_init(ddev);
508 kms = dpu_kms_init(ddev);
512 kms = ERR_PTR(-ENODEV);
518 * NOTE: once we have GPU support, having no kms should not
519 * be considered fatal.. ideally we would still support gpu
520 * and (for example) use dmabuf/prime to share buffers with
521 * imx drm driver on iMX5
523 DRM_DEV_ERROR(dev, "failed to load kms\n");
528 /* Enable normalization of plane zpos */
529 ddev->mode_config.normalize_zpos = true;
532 ret = kms->funcs->hw_init(kms);
534 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
539 ddev->mode_config.funcs = &mode_config_funcs;
540 ddev->mode_config.helper_private = &mode_config_helper_funcs;
543 * this priority was found during empiric testing to have appropriate
544 * realtime scheduling to process display updates and interact with
545 * other real time and normal priority task
547 param.sched_priority = 16;
548 for (i = 0; i < priv->num_crtcs; i++) {
550 /* initialize display thread */
551 priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id;
552 kthread_init_worker(&priv->disp_thread[i].worker);
553 priv->disp_thread[i].dev = ddev;
554 priv->disp_thread[i].thread =
555 kthread_run(kthread_worker_fn,
556 &priv->disp_thread[i].worker,
557 "crtc_commit:%d", priv->disp_thread[i].crtc_id);
558 ret = sched_setscheduler(priv->disp_thread[i].thread,
561 pr_warn("display thread priority update failed: %d\n",
564 if (IS_ERR(priv->disp_thread[i].thread)) {
565 DRM_DEV_ERROR(dev, "failed to create crtc_commit kthread\n");
566 priv->disp_thread[i].thread = NULL;
569 /* initialize event thread */
570 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
571 kthread_init_worker(&priv->event_thread[i].worker);
572 priv->event_thread[i].dev = ddev;
573 priv->event_thread[i].thread =
574 kthread_run(kthread_worker_fn,
575 &priv->event_thread[i].worker,
576 "crtc_event:%d", priv->event_thread[i].crtc_id);
579 * event thread should also run at same priority as disp_thread
580 * because it is handling frame_done events. A lower priority
581 * event thread and higher priority disp_thread can causes
582 * frame_pending counters beyond 2. This can lead to commit
583 * failure at crtc commit level.
585 ret = sched_setscheduler(priv->event_thread[i].thread,
588 pr_warn("display event thread priority update failed: %d\n",
591 if (IS_ERR(priv->event_thread[i].thread)) {
592 dev_err(dev, "failed to create crtc_event kthread\n");
593 priv->event_thread[i].thread = NULL;
596 if ((!priv->disp_thread[i].thread) ||
597 !priv->event_thread[i].thread) {
598 /* clean up previously created threads if any */
599 for ( ; i >= 0; i--) {
600 if (priv->disp_thread[i].thread) {
602 priv->disp_thread[i].thread);
603 priv->disp_thread[i].thread = NULL;
606 if (priv->event_thread[i].thread) {
608 priv->event_thread[i].thread);
609 priv->event_thread[i].thread = NULL;
616 ret = drm_vblank_init(ddev, priv->num_crtcs);
618 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
623 pm_runtime_get_sync(dev);
624 ret = drm_irq_install(ddev, kms->irq);
625 pm_runtime_put_sync(dev);
627 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
632 ret = drm_dev_register(ddev, 0);
636 drm_mode_config_reset(ddev);
638 #ifdef CONFIG_DRM_FBDEV_EMULATION
640 priv->fbdev = msm_fbdev_init(ddev);
643 ret = msm_debugfs_late_init(ddev);
647 drm_kms_helper_poll_init(ddev);
655 if (mdss && mdss->funcs)
656 mdss->funcs->destroy(ddev);
668 static void load_gpu(struct drm_device *dev)
670 static DEFINE_MUTEX(init_lock);
671 struct msm_drm_private *priv = dev->dev_private;
673 mutex_lock(&init_lock);
676 priv->gpu = adreno_load_gpu(dev);
678 mutex_unlock(&init_lock);
681 static int context_init(struct drm_device *dev, struct drm_file *file)
683 struct msm_file_private *ctx;
685 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
689 msm_submitqueue_init(dev, ctx);
691 file->driver_priv = ctx;
696 static int msm_open(struct drm_device *dev, struct drm_file *file)
698 /* For now, load gpu on open.. to avoid the requirement of having
699 * firmware in the initrd.
703 return context_init(dev, file);
706 static void context_close(struct msm_file_private *ctx)
708 msm_submitqueue_close(ctx);
712 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
714 struct msm_drm_private *priv = dev->dev_private;
715 struct msm_file_private *ctx = file->driver_priv;
717 mutex_lock(&dev->struct_mutex);
718 if (ctx == priv->lastctx)
719 priv->lastctx = NULL;
720 mutex_unlock(&dev->struct_mutex);
725 static irqreturn_t msm_irq(int irq, void *arg)
727 struct drm_device *dev = arg;
728 struct msm_drm_private *priv = dev->dev_private;
729 struct msm_kms *kms = priv->kms;
731 return kms->funcs->irq(kms);
734 static void msm_irq_preinstall(struct drm_device *dev)
736 struct msm_drm_private *priv = dev->dev_private;
737 struct msm_kms *kms = priv->kms;
739 kms->funcs->irq_preinstall(kms);
742 static int msm_irq_postinstall(struct drm_device *dev)
744 struct msm_drm_private *priv = dev->dev_private;
745 struct msm_kms *kms = priv->kms;
747 return kms->funcs->irq_postinstall(kms);
750 static void msm_irq_uninstall(struct drm_device *dev)
752 struct msm_drm_private *priv = dev->dev_private;
753 struct msm_kms *kms = priv->kms;
755 kms->funcs->irq_uninstall(kms);
758 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
760 struct msm_drm_private *priv = dev->dev_private;
761 struct msm_kms *kms = priv->kms;
764 DBG("dev=%p, crtc=%u", dev, pipe);
765 return vblank_ctrl_queue_work(priv, pipe, true);
768 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
770 struct msm_drm_private *priv = dev->dev_private;
771 struct msm_kms *kms = priv->kms;
774 DBG("dev=%p, crtc=%u", dev, pipe);
775 vblank_ctrl_queue_work(priv, pipe, false);
782 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
783 struct drm_file *file)
785 struct msm_drm_private *priv = dev->dev_private;
786 struct drm_msm_param *args = data;
789 /* for now, we just have 3d pipe.. eventually this would need to
790 * be more clever to dispatch to appropriate gpu module:
792 if (args->pipe != MSM_PIPE_3D0)
800 return gpu->funcs->get_param(gpu, args->param, &args->value);
803 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
804 struct drm_file *file)
806 struct drm_msm_gem_new *args = data;
808 if (args->flags & ~MSM_BO_FLAGS) {
809 DRM_ERROR("invalid flags: %08x\n", args->flags);
813 return msm_gem_new_handle(dev, file, args->size,
814 args->flags, &args->handle, NULL);
817 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
819 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
822 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
823 struct drm_file *file)
825 struct drm_msm_gem_cpu_prep *args = data;
826 struct drm_gem_object *obj;
827 ktime_t timeout = to_ktime(args->timeout);
830 if (args->op & ~MSM_PREP_FLAGS) {
831 DRM_ERROR("invalid op: %08x\n", args->op);
835 obj = drm_gem_object_lookup(file, args->handle);
839 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
841 drm_gem_object_put_unlocked(obj);
846 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
847 struct drm_file *file)
849 struct drm_msm_gem_cpu_fini *args = data;
850 struct drm_gem_object *obj;
853 obj = drm_gem_object_lookup(file, args->handle);
857 ret = msm_gem_cpu_fini(obj);
859 drm_gem_object_put_unlocked(obj);
864 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
865 struct drm_gem_object *obj, uint64_t *iova)
867 struct msm_drm_private *priv = dev->dev_private;
873 * Don't pin the memory here - just get an address so that userspace can
876 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
879 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
880 struct drm_file *file)
882 struct drm_msm_gem_info *args = data;
883 struct drm_gem_object *obj;
884 struct msm_gem_object *msm_obj;
890 switch (args->info) {
891 case MSM_INFO_GET_OFFSET:
892 case MSM_INFO_GET_IOVA:
893 /* value returned as immediate, not pointer, so len==0: */
897 case MSM_INFO_SET_NAME:
898 case MSM_INFO_GET_NAME:
904 obj = drm_gem_object_lookup(file, args->handle);
908 msm_obj = to_msm_bo(obj);
910 switch (args->info) {
911 case MSM_INFO_GET_OFFSET:
912 args->value = msm_gem_mmap_offset(obj);
914 case MSM_INFO_GET_IOVA:
915 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
917 case MSM_INFO_SET_NAME:
918 /* length check should leave room for terminating null: */
919 if (args->len >= sizeof(msm_obj->name)) {
923 ret = copy_from_user(msm_obj->name,
924 u64_to_user_ptr(args->value), args->len);
925 msm_obj->name[args->len] = '\0';
926 for (i = 0; i < args->len; i++) {
927 if (!isprint(msm_obj->name[i])) {
928 msm_obj->name[i] = '\0';
933 case MSM_INFO_GET_NAME:
934 if (args->value && (args->len < strlen(msm_obj->name))) {
938 args->len = strlen(msm_obj->name);
940 ret = copy_to_user(u64_to_user_ptr(args->value),
941 msm_obj->name, args->len);
946 drm_gem_object_put_unlocked(obj);
951 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
952 struct drm_file *file)
954 struct msm_drm_private *priv = dev->dev_private;
955 struct drm_msm_wait_fence *args = data;
956 ktime_t timeout = to_ktime(args->timeout);
957 struct msm_gpu_submitqueue *queue;
958 struct msm_gpu *gpu = priv->gpu;
962 DRM_ERROR("invalid pad: %08x\n", args->pad);
969 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
973 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
976 msm_submitqueue_put(queue);
980 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
981 struct drm_file *file)
983 struct drm_msm_gem_madvise *args = data;
984 struct drm_gem_object *obj;
987 switch (args->madv) {
988 case MSM_MADV_DONTNEED:
989 case MSM_MADV_WILLNEED:
995 ret = mutex_lock_interruptible(&dev->struct_mutex);
999 obj = drm_gem_object_lookup(file, args->handle);
1005 ret = msm_gem_madvise(obj, args->madv);
1007 args->retained = ret;
1011 drm_gem_object_put(obj);
1014 mutex_unlock(&dev->struct_mutex);
1019 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
1020 struct drm_file *file)
1022 struct drm_msm_submitqueue *args = data;
1024 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
1027 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
1028 args->flags, &args->id);
1032 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1033 struct drm_file *file)
1035 u32 id = *(u32 *) data;
1037 return msm_submitqueue_remove(file->driver_priv, id);
1040 static const struct drm_ioctl_desc msm_ioctls[] = {
1041 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
1042 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
1043 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
1044 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
1045 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
1046 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
1047 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
1048 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
1049 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
1050 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
1053 static const struct vm_operations_struct vm_ops = {
1054 .fault = msm_gem_fault,
1055 .open = drm_gem_vm_open,
1056 .close = drm_gem_vm_close,
1059 static const struct file_operations fops = {
1060 .owner = THIS_MODULE,
1062 .release = drm_release,
1063 .unlocked_ioctl = drm_ioctl,
1064 .compat_ioctl = drm_compat_ioctl,
1067 .llseek = no_llseek,
1068 .mmap = msm_gem_mmap,
1071 static struct drm_driver msm_driver = {
1072 .driver_features = DRIVER_HAVE_IRQ |
1079 .postclose = msm_postclose,
1080 .lastclose = drm_fb_helper_lastclose,
1081 .irq_handler = msm_irq,
1082 .irq_preinstall = msm_irq_preinstall,
1083 .irq_postinstall = msm_irq_postinstall,
1084 .irq_uninstall = msm_irq_uninstall,
1085 .enable_vblank = msm_enable_vblank,
1086 .disable_vblank = msm_disable_vblank,
1087 .gem_free_object = msm_gem_free_object,
1088 .gem_vm_ops = &vm_ops,
1089 .dumb_create = msm_gem_dumb_create,
1090 .dumb_map_offset = msm_gem_dumb_map_offset,
1091 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1092 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1093 .gem_prime_export = drm_gem_prime_export,
1094 .gem_prime_import = drm_gem_prime_import,
1095 .gem_prime_res_obj = msm_gem_prime_res_obj,
1096 .gem_prime_pin = msm_gem_prime_pin,
1097 .gem_prime_unpin = msm_gem_prime_unpin,
1098 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1099 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1100 .gem_prime_vmap = msm_gem_prime_vmap,
1101 .gem_prime_vunmap = msm_gem_prime_vunmap,
1102 .gem_prime_mmap = msm_gem_prime_mmap,
1103 #ifdef CONFIG_DEBUG_FS
1104 .debugfs_init = msm_debugfs_init,
1106 .ioctls = msm_ioctls,
1107 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1110 .desc = "MSM Snapdragon DRM",
1112 .major = MSM_VERSION_MAJOR,
1113 .minor = MSM_VERSION_MINOR,
1114 .patchlevel = MSM_VERSION_PATCHLEVEL,
1117 #ifdef CONFIG_PM_SLEEP
1118 static int msm_pm_suspend(struct device *dev)
1120 struct drm_device *ddev = dev_get_drvdata(dev);
1121 struct msm_drm_private *priv = ddev->dev_private;
1123 if (WARN_ON(priv->pm_state))
1124 drm_atomic_state_put(priv->pm_state);
1126 priv->pm_state = drm_atomic_helper_suspend(ddev);
1127 if (IS_ERR(priv->pm_state)) {
1128 int ret = PTR_ERR(priv->pm_state);
1129 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1136 static int msm_pm_resume(struct device *dev)
1138 struct drm_device *ddev = dev_get_drvdata(dev);
1139 struct msm_drm_private *priv = ddev->dev_private;
1142 if (WARN_ON(!priv->pm_state))
1145 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1147 priv->pm_state = NULL;
1154 static int msm_runtime_suspend(struct device *dev)
1156 struct drm_device *ddev = dev_get_drvdata(dev);
1157 struct msm_drm_private *priv = ddev->dev_private;
1158 struct msm_mdss *mdss = priv->mdss;
1162 if (mdss && mdss->funcs)
1163 return mdss->funcs->disable(mdss);
1168 static int msm_runtime_resume(struct device *dev)
1170 struct drm_device *ddev = dev_get_drvdata(dev);
1171 struct msm_drm_private *priv = ddev->dev_private;
1172 struct msm_mdss *mdss = priv->mdss;
1176 if (mdss && mdss->funcs)
1177 return mdss->funcs->enable(mdss);
1183 static const struct dev_pm_ops msm_pm_ops = {
1184 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1185 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1189 * Componentized driver support:
1193 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1194 * so probably some room for some helpers
1196 static int compare_of(struct device *dev, void *data)
1198 return dev->of_node == data;
1202 * Identify what components need to be added by parsing what remote-endpoints
1203 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1204 * is no external component that we need to add since LVDS is within MDP4
1207 static int add_components_mdp(struct device *mdp_dev,
1208 struct component_match **matchptr)
1210 struct device_node *np = mdp_dev->of_node;
1211 struct device_node *ep_node;
1212 struct device *master_dev;
1215 * on MDP4 based platforms, the MDP platform device is the component
1216 * master that adds other display interface components to itself.
1218 * on MDP5 based platforms, the MDSS platform device is the component
1219 * master that adds MDP5 and other display interface components to
1222 if (of_device_is_compatible(np, "qcom,mdp4"))
1223 master_dev = mdp_dev;
1225 master_dev = mdp_dev->parent;
1227 for_each_endpoint_of_node(np, ep_node) {
1228 struct device_node *intf;
1229 struct of_endpoint ep;
1232 ret = of_graph_parse_endpoint(ep_node, &ep);
1234 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1235 of_node_put(ep_node);
1240 * The LCDC/LVDS port on MDP4 is a speacial case where the
1241 * remote-endpoint isn't a component that we need to add
1243 if (of_device_is_compatible(np, "qcom,mdp4") &&
1248 * It's okay if some of the ports don't have a remote endpoint
1249 * specified. It just means that the port isn't connected to
1250 * any external interface.
1252 intf = of_graph_get_remote_port_parent(ep_node);
1256 drm_of_component_match_add(master_dev, matchptr, compare_of,
1264 static int compare_name_mdp(struct device *dev, void *data)
1266 return (strstr(dev_name(dev), "mdp") != NULL);
1269 static int add_display_components(struct device *dev,
1270 struct component_match **matchptr)
1272 struct device *mdp_dev;
1276 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1277 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1278 * Populate the children devices, find the MDP5/DPU node, and then add
1279 * the interfaces to our components list.
1281 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1282 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1283 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1285 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1289 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1291 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1292 of_platform_depopulate(dev);
1296 put_device(mdp_dev);
1298 /* add the MDP component itself */
1299 drm_of_component_match_add(dev, matchptr, compare_of,
1306 ret = add_components_mdp(mdp_dev, matchptr);
1308 of_platform_depopulate(dev);
1314 * We don't know what's the best binding to link the gpu with the drm device.
1315 * Fow now, we just hunt for all the possible gpus that we support, and add them
1318 static const struct of_device_id msm_gpu_match[] = {
1319 { .compatible = "qcom,adreno" },
1320 { .compatible = "qcom,adreno-3xx" },
1321 { .compatible = "qcom,kgsl-3d0" },
1325 static int add_gpu_components(struct device *dev,
1326 struct component_match **matchptr)
1328 struct device_node *np;
1330 np = of_find_matching_node(NULL, msm_gpu_match);
1334 drm_of_component_match_add(dev, matchptr, compare_of, np);
1341 static int msm_drm_bind(struct device *dev)
1343 return msm_drm_init(dev, &msm_driver);
1346 static void msm_drm_unbind(struct device *dev)
1348 msm_drm_uninit(dev);
1351 static const struct component_master_ops msm_drm_ops = {
1352 .bind = msm_drm_bind,
1353 .unbind = msm_drm_unbind,
1360 static int msm_pdev_probe(struct platform_device *pdev)
1362 struct component_match *match = NULL;
1365 ret = add_display_components(&pdev->dev, &match);
1369 ret = add_gpu_components(&pdev->dev, &match);
1373 /* on all devices that I am aware of, iommu's which can map
1374 * any address the cpu can see are used:
1376 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1380 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1383 static int msm_pdev_remove(struct platform_device *pdev)
1385 component_master_del(&pdev->dev, &msm_drm_ops);
1386 of_platform_depopulate(&pdev->dev);
1391 static const struct of_device_id dt_match[] = {
1392 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1393 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1394 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1397 MODULE_DEVICE_TABLE(of, dt_match);
1399 static struct platform_driver msm_platform_driver = {
1400 .probe = msm_pdev_probe,
1401 .remove = msm_pdev_remove,
1404 .of_match_table = dt_match,
1409 static int __init msm_drm_register(void)
1419 msm_hdmi_register();
1421 return platform_driver_register(&msm_platform_driver);
1424 static void __exit msm_drm_unregister(void)
1427 platform_driver_unregister(&msm_platform_driver);
1428 msm_hdmi_unregister();
1429 adreno_unregister();
1430 msm_edp_unregister();
1431 msm_dsi_unregister();
1432 msm_mdp_unregister();
1433 msm_dpu_unregister();
1436 module_init(msm_drm_register);
1437 module_exit(msm_drm_unregister);
1439 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1440 MODULE_DESCRIPTION("MSM DRM Driver");
1441 MODULE_LICENSE("GPL");