2 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kthread.h>
20 #include <uapi/linux/sched/types.h>
21 #include <drm/drm_of.h>
24 #include "msm_debugfs.h"
25 #include "msm_fence.h"
32 * - 1.0.0 - initial interface
33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
34 * - 1.2.0 - adds explicit fence support for submit ioctl
35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
39 #define MSM_VERSION_MAJOR 1
40 #define MSM_VERSION_MINOR 3
41 #define MSM_VERSION_PATCHLEVEL 0
43 static const struct drm_mode_config_funcs mode_config_funcs = {
44 .fb_create = msm_framebuffer_create,
45 .output_poll_changed = drm_fb_helper_output_poll_changed,
46 .atomic_check = drm_atomic_helper_check,
47 .atomic_commit = drm_atomic_helper_commit,
50 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
51 .atomic_commit_tail = msm_atomic_commit_tail,
54 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
55 static bool reglog = false;
56 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
57 module_param(reglog, bool, 0600);
62 #ifdef CONFIG_DRM_FBDEV_EMULATION
63 static bool fbdev = true;
64 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
65 module_param(fbdev, bool, 0600);
68 static char *vram = "16m";
69 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
70 module_param(vram, charp, 0);
72 bool dumpstate = false;
73 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
74 module_param(dumpstate, bool, 0600);
76 static bool modeset = true;
77 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
78 module_param(modeset, bool, 0600);
84 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
86 struct property *prop;
88 struct clk_bulk_data *local;
89 int i = 0, ret, count;
91 count = of_property_count_strings(dev->of_node, "clock-names");
95 local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
100 of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
101 local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
103 devm_kfree(dev, local);
110 ret = devm_clk_bulk_get(dev, count, local);
113 for (i = 0; i < count; i++)
114 devm_kfree(dev, (void *) local[i].id);
115 devm_kfree(dev, local);
124 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
130 snprintf(n, sizeof(n), "%s_clk", name);
132 for (i = 0; bulk && i < count; i++) {
133 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
141 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
146 clk = devm_clk_get(&pdev->dev, name);
147 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
150 snprintf(name2, sizeof(name2), "%s_clk", name);
152 clk = devm_clk_get(&pdev->dev, name2);
154 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
155 "\"%s\" instead of \"%s\"\n", name, name2);
160 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
163 struct resource *res;
168 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
173 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
174 return ERR_PTR(-EINVAL);
177 size = resource_size(res);
179 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
181 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
182 return ERR_PTR(-ENOMEM);
186 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
191 void msm_writel(u32 data, void __iomem *addr)
194 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
198 u32 msm_readl(const void __iomem *addr)
200 u32 val = readl(addr);
202 pr_err("IO:R %p %08x\n", addr, val);
206 struct vblank_event {
207 struct list_head node;
212 static void vblank_ctrl_worker(struct kthread_work *work)
214 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
215 struct msm_vblank_ctrl, work);
216 struct msm_drm_private *priv = container_of(vbl_ctrl,
217 struct msm_drm_private, vblank_ctrl);
218 struct msm_kms *kms = priv->kms;
219 struct vblank_event *vbl_ev, *tmp;
222 spin_lock_irqsave(&vbl_ctrl->lock, flags);
223 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
224 list_del(&vbl_ev->node);
225 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
228 kms->funcs->enable_vblank(kms,
229 priv->crtcs[vbl_ev->crtc_id]);
231 kms->funcs->disable_vblank(kms,
232 priv->crtcs[vbl_ev->crtc_id]);
236 spin_lock_irqsave(&vbl_ctrl->lock, flags);
239 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
242 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
243 int crtc_id, bool enable)
245 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
246 struct vblank_event *vbl_ev;
249 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
253 vbl_ev->crtc_id = crtc_id;
254 vbl_ev->enable = enable;
256 spin_lock_irqsave(&vbl_ctrl->lock, flags);
257 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
258 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
260 kthread_queue_work(&priv->disp_thread[crtc_id].worker,
266 static int msm_drm_uninit(struct device *dev)
268 struct platform_device *pdev = to_platform_device(dev);
269 struct drm_device *ddev = platform_get_drvdata(pdev);
270 struct msm_drm_private *priv = ddev->dev_private;
271 struct msm_kms *kms = priv->kms;
272 struct msm_mdss *mdss = priv->mdss;
273 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
274 struct vblank_event *vbl_ev, *tmp;
277 /* We must cancel and cleanup any pending vblank enable/disable
278 * work before drm_irq_uninstall() to avoid work re-enabling an
279 * irq after uninstall has disabled it.
281 kthread_flush_work(&vbl_ctrl->work);
282 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
283 list_del(&vbl_ev->node);
287 /* clean up display commit/event worker threads */
288 for (i = 0; i < priv->num_crtcs; i++) {
289 if (priv->disp_thread[i].thread) {
290 kthread_flush_worker(&priv->disp_thread[i].worker);
291 kthread_stop(priv->disp_thread[i].thread);
292 priv->disp_thread[i].thread = NULL;
295 if (priv->event_thread[i].thread) {
296 kthread_flush_worker(&priv->event_thread[i].worker);
297 kthread_stop(priv->event_thread[i].thread);
298 priv->event_thread[i].thread = NULL;
302 msm_gem_shrinker_cleanup(ddev);
304 drm_kms_helper_poll_fini(ddev);
306 drm_dev_unregister(ddev);
308 msm_perf_debugfs_cleanup(priv);
309 msm_rd_debugfs_cleanup(priv);
311 #ifdef CONFIG_DRM_FBDEV_EMULATION
312 if (fbdev && priv->fbdev)
313 msm_fbdev_free(ddev);
315 drm_atomic_helper_shutdown(ddev);
316 drm_mode_config_cleanup(ddev);
318 pm_runtime_get_sync(dev);
319 drm_irq_uninstall(ddev);
320 pm_runtime_put_sync(dev);
322 flush_workqueue(priv->wq);
323 destroy_workqueue(priv->wq);
325 if (kms && kms->funcs)
326 kms->funcs->destroy(kms);
328 if (priv->vram.paddr) {
329 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
330 drm_mm_takedown(&priv->vram.mm);
331 dma_free_attrs(dev, priv->vram.size, NULL,
332 priv->vram.paddr, attrs);
335 component_unbind_all(dev, ddev);
337 if (mdss && mdss->funcs)
338 mdss->funcs->destroy(ddev);
340 ddev->dev_private = NULL;
352 static int get_mdp_ver(struct platform_device *pdev)
354 struct device *dev = &pdev->dev;
356 return (int) (unsigned long) of_device_get_match_data(dev);
359 #include <linux/of_address.h>
361 static int msm_init_vram(struct drm_device *dev)
363 struct msm_drm_private *priv = dev->dev_private;
364 struct device_node *node;
365 unsigned long size = 0;
368 /* In the device-tree world, we could have a 'memory-region'
369 * phandle, which gives us a link to our "vram". Allocating
370 * is all nicely abstracted behind the dma api, but we need
371 * to know the entire size to allocate it all in one go. There
373 * 1) device with no IOMMU, in which case we need exclusive
374 * access to a VRAM carveout big enough for all gpu
376 * 2) device with IOMMU, but where the bootloader puts up
377 * a splash screen. In this case, the VRAM carveout
378 * need only be large enough for fbdev fb. But we need
379 * exclusive access to the buffer to avoid the kernel
380 * using those pages for other purposes (which appears
381 * as corruption on screen before we have a chance to
382 * load and do initial modeset)
385 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
388 ret = of_address_to_resource(node, 0, &r);
392 size = r.end - r.start;
393 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
395 /* if we have no IOMMU, then we need to use carveout allocator.
396 * Grab the entire CMA chunk carved out in early startup in
399 } else if (!iommu_present(&platform_bus_type)) {
400 DRM_INFO("using %s VRAM carveout\n", vram);
401 size = memparse(vram, NULL);
405 unsigned long attrs = 0;
408 priv->vram.size = size;
410 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
411 spin_lock_init(&priv->vram.lock);
413 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
414 attrs |= DMA_ATTR_WRITE_COMBINE;
416 /* note that for no-kernel-mapping, the vaddr returned
417 * is bogus, but non-null if allocation succeeded:
419 p = dma_alloc_attrs(dev->dev, size,
420 &priv->vram.paddr, GFP_KERNEL, attrs);
422 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
423 priv->vram.paddr = 0;
427 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
428 (uint32_t)priv->vram.paddr,
429 (uint32_t)(priv->vram.paddr + size));
435 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
437 struct platform_device *pdev = to_platform_device(dev);
438 struct drm_device *ddev;
439 struct msm_drm_private *priv;
441 struct msm_mdss *mdss;
443 struct sched_param param;
445 ddev = drm_dev_alloc(drv, dev);
447 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
448 return PTR_ERR(ddev);
451 platform_set_drvdata(pdev, ddev);
453 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
456 goto err_put_drm_dev;
459 ddev->dev_private = priv;
462 switch (get_mdp_ver(pdev)) {
464 ret = mdp5_mdss_init(ddev);
467 ret = dpu_mdss_init(ddev);
478 priv->wq = alloc_ordered_workqueue("msm", 0);
480 INIT_LIST_HEAD(&priv->inactive_list);
481 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
482 kthread_init_work(&priv->vblank_ctrl.work, vblank_ctrl_worker);
483 spin_lock_init(&priv->vblank_ctrl.lock);
485 drm_mode_config_init(ddev);
487 /* Bind all our sub-components: */
488 ret = component_bind_all(dev, ddev);
490 goto err_destroy_mdss;
492 ret = msm_init_vram(ddev);
496 msm_gem_shrinker_init(ddev);
498 switch (get_mdp_ver(pdev)) {
500 kms = mdp4_kms_init(ddev);
504 kms = mdp5_kms_init(ddev);
507 kms = dpu_kms_init(ddev);
511 kms = ERR_PTR(-ENODEV);
517 * NOTE: once we have GPU support, having no kms should not
518 * be considered fatal.. ideally we would still support gpu
519 * and (for example) use dmabuf/prime to share buffers with
520 * imx drm driver on iMX5
522 DRM_DEV_ERROR(dev, "failed to load kms\n");
527 /* Enable normalization of plane zpos */
528 ddev->mode_config.normalize_zpos = true;
531 ret = kms->funcs->hw_init(kms);
533 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
538 ddev->mode_config.funcs = &mode_config_funcs;
539 ddev->mode_config.helper_private = &mode_config_helper_funcs;
542 * this priority was found during empiric testing to have appropriate
543 * realtime scheduling to process display updates and interact with
544 * other real time and normal priority task
546 param.sched_priority = 16;
547 for (i = 0; i < priv->num_crtcs; i++) {
549 /* initialize display thread */
550 priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id;
551 kthread_init_worker(&priv->disp_thread[i].worker);
552 priv->disp_thread[i].dev = ddev;
553 priv->disp_thread[i].thread =
554 kthread_run(kthread_worker_fn,
555 &priv->disp_thread[i].worker,
556 "crtc_commit:%d", priv->disp_thread[i].crtc_id);
557 ret = sched_setscheduler(priv->disp_thread[i].thread,
560 pr_warn("display thread priority update failed: %d\n",
563 if (IS_ERR(priv->disp_thread[i].thread)) {
564 DRM_DEV_ERROR(dev, "failed to create crtc_commit kthread\n");
565 priv->disp_thread[i].thread = NULL;
568 /* initialize event thread */
569 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
570 kthread_init_worker(&priv->event_thread[i].worker);
571 priv->event_thread[i].dev = ddev;
572 priv->event_thread[i].thread =
573 kthread_run(kthread_worker_fn,
574 &priv->event_thread[i].worker,
575 "crtc_event:%d", priv->event_thread[i].crtc_id);
578 * event thread should also run at same priority as disp_thread
579 * because it is handling frame_done events. A lower priority
580 * event thread and higher priority disp_thread can causes
581 * frame_pending counters beyond 2. This can lead to commit
582 * failure at crtc commit level.
584 ret = sched_setscheduler(priv->event_thread[i].thread,
587 pr_warn("display event thread priority update failed: %d\n",
590 if (IS_ERR(priv->event_thread[i].thread)) {
591 dev_err(dev, "failed to create crtc_event kthread\n");
592 priv->event_thread[i].thread = NULL;
595 if ((!priv->disp_thread[i].thread) ||
596 !priv->event_thread[i].thread) {
597 /* clean up previously created threads if any */
598 for ( ; i >= 0; i--) {
599 if (priv->disp_thread[i].thread) {
601 priv->disp_thread[i].thread);
602 priv->disp_thread[i].thread = NULL;
605 if (priv->event_thread[i].thread) {
607 priv->event_thread[i].thread);
608 priv->event_thread[i].thread = NULL;
615 ret = drm_vblank_init(ddev, priv->num_crtcs);
617 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
622 pm_runtime_get_sync(dev);
623 ret = drm_irq_install(ddev, kms->irq);
624 pm_runtime_put_sync(dev);
626 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
631 ret = drm_dev_register(ddev, 0);
635 drm_mode_config_reset(ddev);
637 #ifdef CONFIG_DRM_FBDEV_EMULATION
639 priv->fbdev = msm_fbdev_init(ddev);
642 ret = msm_debugfs_late_init(ddev);
646 drm_kms_helper_poll_init(ddev);
654 if (mdss && mdss->funcs)
655 mdss->funcs->destroy(ddev);
667 static void load_gpu(struct drm_device *dev)
669 static DEFINE_MUTEX(init_lock);
670 struct msm_drm_private *priv = dev->dev_private;
672 mutex_lock(&init_lock);
675 priv->gpu = adreno_load_gpu(dev);
677 mutex_unlock(&init_lock);
680 static int context_init(struct drm_device *dev, struct drm_file *file)
682 struct msm_file_private *ctx;
684 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
688 msm_submitqueue_init(dev, ctx);
690 file->driver_priv = ctx;
695 static int msm_open(struct drm_device *dev, struct drm_file *file)
697 /* For now, load gpu on open.. to avoid the requirement of having
698 * firmware in the initrd.
702 return context_init(dev, file);
705 static void context_close(struct msm_file_private *ctx)
707 msm_submitqueue_close(ctx);
711 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
713 struct msm_drm_private *priv = dev->dev_private;
714 struct msm_file_private *ctx = file->driver_priv;
716 mutex_lock(&dev->struct_mutex);
717 if (ctx == priv->lastctx)
718 priv->lastctx = NULL;
719 mutex_unlock(&dev->struct_mutex);
724 static irqreturn_t msm_irq(int irq, void *arg)
726 struct drm_device *dev = arg;
727 struct msm_drm_private *priv = dev->dev_private;
728 struct msm_kms *kms = priv->kms;
730 return kms->funcs->irq(kms);
733 static void msm_irq_preinstall(struct drm_device *dev)
735 struct msm_drm_private *priv = dev->dev_private;
736 struct msm_kms *kms = priv->kms;
738 kms->funcs->irq_preinstall(kms);
741 static int msm_irq_postinstall(struct drm_device *dev)
743 struct msm_drm_private *priv = dev->dev_private;
744 struct msm_kms *kms = priv->kms;
746 return kms->funcs->irq_postinstall(kms);
749 static void msm_irq_uninstall(struct drm_device *dev)
751 struct msm_drm_private *priv = dev->dev_private;
752 struct msm_kms *kms = priv->kms;
754 kms->funcs->irq_uninstall(kms);
757 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
759 struct msm_drm_private *priv = dev->dev_private;
760 struct msm_kms *kms = priv->kms;
763 DBG("dev=%p, crtc=%u", dev, pipe);
764 return vblank_ctrl_queue_work(priv, pipe, true);
767 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
769 struct msm_drm_private *priv = dev->dev_private;
770 struct msm_kms *kms = priv->kms;
773 DBG("dev=%p, crtc=%u", dev, pipe);
774 vblank_ctrl_queue_work(priv, pipe, false);
781 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
782 struct drm_file *file)
784 struct msm_drm_private *priv = dev->dev_private;
785 struct drm_msm_param *args = data;
788 /* for now, we just have 3d pipe.. eventually this would need to
789 * be more clever to dispatch to appropriate gpu module:
791 if (args->pipe != MSM_PIPE_3D0)
799 return gpu->funcs->get_param(gpu, args->param, &args->value);
802 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
803 struct drm_file *file)
805 struct drm_msm_gem_new *args = data;
807 if (args->flags & ~MSM_BO_FLAGS) {
808 DRM_ERROR("invalid flags: %08x\n", args->flags);
812 return msm_gem_new_handle(dev, file, args->size,
813 args->flags, &args->handle, NULL);
816 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
818 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
821 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
822 struct drm_file *file)
824 struct drm_msm_gem_cpu_prep *args = data;
825 struct drm_gem_object *obj;
826 ktime_t timeout = to_ktime(args->timeout);
829 if (args->op & ~MSM_PREP_FLAGS) {
830 DRM_ERROR("invalid op: %08x\n", args->op);
834 obj = drm_gem_object_lookup(file, args->handle);
838 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
840 drm_gem_object_put_unlocked(obj);
845 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
846 struct drm_file *file)
848 struct drm_msm_gem_cpu_fini *args = data;
849 struct drm_gem_object *obj;
852 obj = drm_gem_object_lookup(file, args->handle);
856 ret = msm_gem_cpu_fini(obj);
858 drm_gem_object_put_unlocked(obj);
863 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
864 struct drm_gem_object *obj, uint64_t *iova)
866 struct msm_drm_private *priv = dev->dev_private;
872 * Don't pin the memory here - just get an address so that userspace can
875 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
878 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
879 struct drm_file *file)
881 struct drm_msm_gem_info *args = data;
882 struct drm_gem_object *obj;
888 switch (args->info) {
889 case MSM_INFO_GET_OFFSET:
890 case MSM_INFO_GET_IOVA:
891 /* value returned as immediate, not pointer, so len==0: */
899 obj = drm_gem_object_lookup(file, args->handle);
903 switch (args->info) {
904 case MSM_INFO_GET_OFFSET:
905 args->value = msm_gem_mmap_offset(obj);
907 case MSM_INFO_GET_IOVA:
908 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
912 drm_gem_object_put_unlocked(obj);
917 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
918 struct drm_file *file)
920 struct msm_drm_private *priv = dev->dev_private;
921 struct drm_msm_wait_fence *args = data;
922 ktime_t timeout = to_ktime(args->timeout);
923 struct msm_gpu_submitqueue *queue;
924 struct msm_gpu *gpu = priv->gpu;
928 DRM_ERROR("invalid pad: %08x\n", args->pad);
935 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
939 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
942 msm_submitqueue_put(queue);
946 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
947 struct drm_file *file)
949 struct drm_msm_gem_madvise *args = data;
950 struct drm_gem_object *obj;
953 switch (args->madv) {
954 case MSM_MADV_DONTNEED:
955 case MSM_MADV_WILLNEED:
961 ret = mutex_lock_interruptible(&dev->struct_mutex);
965 obj = drm_gem_object_lookup(file, args->handle);
971 ret = msm_gem_madvise(obj, args->madv);
973 args->retained = ret;
977 drm_gem_object_put(obj);
980 mutex_unlock(&dev->struct_mutex);
985 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
986 struct drm_file *file)
988 struct drm_msm_submitqueue *args = data;
990 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
993 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
994 args->flags, &args->id);
998 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
999 struct drm_file *file)
1001 u32 id = *(u32 *) data;
1003 return msm_submitqueue_remove(file->driver_priv, id);
1006 static const struct drm_ioctl_desc msm_ioctls[] = {
1007 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
1008 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
1009 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
1010 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
1011 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
1012 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
1013 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
1014 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
1015 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
1016 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
1019 static const struct vm_operations_struct vm_ops = {
1020 .fault = msm_gem_fault,
1021 .open = drm_gem_vm_open,
1022 .close = drm_gem_vm_close,
1025 static const struct file_operations fops = {
1026 .owner = THIS_MODULE,
1028 .release = drm_release,
1029 .unlocked_ioctl = drm_ioctl,
1030 .compat_ioctl = drm_compat_ioctl,
1033 .llseek = no_llseek,
1034 .mmap = msm_gem_mmap,
1037 static struct drm_driver msm_driver = {
1038 .driver_features = DRIVER_HAVE_IRQ |
1045 .postclose = msm_postclose,
1046 .lastclose = drm_fb_helper_lastclose,
1047 .irq_handler = msm_irq,
1048 .irq_preinstall = msm_irq_preinstall,
1049 .irq_postinstall = msm_irq_postinstall,
1050 .irq_uninstall = msm_irq_uninstall,
1051 .enable_vblank = msm_enable_vblank,
1052 .disable_vblank = msm_disable_vblank,
1053 .gem_free_object = msm_gem_free_object,
1054 .gem_vm_ops = &vm_ops,
1055 .dumb_create = msm_gem_dumb_create,
1056 .dumb_map_offset = msm_gem_dumb_map_offset,
1057 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1058 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1059 .gem_prime_export = drm_gem_prime_export,
1060 .gem_prime_import = drm_gem_prime_import,
1061 .gem_prime_res_obj = msm_gem_prime_res_obj,
1062 .gem_prime_pin = msm_gem_prime_pin,
1063 .gem_prime_unpin = msm_gem_prime_unpin,
1064 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1065 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1066 .gem_prime_vmap = msm_gem_prime_vmap,
1067 .gem_prime_vunmap = msm_gem_prime_vunmap,
1068 .gem_prime_mmap = msm_gem_prime_mmap,
1069 #ifdef CONFIG_DEBUG_FS
1070 .debugfs_init = msm_debugfs_init,
1072 .ioctls = msm_ioctls,
1073 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1076 .desc = "MSM Snapdragon DRM",
1078 .major = MSM_VERSION_MAJOR,
1079 .minor = MSM_VERSION_MINOR,
1080 .patchlevel = MSM_VERSION_PATCHLEVEL,
1083 #ifdef CONFIG_PM_SLEEP
1084 static int msm_pm_suspend(struct device *dev)
1086 struct drm_device *ddev = dev_get_drvdata(dev);
1087 struct msm_drm_private *priv = ddev->dev_private;
1089 if (WARN_ON(priv->pm_state))
1090 drm_atomic_state_put(priv->pm_state);
1092 priv->pm_state = drm_atomic_helper_suspend(ddev);
1093 if (IS_ERR(priv->pm_state)) {
1094 int ret = PTR_ERR(priv->pm_state);
1095 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1102 static int msm_pm_resume(struct device *dev)
1104 struct drm_device *ddev = dev_get_drvdata(dev);
1105 struct msm_drm_private *priv = ddev->dev_private;
1108 if (WARN_ON(!priv->pm_state))
1111 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1113 priv->pm_state = NULL;
1120 static int msm_runtime_suspend(struct device *dev)
1122 struct drm_device *ddev = dev_get_drvdata(dev);
1123 struct msm_drm_private *priv = ddev->dev_private;
1124 struct msm_mdss *mdss = priv->mdss;
1128 if (mdss && mdss->funcs)
1129 return mdss->funcs->disable(mdss);
1134 static int msm_runtime_resume(struct device *dev)
1136 struct drm_device *ddev = dev_get_drvdata(dev);
1137 struct msm_drm_private *priv = ddev->dev_private;
1138 struct msm_mdss *mdss = priv->mdss;
1142 if (mdss && mdss->funcs)
1143 return mdss->funcs->enable(mdss);
1149 static const struct dev_pm_ops msm_pm_ops = {
1150 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1151 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1155 * Componentized driver support:
1159 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1160 * so probably some room for some helpers
1162 static int compare_of(struct device *dev, void *data)
1164 return dev->of_node == data;
1168 * Identify what components need to be added by parsing what remote-endpoints
1169 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1170 * is no external component that we need to add since LVDS is within MDP4
1173 static int add_components_mdp(struct device *mdp_dev,
1174 struct component_match **matchptr)
1176 struct device_node *np = mdp_dev->of_node;
1177 struct device_node *ep_node;
1178 struct device *master_dev;
1181 * on MDP4 based platforms, the MDP platform device is the component
1182 * master that adds other display interface components to itself.
1184 * on MDP5 based platforms, the MDSS platform device is the component
1185 * master that adds MDP5 and other display interface components to
1188 if (of_device_is_compatible(np, "qcom,mdp4"))
1189 master_dev = mdp_dev;
1191 master_dev = mdp_dev->parent;
1193 for_each_endpoint_of_node(np, ep_node) {
1194 struct device_node *intf;
1195 struct of_endpoint ep;
1198 ret = of_graph_parse_endpoint(ep_node, &ep);
1200 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1201 of_node_put(ep_node);
1206 * The LCDC/LVDS port on MDP4 is a speacial case where the
1207 * remote-endpoint isn't a component that we need to add
1209 if (of_device_is_compatible(np, "qcom,mdp4") &&
1214 * It's okay if some of the ports don't have a remote endpoint
1215 * specified. It just means that the port isn't connected to
1216 * any external interface.
1218 intf = of_graph_get_remote_port_parent(ep_node);
1222 drm_of_component_match_add(master_dev, matchptr, compare_of,
1230 static int compare_name_mdp(struct device *dev, void *data)
1232 return (strstr(dev_name(dev), "mdp") != NULL);
1235 static int add_display_components(struct device *dev,
1236 struct component_match **matchptr)
1238 struct device *mdp_dev;
1242 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1243 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1244 * Populate the children devices, find the MDP5/DPU node, and then add
1245 * the interfaces to our components list.
1247 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1248 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1249 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1251 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1255 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1257 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1258 of_platform_depopulate(dev);
1262 put_device(mdp_dev);
1264 /* add the MDP component itself */
1265 drm_of_component_match_add(dev, matchptr, compare_of,
1272 ret = add_components_mdp(mdp_dev, matchptr);
1274 of_platform_depopulate(dev);
1280 * We don't know what's the best binding to link the gpu with the drm device.
1281 * Fow now, we just hunt for all the possible gpus that we support, and add them
1284 static const struct of_device_id msm_gpu_match[] = {
1285 { .compatible = "qcom,adreno" },
1286 { .compatible = "qcom,adreno-3xx" },
1287 { .compatible = "qcom,kgsl-3d0" },
1291 static int add_gpu_components(struct device *dev,
1292 struct component_match **matchptr)
1294 struct device_node *np;
1296 np = of_find_matching_node(NULL, msm_gpu_match);
1300 drm_of_component_match_add(dev, matchptr, compare_of, np);
1307 static int msm_drm_bind(struct device *dev)
1309 return msm_drm_init(dev, &msm_driver);
1312 static void msm_drm_unbind(struct device *dev)
1314 msm_drm_uninit(dev);
1317 static const struct component_master_ops msm_drm_ops = {
1318 .bind = msm_drm_bind,
1319 .unbind = msm_drm_unbind,
1326 static int msm_pdev_probe(struct platform_device *pdev)
1328 struct component_match *match = NULL;
1331 ret = add_display_components(&pdev->dev, &match);
1335 ret = add_gpu_components(&pdev->dev, &match);
1339 /* on all devices that I am aware of, iommu's which can map
1340 * any address the cpu can see are used:
1342 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1346 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1349 static int msm_pdev_remove(struct platform_device *pdev)
1351 component_master_del(&pdev->dev, &msm_drm_ops);
1352 of_platform_depopulate(&pdev->dev);
1357 static const struct of_device_id dt_match[] = {
1358 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1359 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1360 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1363 MODULE_DEVICE_TABLE(of, dt_match);
1365 static struct platform_driver msm_platform_driver = {
1366 .probe = msm_pdev_probe,
1367 .remove = msm_pdev_remove,
1370 .of_match_table = dt_match,
1375 static int __init msm_drm_register(void)
1385 msm_hdmi_register();
1387 return platform_driver_register(&msm_platform_driver);
1390 static void __exit msm_drm_unregister(void)
1393 platform_driver_unregister(&msm_platform_driver);
1394 msm_hdmi_unregister();
1395 adreno_unregister();
1396 msm_edp_unregister();
1397 msm_dsi_unregister();
1398 msm_mdp_unregister();
1399 msm_dpu_unregister();
1402 module_init(msm_drm_register);
1403 module_exit(msm_drm_unregister);
1405 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1406 MODULE_DESCRIPTION("MSM DRM Driver");
1407 MODULE_LICENSE("GPL");