1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/kthread.h>
10 #include <linux/uaccess.h>
11 #include <uapi/linux/sched/types.h>
13 #include <drm/drm_drv.h>
14 #include <drm/drm_file.h>
15 #include <drm/drm_ioctl.h>
16 #include <drm/drm_irq.h>
17 #include <drm/drm_prime.h>
18 #include <drm/drm_of.h>
19 #include <drm/drm_vblank.h>
22 #include "msm_debugfs.h"
23 #include "msm_fence.h"
27 #include "adreno/adreno_gpu.h"
31 * - 1.0.0 - initial interface
32 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
33 * - 1.2.0 - adds explicit fence support for submit ioctl
34 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
35 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
37 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
38 * GEM object's debug name
39 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
41 #define MSM_VERSION_MAJOR 1
42 #define MSM_VERSION_MINOR 5
43 #define MSM_VERSION_PATCHLEVEL 0
45 static const struct drm_mode_config_funcs mode_config_funcs = {
46 .fb_create = msm_framebuffer_create,
47 .output_poll_changed = drm_fb_helper_output_poll_changed,
48 .atomic_check = drm_atomic_helper_check,
49 .atomic_commit = drm_atomic_helper_commit,
52 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
53 .atomic_commit_tail = msm_atomic_commit_tail,
56 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
57 static bool reglog = false;
58 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
59 module_param(reglog, bool, 0600);
64 #ifdef CONFIG_DRM_FBDEV_EMULATION
65 static bool fbdev = true;
66 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67 module_param(fbdev, bool, 0600);
70 static char *vram = "16m";
71 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72 module_param(vram, charp, 0);
74 bool dumpstate = false;
75 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76 module_param(dumpstate, bool, 0600);
78 static bool modeset = true;
79 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80 module_param(modeset, bool, 0600);
86 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
92 snprintf(n, sizeof(n), "%s_clk", name);
94 for (i = 0; bulk && i < count; i++) {
95 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
103 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
108 clk = devm_clk_get(&pdev->dev, name);
109 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
112 snprintf(name2, sizeof(name2), "%s_clk", name);
114 clk = devm_clk_get(&pdev->dev, name2);
116 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
117 "\"%s\" instead of \"%s\"\n", name, name2);
122 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
125 struct resource *res;
130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
135 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
136 return ERR_PTR(-EINVAL);
139 size = resource_size(res);
141 ptr = devm_ioremap(&pdev->dev, res->start, size);
143 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
144 return ERR_PTR(-ENOMEM);
148 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
153 void msm_writel(u32 data, void __iomem *addr)
156 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
160 u32 msm_readl(const void __iomem *addr)
162 u32 val = readl(addr);
164 pr_err("IO:R %p %08x\n", addr, val);
168 struct msm_vblank_work {
169 struct work_struct work;
172 struct msm_drm_private *priv;
175 static void vblank_ctrl_worker(struct work_struct *work)
177 struct msm_vblank_work *vbl_work = container_of(work,
178 struct msm_vblank_work, work);
179 struct msm_drm_private *priv = vbl_work->priv;
180 struct msm_kms *kms = priv->kms;
182 if (vbl_work->enable)
183 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
185 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
190 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
191 int crtc_id, bool enable)
193 struct msm_vblank_work *vbl_work;
195 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
199 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
201 vbl_work->crtc_id = crtc_id;
202 vbl_work->enable = enable;
203 vbl_work->priv = priv;
205 queue_work(priv->wq, &vbl_work->work);
210 static int msm_drm_uninit(struct device *dev)
212 struct platform_device *pdev = to_platform_device(dev);
213 struct drm_device *ddev = platform_get_drvdata(pdev);
214 struct msm_drm_private *priv = ddev->dev_private;
215 struct msm_kms *kms = priv->kms;
216 struct msm_mdss *mdss = priv->mdss;
220 * Shutdown the hw if we're far enough along where things might be on.
221 * If we run this too early, we'll end up panicking in any variety of
222 * places. Since we don't register the drm device until late in
223 * msm_drm_init, drm_dev->registered is used as an indicator that the
224 * shutdown will be successful.
226 if (ddev->registered) {
227 drm_dev_unregister(ddev);
228 drm_atomic_helper_shutdown(ddev);
231 /* We must cancel and cleanup any pending vblank enable/disable
232 * work before drm_irq_uninstall() to avoid work re-enabling an
233 * irq after uninstall has disabled it.
236 flush_workqueue(priv->wq);
238 /* clean up event worker threads */
239 for (i = 0; i < priv->num_crtcs; i++) {
240 if (priv->event_thread[i].thread) {
241 kthread_destroy_worker(&priv->event_thread[i].worker);
242 priv->event_thread[i].thread = NULL;
246 msm_gem_shrinker_cleanup(ddev);
248 drm_kms_helper_poll_fini(ddev);
250 msm_perf_debugfs_cleanup(priv);
251 msm_rd_debugfs_cleanup(priv);
253 #ifdef CONFIG_DRM_FBDEV_EMULATION
254 if (fbdev && priv->fbdev)
255 msm_fbdev_free(ddev);
258 drm_mode_config_cleanup(ddev);
260 pm_runtime_get_sync(dev);
261 drm_irq_uninstall(ddev);
262 pm_runtime_put_sync(dev);
264 if (kms && kms->funcs)
265 kms->funcs->destroy(kms);
267 if (priv->vram.paddr) {
268 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
269 drm_mm_takedown(&priv->vram.mm);
270 dma_free_attrs(dev, priv->vram.size, NULL,
271 priv->vram.paddr, attrs);
274 component_unbind_all(dev, ddev);
276 if (mdss && mdss->funcs)
277 mdss->funcs->destroy(ddev);
279 ddev->dev_private = NULL;
282 destroy_workqueue(priv->wq);
292 static int get_mdp_ver(struct platform_device *pdev)
294 struct device *dev = &pdev->dev;
296 return (int) (unsigned long) of_device_get_match_data(dev);
299 #include <linux/of_address.h>
301 bool msm_use_mmu(struct drm_device *dev)
303 struct msm_drm_private *priv = dev->dev_private;
305 /* a2xx comes with its own MMU */
306 return priv->is_a2xx || iommu_present(&platform_bus_type);
309 static int msm_init_vram(struct drm_device *dev)
311 struct msm_drm_private *priv = dev->dev_private;
312 struct device_node *node;
313 unsigned long size = 0;
316 /* In the device-tree world, we could have a 'memory-region'
317 * phandle, which gives us a link to our "vram". Allocating
318 * is all nicely abstracted behind the dma api, but we need
319 * to know the entire size to allocate it all in one go. There
321 * 1) device with no IOMMU, in which case we need exclusive
322 * access to a VRAM carveout big enough for all gpu
324 * 2) device with IOMMU, but where the bootloader puts up
325 * a splash screen. In this case, the VRAM carveout
326 * need only be large enough for fbdev fb. But we need
327 * exclusive access to the buffer to avoid the kernel
328 * using those pages for other purposes (which appears
329 * as corruption on screen before we have a chance to
330 * load and do initial modeset)
333 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
336 ret = of_address_to_resource(node, 0, &r);
340 size = r.end - r.start;
341 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
343 /* if we have no IOMMU, then we need to use carveout allocator.
344 * Grab the entire CMA chunk carved out in early startup in
347 } else if (!msm_use_mmu(dev)) {
348 DRM_INFO("using %s VRAM carveout\n", vram);
349 size = memparse(vram, NULL);
353 unsigned long attrs = 0;
356 priv->vram.size = size;
358 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
359 spin_lock_init(&priv->vram.lock);
361 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
362 attrs |= DMA_ATTR_WRITE_COMBINE;
364 /* note that for no-kernel-mapping, the vaddr returned
365 * is bogus, but non-null if allocation succeeded:
367 p = dma_alloc_attrs(dev->dev, size,
368 &priv->vram.paddr, GFP_KERNEL, attrs);
370 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
371 priv->vram.paddr = 0;
375 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
376 (uint32_t)priv->vram.paddr,
377 (uint32_t)(priv->vram.paddr + size));
383 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
385 struct platform_device *pdev = to_platform_device(dev);
386 struct drm_device *ddev;
387 struct msm_drm_private *priv;
389 struct msm_mdss *mdss;
391 struct sched_param param;
393 ddev = drm_dev_alloc(drv, dev);
395 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
396 return PTR_ERR(ddev);
399 platform_set_drvdata(pdev, ddev);
401 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
404 goto err_put_drm_dev;
407 ddev->dev_private = priv;
410 switch (get_mdp_ver(pdev)) {
412 ret = mdp5_mdss_init(ddev);
415 ret = dpu_mdss_init(ddev);
426 priv->wq = alloc_ordered_workqueue("msm", 0);
428 INIT_WORK(&priv->free_work, msm_gem_free_work);
429 init_llist_head(&priv->free_list);
431 INIT_LIST_HEAD(&priv->inactive_list);
433 drm_mode_config_init(ddev);
435 /* Bind all our sub-components: */
436 ret = component_bind_all(dev, ddev);
438 goto err_destroy_mdss;
440 ret = msm_init_vram(ddev);
444 if (!dev->dma_parms) {
445 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms),
450 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
452 msm_gem_shrinker_init(ddev);
454 switch (get_mdp_ver(pdev)) {
456 kms = mdp4_kms_init(ddev);
460 kms = mdp5_kms_init(ddev);
463 kms = dpu_kms_init(ddev);
467 /* valid only for the dummy headless case, where of_node=NULL */
468 WARN_ON(dev->of_node);
474 DRM_DEV_ERROR(dev, "failed to load kms\n");
480 /* Enable normalization of plane zpos */
481 ddev->mode_config.normalize_zpos = true;
485 ret = kms->funcs->hw_init(kms);
487 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
492 ddev->mode_config.funcs = &mode_config_funcs;
493 ddev->mode_config.helper_private = &mode_config_helper_funcs;
496 * this priority was found during empiric testing to have appropriate
497 * realtime scheduling to process display updates and interact with
498 * other real time and normal priority task
500 param.sched_priority = 16;
501 for (i = 0; i < priv->num_crtcs; i++) {
502 /* initialize event thread */
503 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
504 kthread_init_worker(&priv->event_thread[i].worker);
505 priv->event_thread[i].dev = ddev;
506 priv->event_thread[i].thread =
507 kthread_run(kthread_worker_fn,
508 &priv->event_thread[i].worker,
509 "crtc_event:%d", priv->event_thread[i].crtc_id);
510 if (IS_ERR(priv->event_thread[i].thread)) {
511 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
512 priv->event_thread[i].thread = NULL;
516 ret = sched_setscheduler(priv->event_thread[i].thread,
519 dev_warn(dev, "event_thread set priority failed:%d\n",
523 ret = drm_vblank_init(ddev, priv->num_crtcs);
525 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
530 pm_runtime_get_sync(dev);
531 ret = drm_irq_install(ddev, kms->irq);
532 pm_runtime_put_sync(dev);
534 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
539 ret = drm_dev_register(ddev, 0);
543 drm_mode_config_reset(ddev);
545 #ifdef CONFIG_DRM_FBDEV_EMULATION
547 priv->fbdev = msm_fbdev_init(ddev);
550 ret = msm_debugfs_late_init(ddev);
554 drm_kms_helper_poll_init(ddev);
562 if (mdss && mdss->funcs)
563 mdss->funcs->destroy(ddev);
575 static void load_gpu(struct drm_device *dev)
577 static DEFINE_MUTEX(init_lock);
578 struct msm_drm_private *priv = dev->dev_private;
580 mutex_lock(&init_lock);
583 priv->gpu = adreno_load_gpu(dev);
585 mutex_unlock(&init_lock);
588 static int context_init(struct drm_device *dev, struct drm_file *file)
590 struct msm_drm_private *priv = dev->dev_private;
591 struct msm_file_private *ctx;
593 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
597 msm_submitqueue_init(dev, ctx);
599 ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
600 file->driver_priv = ctx;
605 static int msm_open(struct drm_device *dev, struct drm_file *file)
607 /* For now, load gpu on open.. to avoid the requirement of having
608 * firmware in the initrd.
612 return context_init(dev, file);
615 static void context_close(struct msm_file_private *ctx)
617 msm_submitqueue_close(ctx);
621 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
623 struct msm_drm_private *priv = dev->dev_private;
624 struct msm_file_private *ctx = file->driver_priv;
626 mutex_lock(&dev->struct_mutex);
627 if (ctx == priv->lastctx)
628 priv->lastctx = NULL;
629 mutex_unlock(&dev->struct_mutex);
634 static irqreturn_t msm_irq(int irq, void *arg)
636 struct drm_device *dev = arg;
637 struct msm_drm_private *priv = dev->dev_private;
638 struct msm_kms *kms = priv->kms;
640 return kms->funcs->irq(kms);
643 static void msm_irq_preinstall(struct drm_device *dev)
645 struct msm_drm_private *priv = dev->dev_private;
646 struct msm_kms *kms = priv->kms;
648 kms->funcs->irq_preinstall(kms);
651 static int msm_irq_postinstall(struct drm_device *dev)
653 struct msm_drm_private *priv = dev->dev_private;
654 struct msm_kms *kms = priv->kms;
657 if (kms->funcs->irq_postinstall)
658 return kms->funcs->irq_postinstall(kms);
663 static void msm_irq_uninstall(struct drm_device *dev)
665 struct msm_drm_private *priv = dev->dev_private;
666 struct msm_kms *kms = priv->kms;
668 kms->funcs->irq_uninstall(kms);
671 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
673 struct msm_drm_private *priv = dev->dev_private;
674 struct msm_kms *kms = priv->kms;
677 DBG("dev=%p, crtc=%u", dev, pipe);
678 return vblank_ctrl_queue_work(priv, pipe, true);
681 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
683 struct msm_drm_private *priv = dev->dev_private;
684 struct msm_kms *kms = priv->kms;
687 DBG("dev=%p, crtc=%u", dev, pipe);
688 vblank_ctrl_queue_work(priv, pipe, false);
695 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
696 struct drm_file *file)
698 struct msm_drm_private *priv = dev->dev_private;
699 struct drm_msm_param *args = data;
702 /* for now, we just have 3d pipe.. eventually this would need to
703 * be more clever to dispatch to appropriate gpu module:
705 if (args->pipe != MSM_PIPE_3D0)
713 return gpu->funcs->get_param(gpu, args->param, &args->value);
716 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
717 struct drm_file *file)
719 struct drm_msm_gem_new *args = data;
721 if (args->flags & ~MSM_BO_FLAGS) {
722 DRM_ERROR("invalid flags: %08x\n", args->flags);
726 return msm_gem_new_handle(dev, file, args->size,
727 args->flags, &args->handle, NULL);
730 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
732 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
735 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
736 struct drm_file *file)
738 struct drm_msm_gem_cpu_prep *args = data;
739 struct drm_gem_object *obj;
740 ktime_t timeout = to_ktime(args->timeout);
743 if (args->op & ~MSM_PREP_FLAGS) {
744 DRM_ERROR("invalid op: %08x\n", args->op);
748 obj = drm_gem_object_lookup(file, args->handle);
752 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
754 drm_gem_object_put_unlocked(obj);
759 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
760 struct drm_file *file)
762 struct drm_msm_gem_cpu_fini *args = data;
763 struct drm_gem_object *obj;
766 obj = drm_gem_object_lookup(file, args->handle);
770 ret = msm_gem_cpu_fini(obj);
772 drm_gem_object_put_unlocked(obj);
777 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
778 struct drm_gem_object *obj, uint64_t *iova)
780 struct msm_drm_private *priv = dev->dev_private;
786 * Don't pin the memory here - just get an address so that userspace can
789 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
792 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
793 struct drm_file *file)
795 struct drm_msm_gem_info *args = data;
796 struct drm_gem_object *obj;
797 struct msm_gem_object *msm_obj;
803 switch (args->info) {
804 case MSM_INFO_GET_OFFSET:
805 case MSM_INFO_GET_IOVA:
806 /* value returned as immediate, not pointer, so len==0: */
810 case MSM_INFO_SET_NAME:
811 case MSM_INFO_GET_NAME:
817 obj = drm_gem_object_lookup(file, args->handle);
821 msm_obj = to_msm_bo(obj);
823 switch (args->info) {
824 case MSM_INFO_GET_OFFSET:
825 args->value = msm_gem_mmap_offset(obj);
827 case MSM_INFO_GET_IOVA:
828 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
830 case MSM_INFO_SET_NAME:
831 /* length check should leave room for terminating null: */
832 if (args->len >= sizeof(msm_obj->name)) {
836 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
838 msm_obj->name[0] = '\0';
842 msm_obj->name[args->len] = '\0';
843 for (i = 0; i < args->len; i++) {
844 if (!isprint(msm_obj->name[i])) {
845 msm_obj->name[i] = '\0';
850 case MSM_INFO_GET_NAME:
851 if (args->value && (args->len < strlen(msm_obj->name))) {
855 args->len = strlen(msm_obj->name);
857 if (copy_to_user(u64_to_user_ptr(args->value),
858 msm_obj->name, args->len))
864 drm_gem_object_put_unlocked(obj);
869 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
870 struct drm_file *file)
872 struct msm_drm_private *priv = dev->dev_private;
873 struct drm_msm_wait_fence *args = data;
874 ktime_t timeout = to_ktime(args->timeout);
875 struct msm_gpu_submitqueue *queue;
876 struct msm_gpu *gpu = priv->gpu;
880 DRM_ERROR("invalid pad: %08x\n", args->pad);
887 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
891 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
894 msm_submitqueue_put(queue);
898 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
899 struct drm_file *file)
901 struct drm_msm_gem_madvise *args = data;
902 struct drm_gem_object *obj;
905 switch (args->madv) {
906 case MSM_MADV_DONTNEED:
907 case MSM_MADV_WILLNEED:
913 ret = mutex_lock_interruptible(&dev->struct_mutex);
917 obj = drm_gem_object_lookup(file, args->handle);
923 ret = msm_gem_madvise(obj, args->madv);
925 args->retained = ret;
929 drm_gem_object_put(obj);
932 mutex_unlock(&dev->struct_mutex);
937 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
938 struct drm_file *file)
940 struct drm_msm_submitqueue *args = data;
942 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
945 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
946 args->flags, &args->id);
949 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
950 struct drm_file *file)
952 return msm_submitqueue_query(dev, file->driver_priv, data);
955 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
956 struct drm_file *file)
958 u32 id = *(u32 *) data;
960 return msm_submitqueue_remove(file->driver_priv, id);
963 static const struct drm_ioctl_desc msm_ioctls[] = {
964 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
965 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
967 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
968 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
969 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
970 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
971 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
972 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
973 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
974 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
977 static const struct vm_operations_struct vm_ops = {
978 .fault = msm_gem_fault,
979 .open = drm_gem_vm_open,
980 .close = drm_gem_vm_close,
983 static const struct file_operations fops = {
984 .owner = THIS_MODULE,
986 .release = drm_release,
987 .unlocked_ioctl = drm_ioctl,
988 .compat_ioctl = drm_compat_ioctl,
992 .mmap = msm_gem_mmap,
995 static struct drm_driver msm_driver = {
996 .driver_features = DRIVER_GEM |
1001 .postclose = msm_postclose,
1002 .lastclose = drm_fb_helper_lastclose,
1003 .irq_handler = msm_irq,
1004 .irq_preinstall = msm_irq_preinstall,
1005 .irq_postinstall = msm_irq_postinstall,
1006 .irq_uninstall = msm_irq_uninstall,
1007 .enable_vblank = msm_enable_vblank,
1008 .disable_vblank = msm_disable_vblank,
1009 .gem_free_object_unlocked = msm_gem_free_object,
1010 .gem_vm_ops = &vm_ops,
1011 .dumb_create = msm_gem_dumb_create,
1012 .dumb_map_offset = msm_gem_dumb_map_offset,
1013 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1014 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1015 .gem_prime_pin = msm_gem_prime_pin,
1016 .gem_prime_unpin = msm_gem_prime_unpin,
1017 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1018 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1019 .gem_prime_vmap = msm_gem_prime_vmap,
1020 .gem_prime_vunmap = msm_gem_prime_vunmap,
1021 .gem_prime_mmap = msm_gem_prime_mmap,
1022 #ifdef CONFIG_DEBUG_FS
1023 .debugfs_init = msm_debugfs_init,
1025 .ioctls = msm_ioctls,
1026 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1029 .desc = "MSM Snapdragon DRM",
1031 .major = MSM_VERSION_MAJOR,
1032 .minor = MSM_VERSION_MINOR,
1033 .patchlevel = MSM_VERSION_PATCHLEVEL,
1036 #ifdef CONFIG_PM_SLEEP
1037 static int msm_pm_suspend(struct device *dev)
1039 struct drm_device *ddev = dev_get_drvdata(dev);
1040 struct msm_drm_private *priv = ddev->dev_private;
1042 if (WARN_ON(priv->pm_state))
1043 drm_atomic_state_put(priv->pm_state);
1045 priv->pm_state = drm_atomic_helper_suspend(ddev);
1046 if (IS_ERR(priv->pm_state)) {
1047 int ret = PTR_ERR(priv->pm_state);
1048 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1055 static int msm_pm_resume(struct device *dev)
1057 struct drm_device *ddev = dev_get_drvdata(dev);
1058 struct msm_drm_private *priv = ddev->dev_private;
1061 if (WARN_ON(!priv->pm_state))
1064 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1066 priv->pm_state = NULL;
1073 static int msm_runtime_suspend(struct device *dev)
1075 struct drm_device *ddev = dev_get_drvdata(dev);
1076 struct msm_drm_private *priv = ddev->dev_private;
1077 struct msm_mdss *mdss = priv->mdss;
1081 if (mdss && mdss->funcs)
1082 return mdss->funcs->disable(mdss);
1087 static int msm_runtime_resume(struct device *dev)
1089 struct drm_device *ddev = dev_get_drvdata(dev);
1090 struct msm_drm_private *priv = ddev->dev_private;
1091 struct msm_mdss *mdss = priv->mdss;
1095 if (mdss && mdss->funcs)
1096 return mdss->funcs->enable(mdss);
1102 static const struct dev_pm_ops msm_pm_ops = {
1103 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1104 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1108 * Componentized driver support:
1112 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1113 * so probably some room for some helpers
1115 static int compare_of(struct device *dev, void *data)
1117 return dev->of_node == data;
1121 * Identify what components need to be added by parsing what remote-endpoints
1122 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1123 * is no external component that we need to add since LVDS is within MDP4
1126 static int add_components_mdp(struct device *mdp_dev,
1127 struct component_match **matchptr)
1129 struct device_node *np = mdp_dev->of_node;
1130 struct device_node *ep_node;
1131 struct device *master_dev;
1134 * on MDP4 based platforms, the MDP platform device is the component
1135 * master that adds other display interface components to itself.
1137 * on MDP5 based platforms, the MDSS platform device is the component
1138 * master that adds MDP5 and other display interface components to
1141 if (of_device_is_compatible(np, "qcom,mdp4"))
1142 master_dev = mdp_dev;
1144 master_dev = mdp_dev->parent;
1146 for_each_endpoint_of_node(np, ep_node) {
1147 struct device_node *intf;
1148 struct of_endpoint ep;
1151 ret = of_graph_parse_endpoint(ep_node, &ep);
1153 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1154 of_node_put(ep_node);
1159 * The LCDC/LVDS port on MDP4 is a speacial case where the
1160 * remote-endpoint isn't a component that we need to add
1162 if (of_device_is_compatible(np, "qcom,mdp4") &&
1167 * It's okay if some of the ports don't have a remote endpoint
1168 * specified. It just means that the port isn't connected to
1169 * any external interface.
1171 intf = of_graph_get_remote_port_parent(ep_node);
1175 if (of_device_is_available(intf))
1176 drm_of_component_match_add(master_dev, matchptr,
1185 static int compare_name_mdp(struct device *dev, void *data)
1187 return (strstr(dev_name(dev), "mdp") != NULL);
1190 static int add_display_components(struct device *dev,
1191 struct component_match **matchptr)
1193 struct device *mdp_dev;
1197 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1198 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1199 * Populate the children devices, find the MDP5/DPU node, and then add
1200 * the interfaces to our components list.
1202 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1203 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") ||
1204 of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) {
1205 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1207 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1211 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1213 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1214 of_platform_depopulate(dev);
1218 put_device(mdp_dev);
1220 /* add the MDP component itself */
1221 drm_of_component_match_add(dev, matchptr, compare_of,
1228 ret = add_components_mdp(mdp_dev, matchptr);
1230 of_platform_depopulate(dev);
1236 * We don't know what's the best binding to link the gpu with the drm device.
1237 * Fow now, we just hunt for all the possible gpus that we support, and add them
1240 static const struct of_device_id msm_gpu_match[] = {
1241 { .compatible = "qcom,adreno" },
1242 { .compatible = "qcom,adreno-3xx" },
1243 { .compatible = "amd,imageon" },
1244 { .compatible = "qcom,kgsl-3d0" },
1248 static int add_gpu_components(struct device *dev,
1249 struct component_match **matchptr)
1251 struct device_node *np;
1253 np = of_find_matching_node(NULL, msm_gpu_match);
1257 if (of_device_is_available(np))
1258 drm_of_component_match_add(dev, matchptr, compare_of, np);
1265 static int msm_drm_bind(struct device *dev)
1267 return msm_drm_init(dev, &msm_driver);
1270 static void msm_drm_unbind(struct device *dev)
1272 msm_drm_uninit(dev);
1275 static const struct component_master_ops msm_drm_ops = {
1276 .bind = msm_drm_bind,
1277 .unbind = msm_drm_unbind,
1284 static int msm_pdev_probe(struct platform_device *pdev)
1286 struct component_match *match = NULL;
1289 if (get_mdp_ver(pdev)) {
1290 ret = add_display_components(&pdev->dev, &match);
1295 ret = add_gpu_components(&pdev->dev, &match);
1299 /* on all devices that I am aware of, iommu's which can map
1300 * any address the cpu can see are used:
1302 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1306 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1313 of_platform_depopulate(&pdev->dev);
1317 static int msm_pdev_remove(struct platform_device *pdev)
1319 component_master_del(&pdev->dev, &msm_drm_ops);
1320 of_platform_depopulate(&pdev->dev);
1325 static const struct of_device_id dt_match[] = {
1326 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1327 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1328 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1329 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1332 MODULE_DEVICE_TABLE(of, dt_match);
1334 static struct platform_driver msm_platform_driver = {
1335 .probe = msm_pdev_probe,
1336 .remove = msm_pdev_remove,
1339 .of_match_table = dt_match,
1344 static int __init msm_drm_register(void)
1354 msm_hdmi_register();
1356 return platform_driver_register(&msm_platform_driver);
1359 static void __exit msm_drm_unregister(void)
1362 platform_driver_unregister(&msm_platform_driver);
1363 msm_hdmi_unregister();
1364 adreno_unregister();
1365 msm_edp_unregister();
1366 msm_dsi_unregister();
1367 msm_mdp_unregister();
1368 msm_dpu_unregister();
1371 module_init(msm_drm_register);
1372 module_exit(msm_drm_unregister);
1374 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1375 MODULE_DESCRIPTION("MSM DRM Driver");
1376 MODULE_LICENSE("GPL");