2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/class.h>
27 #include <core/client.h>
28 #include <core/handle.h>
29 #include <core/engctx.h>
30 #include <core/enum.h>
32 #include <subdev/fb.h>
33 #include <subdev/vm.h>
34 #include <subdev/timer.h>
36 #include <engine/fifo.h>
37 #include <engine/graph.h>
41 struct nv50_graph_priv {
42 struct nouveau_graph base;
47 struct nv50_graph_chan {
48 struct nouveau_graph_chan base;
52 nv50_graph_units(struct nouveau_graph *graph)
54 struct nv50_graph_priv *priv = (void *)graph;
56 return nv_rd32(priv, 0x1540);
59 /*******************************************************************************
60 * Graphics object classes
61 ******************************************************************************/
64 nv50_graph_object_ctor(struct nouveau_object *parent,
65 struct nouveau_object *engine,
66 struct nouveau_oclass *oclass, void *data, u32 size,
67 struct nouveau_object **pobject)
69 struct nouveau_gpuobj *obj;
72 ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
74 *pobject = nv_object(obj);
78 nv_wo32(obj, 0x00, nv_mclass(obj));
79 nv_wo32(obj, 0x04, 0x00000000);
80 nv_wo32(obj, 0x08, 0x00000000);
81 nv_wo32(obj, 0x0c, 0x00000000);
85 static struct nouveau_ofuncs
87 .ctor = nv50_graph_object_ctor,
88 .dtor = _nouveau_gpuobj_dtor,
89 .init = _nouveau_gpuobj_init,
90 .fini = _nouveau_gpuobj_fini,
91 .rd32 = _nouveau_gpuobj_rd32,
92 .wr32 = _nouveau_gpuobj_wr32,
95 static struct nouveau_oclass
96 nv50_graph_sclass[] = {
97 { 0x0030, &nv50_graph_ofuncs },
98 { 0x502d, &nv50_graph_ofuncs },
99 { 0x5039, &nv50_graph_ofuncs },
100 { 0x5097, &nv50_graph_ofuncs },
101 { 0x50c0, &nv50_graph_ofuncs },
105 static struct nouveau_oclass
106 nv84_graph_sclass[] = {
107 { 0x0030, &nv50_graph_ofuncs },
108 { 0x502d, &nv50_graph_ofuncs },
109 { 0x5039, &nv50_graph_ofuncs },
110 { 0x50c0, &nv50_graph_ofuncs },
111 { 0x8297, &nv50_graph_ofuncs },
115 static struct nouveau_oclass
116 nva0_graph_sclass[] = {
117 { 0x0030, &nv50_graph_ofuncs },
118 { 0x502d, &nv50_graph_ofuncs },
119 { 0x5039, &nv50_graph_ofuncs },
120 { 0x50c0, &nv50_graph_ofuncs },
121 { 0x8397, &nv50_graph_ofuncs },
125 static struct nouveau_oclass
126 nva3_graph_sclass[] = {
127 { 0x0030, &nv50_graph_ofuncs },
128 { 0x502d, &nv50_graph_ofuncs },
129 { 0x5039, &nv50_graph_ofuncs },
130 { 0x50c0, &nv50_graph_ofuncs },
131 { 0x8597, &nv50_graph_ofuncs },
132 { 0x85c0, &nv50_graph_ofuncs },
136 static struct nouveau_oclass
137 nvaf_graph_sclass[] = {
138 { 0x0030, &nv50_graph_ofuncs },
139 { 0x502d, &nv50_graph_ofuncs },
140 { 0x5039, &nv50_graph_ofuncs },
141 { 0x50c0, &nv50_graph_ofuncs },
142 { 0x85c0, &nv50_graph_ofuncs },
143 { 0x8697, &nv50_graph_ofuncs },
147 /*******************************************************************************
149 ******************************************************************************/
152 nv50_graph_context_ctor(struct nouveau_object *parent,
153 struct nouveau_object *engine,
154 struct nouveau_oclass *oclass, void *data, u32 size,
155 struct nouveau_object **pobject)
157 struct nv50_graph_priv *priv = (void *)engine;
158 struct nv50_graph_chan *chan;
161 ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
163 NVOBJ_FLAG_ZERO_ALLOC, &chan);
164 *pobject = nv_object(chan);
168 nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
172 static struct nouveau_oclass
173 nv50_graph_cclass = {
174 .handle = NV_ENGCTX(GR, 0x50),
175 .ofuncs = &(struct nouveau_ofuncs) {
176 .ctor = nv50_graph_context_ctor,
177 .dtor = _nouveau_graph_context_dtor,
178 .init = _nouveau_graph_context_init,
179 .fini = _nouveau_graph_context_fini,
180 .rd32 = _nouveau_graph_context_rd32,
181 .wr32 = _nouveau_graph_context_wr32,
185 /*******************************************************************************
186 * PGRAPH engine/subdev functions
187 ******************************************************************************/
189 static const struct nouveau_bitfield nv50_pgraph_status[] = {
190 { 0x00000001, "BUSY" }, /* set when any bit is set */
191 { 0x00000002, "DISPATCH" },
192 { 0x00000004, "UNK2" },
193 { 0x00000008, "UNK3" },
194 { 0x00000010, "UNK4" },
195 { 0x00000020, "UNK5" },
196 { 0x00000040, "M2MF" },
197 { 0x00000080, "UNK7" },
198 { 0x00000100, "CTXPROG" },
199 { 0x00000200, "VFETCH" },
200 { 0x00000400, "CCACHE_UNK4" },
201 { 0x00000800, "STRMOUT_GSCHED_UNK5" },
202 { 0x00001000, "UNK14XX" },
203 { 0x00002000, "UNK24XX_CSCHED" },
204 { 0x00004000, "UNK1CXX" },
205 { 0x00008000, "CLIPID" },
206 { 0x00010000, "ZCULL" },
207 { 0x00020000, "ENG2D" },
208 { 0x00040000, "UNK34XX" },
209 { 0x00080000, "TPRAST" },
210 { 0x00100000, "TPROP" },
211 { 0x00200000, "TEX" },
212 { 0x00400000, "TPVP" },
213 { 0x00800000, "MP" },
214 { 0x01000000, "ROP" },
218 static const char *const nv50_pgraph_vstatus_0[] = {
219 "VFETCH", "CCACHE", "UNK4", "UNK5", "GSCHED", "STRMOUT", "UNK14XX", NULL
222 static const char *const nv50_pgraph_vstatus_1[] = {
223 "TPRAST", "TPROP", "TEXTURE", "TPVP", "MP", NULL
226 static const char *const nv50_pgraph_vstatus_2[] = {
227 "UNK24XX", "CSCHED", "UNK1CXX", "CLIPID", "ZCULL", "ENG2D", "UNK34XX",
231 static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
232 const char *const units[], u32 status)
236 nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
238 for (i = 0; units[i] && status; i++) {
239 if ((status & 7) == 1)
240 pr_cont(" %s", units[i]);
244 pr_cont(" (invalid: 0x%x)", status);
249 nv84_graph_tlb_flush(struct nouveau_engine *engine)
251 struct nouveau_timer *ptimer = nouveau_timer(engine);
252 struct nv50_graph_priv *priv = (void *)engine;
253 bool idle, timeout = false;
258 spin_lock_irqsave(&priv->lock, flags);
259 nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
261 start = ptimer->read(ptimer);
265 for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
270 for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
275 for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
280 !(timeout = ptimer->read(ptimer) - start > 2000000000));
283 nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
285 tmp = nv_rd32(priv, 0x400700);
286 nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp);
287 nouveau_bitfield_print(nv50_pgraph_status, tmp);
290 nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0,
291 nv_rd32(priv, 0x400380));
292 nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1,
293 nv_rd32(priv, 0x400384));
294 nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2,
295 nv_rd32(priv, 0x400388));
299 nv_wr32(priv, 0x100c80, 0x00000001);
300 if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
301 nv_error(priv, "vm flush timeout\n");
302 nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
303 spin_unlock_irqrestore(&priv->lock, flags);
304 return timeout ? -EBUSY : 0;
307 static const struct nouveau_enum nv50_mp_exec_error_names[] = {
308 { 3, "STACK_UNDERFLOW", NULL },
309 { 4, "QUADON_ACTIVE", NULL },
310 { 8, "TIMEOUT", NULL },
311 { 0x10, "INVALID_OPCODE", NULL },
312 { 0x40, "BREAKPOINT", NULL },
316 static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
317 { 0x00000001, "NOTIFY" },
318 { 0x00000002, "IN" },
319 { 0x00000004, "OUT" },
323 static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
324 { 0x00000001, "FAULT" },
328 static const struct nouveau_bitfield nv50_graph_trap_strmout[] = {
329 { 0x00000001, "FAULT" },
333 static const struct nouveau_bitfield nv50_graph_trap_ccache[] = {
334 { 0x00000001, "FAULT" },
338 /* There must be a *lot* of these. Will take some time to gather them up. */
339 const struct nouveau_enum nv50_data_error_names[] = {
340 { 0x00000003, "INVALID_OPERATION", NULL },
341 { 0x00000004, "INVALID_VALUE", NULL },
342 { 0x00000005, "INVALID_ENUM", NULL },
343 { 0x00000008, "INVALID_OBJECT", NULL },
344 { 0x00000009, "READ_ONLY_OBJECT", NULL },
345 { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
346 { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
347 { 0x0000000c, "INVALID_BITFIELD", NULL },
348 { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
349 { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
350 { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
351 { 0x00000010, "RT_DOUBLE_BIND", NULL },
352 { 0x00000011, "RT_TYPES_MISMATCH", NULL },
353 { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
354 { 0x00000015, "FP_TOO_FEW_REGS", NULL },
355 { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
356 { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
357 { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
358 { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
359 { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
360 { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
361 { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
362 { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
363 { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
364 { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
365 { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
366 { 0x00000024, "VP_ZERO_INPUTS", NULL },
367 { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
368 { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
369 { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
370 { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
371 { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
372 { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
373 { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
374 { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
375 { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
376 { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
377 { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
378 { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
379 { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
380 { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
381 { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
385 static const struct nouveau_bitfield nv50_graph_intr_name[] = {
386 { 0x00000001, "NOTIFY" },
387 { 0x00000002, "COMPUTE_QUERY" },
388 { 0x00000010, "ILLEGAL_MTHD" },
389 { 0x00000020, "ILLEGAL_CLASS" },
390 { 0x00000040, "DOUBLE_NOTIFY" },
391 { 0x00001000, "CONTEXT_SWITCH" },
392 { 0x00010000, "BUFFER_NOTIFY" },
393 { 0x00100000, "DATA_ERROR" },
394 { 0x00200000, "TRAP" },
395 { 0x01000000, "SINGLE_STEP" },
399 static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
400 { 0x00000004, "SURF_WIDTH_OVERRUN" },
401 { 0x00000008, "SURF_HEIGHT_OVERRUN" },
402 { 0x00000010, "DST2D_FAULT" },
403 { 0x00000020, "ZETA_FAULT" },
404 { 0x00000040, "RT_FAULT" },
405 { 0x00000080, "CUDA_FAULT" },
406 { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
407 { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
408 { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
409 { 0x00000800, "DST2D_LINEAR_MISMATCH" },
410 { 0x00001000, "RT_LINEAR_MISMATCH" },
415 nv50_priv_prop_trap(struct nv50_graph_priv *priv,
416 u32 ustatus_addr, u32 ustatus, u32 tp)
418 u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
419 u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
420 u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
421 u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
422 u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
423 u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
424 u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
426 /* CUDA memory: l[], g[] or stack. */
427 if (ustatus & 0x00000080) {
428 if (e18 & 0x80000000) {
429 /* g[] read fault? */
430 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
431 tp, e14, e10 | ((e18 >> 24) & 0x1f));
433 } else if (e18 & 0xc) {
434 /* g[] write fault? */
435 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
436 tp, e14, e10 | ((e18 >> 7) & 0x1f));
439 nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
442 ustatus &= ~0x00000080;
445 nv_error(priv, "TRAP_PROP - TP %d -", tp);
446 nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
447 pr_cont(" - Address %02x%08x\n", e14, e10);
449 nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
450 tp, e0c, e18, e1c, e20, e24);
454 nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
456 u32 units = nv_rd32(priv, 0x1540);
457 u32 addr, mp10, status, pc, oplow, ophigh;
460 for (i = 0; i < 4; i++) {
461 if (!(units & 1 << (i+24)))
463 if (nv_device(priv)->chipset < 0xa0)
464 addr = 0x408200 + (tpid << 12) + (i << 7);
466 addr = 0x408100 + (tpid << 11) + (i << 7);
467 mp10 = nv_rd32(priv, addr + 0x10);
468 status = nv_rd32(priv, addr + 0x14);
472 nv_rd32(priv, addr + 0x20);
473 pc = nv_rd32(priv, addr + 0x24);
474 oplow = nv_rd32(priv, addr + 0x70);
475 ophigh = nv_rd32(priv, addr + 0x74);
476 nv_error(priv, "TRAP_MP_EXEC - "
477 "TP %d MP %d: ", tpid, i);
478 nouveau_enum_print(nv50_mp_exec_error_names, status);
479 pr_cont(" at %06x warp %d, opcode %08x %08x\n",
480 pc&0xffffff, pc >> 24,
483 nv_wr32(priv, addr + 0x10, mp10);
484 nv_wr32(priv, addr + 0x14, 0);
488 nv_error(priv, "TRAP_MP_EXEC - TP %d: "
489 "No MPs claiming errors?\n", tpid);
493 nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
494 u32 ustatus_new, int display, const char *name)
497 u32 units = nv_rd32(priv, 0x1540);
499 u32 ustatus_addr, ustatus;
500 for (i = 0; i < 16; i++) {
501 if (!(units & (1 << i)))
503 if (nv_device(priv)->chipset < 0xa0)
504 ustatus_addr = ustatus_old + (i << 12);
506 ustatus_addr = ustatus_new + (i << 11);
507 ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff;
512 case 6: /* texture error... unknown for now */
514 nv_error(priv, "magic set %d:\n", i);
515 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
516 nv_error(priv, "\t0x%08x: 0x%08x\n", r,
520 case 7: /* MP error */
521 if (ustatus & 0x04030000) {
522 nv50_priv_mp_trap(priv, i, display);
523 ustatus &= ~0x04030000;
526 case 8: /* PROP error */
529 priv, ustatus_addr, ustatus, i);
535 nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
537 nv_wr32(priv, ustatus_addr, 0xc0000000);
541 nv_warn(priv, "%s - No TPs claiming errors?\n", name);
545 nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
546 int chid, u64 inst, struct nouveau_object *engctx)
548 u32 status = nv_rd32(priv, 0x400108);
551 if (!status && display) {
552 nv_error(priv, "TRAP: no units reporting traps?\n");
556 /* DISPATCH: Relays commands to other units and handles NOTIFY,
557 * COND, QUERY. If you get a trap from it, the command is still stuck
558 * in DISPATCH and you need to do something about it. */
559 if (status & 0x001) {
560 ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff;
561 if (!ustatus && display) {
562 nv_error(priv, "TRAP_DISPATCH - no ustatus?\n");
565 nv_wr32(priv, 0x400500, 0x00000000);
567 /* Known to be triggered by screwed up NOTIFY and COND... */
568 if (ustatus & 0x00000001) {
569 u32 addr = nv_rd32(priv, 0x400808);
570 u32 subc = (addr & 0x00070000) >> 16;
571 u32 mthd = (addr & 0x00001ffc);
572 u32 datal = nv_rd32(priv, 0x40080c);
573 u32 datah = nv_rd32(priv, 0x400810);
574 u32 class = nv_rd32(priv, 0x400814);
575 u32 r848 = nv_rd32(priv, 0x400848);
577 nv_error(priv, "TRAP DISPATCH_FAULT\n");
578 if (display && (addr & 0x80000000)) {
580 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
582 nouveau_client_name(engctx), subc,
583 class, mthd, datah, datal, addr, r848);
586 nv_error(priv, "no stuck command?\n");
589 nv_wr32(priv, 0x400808, 0);
590 nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3);
591 nv_wr32(priv, 0x400848, 0);
592 ustatus &= ~0x00000001;
595 if (ustatus & 0x00000002) {
596 u32 addr = nv_rd32(priv, 0x40084c);
597 u32 subc = (addr & 0x00070000) >> 16;
598 u32 mthd = (addr & 0x00001ffc);
599 u32 data = nv_rd32(priv, 0x40085c);
600 u32 class = nv_rd32(priv, 0x400814);
602 nv_error(priv, "TRAP DISPATCH_QUERY\n");
603 if (display && (addr & 0x80000000)) {
605 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
607 nouveau_client_name(engctx), subc,
608 class, mthd, data, addr);
611 nv_error(priv, "no stuck command?\n");
614 nv_wr32(priv, 0x40084c, 0);
615 ustatus &= ~0x00000002;
618 if (ustatus && display) {
619 nv_error(priv, "TRAP_DISPATCH (unknown "
620 "0x%08x)\n", ustatus);
623 nv_wr32(priv, 0x400804, 0xc0000000);
624 nv_wr32(priv, 0x400108, 0x001);
630 /* M2MF: Memory to memory copy engine. */
631 if (status & 0x002) {
632 u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
634 nv_error(priv, "TRAP_M2MF");
635 nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
637 nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
638 nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
639 nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
643 /* No sane way found yet -- just reset the bugger. */
644 nv_wr32(priv, 0x400040, 2);
645 nv_wr32(priv, 0x400040, 0);
646 nv_wr32(priv, 0x406800, 0xc0000000);
647 nv_wr32(priv, 0x400108, 0x002);
651 /* VFETCH: Fetches data from vertex buffers. */
652 if (status & 0x004) {
653 u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
655 nv_error(priv, "TRAP_VFETCH");
656 nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
658 nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
659 nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
660 nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
663 nv_wr32(priv, 0x400c04, 0xc0000000);
664 nv_wr32(priv, 0x400108, 0x004);
668 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
669 if (status & 0x008) {
670 ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
672 nv_error(priv, "TRAP_STRMOUT");
673 nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
675 nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
676 nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
677 nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
681 /* No sane way found yet -- just reset the bugger. */
682 nv_wr32(priv, 0x400040, 0x80);
683 nv_wr32(priv, 0x400040, 0);
684 nv_wr32(priv, 0x401800, 0xc0000000);
685 nv_wr32(priv, 0x400108, 0x008);
689 /* CCACHE: Handles code and c[] caches and fills them. */
690 if (status & 0x010) {
691 ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
693 nv_error(priv, "TRAP_CCACHE");
694 nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
696 nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
698 nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
699 nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c),
700 nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014),
701 nv_rd32(priv, 0x40501c));
705 nv_wr32(priv, 0x405018, 0xc0000000);
706 nv_wr32(priv, 0x400108, 0x010);
710 /* Unknown, not seen yet... 0x402000 is the only trap status reg
711 * remaining, so try to handle it anyway. Perhaps related to that
712 * unknown DMA slot on tesla? */
714 ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff;
716 nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus);
717 nv_wr32(priv, 0x402000, 0xc0000000);
718 /* no status modifiction on purpose */
721 /* TEXTURE: CUDA texturing units */
722 if (status & 0x040) {
723 nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display,
725 nv_wr32(priv, 0x400108, 0x040);
729 /* MP: CUDA execution engines. */
730 if (status & 0x080) {
731 nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display,
733 nv_wr32(priv, 0x400108, 0x080);
737 /* PROP: Handles TP-initiated uncached memory accesses:
738 * l[], g[], stack, 2d surfaces, render targets. */
739 if (status & 0x100) {
740 nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
742 nv_wr32(priv, 0x400108, 0x100);
748 nv_error(priv, "TRAP: unknown 0x%08x\n", status);
749 nv_wr32(priv, 0x400108, status);
756 nv50_graph_intr(struct nouveau_subdev *subdev)
758 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
759 struct nouveau_engine *engine = nv_engine(subdev);
760 struct nouveau_object *engctx;
761 struct nouveau_handle *handle = NULL;
762 struct nv50_graph_priv *priv = (void *)subdev;
763 u32 stat = nv_rd32(priv, 0x400100);
764 u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
765 u32 addr = nv_rd32(priv, 0x400704);
766 u32 subc = (addr & 0x00070000) >> 16;
767 u32 mthd = (addr & 0x00001ffc);
768 u32 data = nv_rd32(priv, 0x400708);
769 u32 class = nv_rd32(priv, 0x400814);
770 u32 show = stat, show_bitfield = stat;
773 engctx = nouveau_engctx_get(engine, inst);
774 chid = pfifo->chid(pfifo, engctx);
776 if (stat & 0x00000010) {
777 handle = nouveau_handle_get_class(engctx, class);
778 if (handle && !nv_call(handle->object, mthd, data))
780 nouveau_handle_put(handle);
783 if (show & 0x00100000) {
784 u32 ecode = nv_rd32(priv, 0x400110);
785 nv_error(priv, "DATA_ERROR ");
786 nouveau_enum_print(nv50_data_error_names, ecode);
788 show_bitfield &= ~0x00100000;
791 if (stat & 0x00200000) {
792 if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
795 show_bitfield &= ~0x00200000;
798 nv_wr32(priv, 0x400100, stat);
799 nv_wr32(priv, 0x400500, 0x00010001);
802 show &= show_bitfield;
804 nv_error(priv, "%s", "");
805 nouveau_bitfield_print(nv50_graph_intr_name, show);
809 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
810 chid, (u64)inst << 12, nouveau_client_name(engctx),
811 subc, class, mthd, data);
814 if (nv_rd32(priv, 0x400824) & (1 << 31))
815 nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
817 nouveau_engctx_put(engctx);
821 nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
822 struct nouveau_oclass *oclass, void *data, u32 size,
823 struct nouveau_object **pobject)
825 struct nv50_graph_priv *priv;
828 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
829 *pobject = nv_object(priv);
833 nv_subdev(priv)->unit = 0x00201000;
834 nv_subdev(priv)->intr = nv50_graph_intr;
835 nv_engine(priv)->cclass = &nv50_graph_cclass;
837 priv->base.units = nv50_graph_units;
839 switch (nv_device(priv)->chipset) {
841 nv_engine(priv)->sclass = nv50_graph_sclass;
849 nv_engine(priv)->sclass = nv84_graph_sclass;
854 nv_engine(priv)->sclass = nva0_graph_sclass;
859 nv_engine(priv)->sclass = nva3_graph_sclass;
862 nv_engine(priv)->sclass = nvaf_graph_sclass;
867 /* unfortunate hw bug workaround... */
868 if (nv_device(priv)->chipset != 0x50 &&
869 nv_device(priv)->chipset != 0xac)
870 nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
872 spin_lock_init(&priv->lock);
877 nv50_graph_init(struct nouveau_object *object)
879 struct nv50_graph_priv *priv = (void *)object;
882 ret = nouveau_graph_init(&priv->base);
886 /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
887 nv_wr32(priv, 0x40008c, 0x00000004);
889 /* reset/enable traps and interrupts */
890 nv_wr32(priv, 0x400804, 0xc0000000);
891 nv_wr32(priv, 0x406800, 0xc0000000);
892 nv_wr32(priv, 0x400c04, 0xc0000000);
893 nv_wr32(priv, 0x401800, 0xc0000000);
894 nv_wr32(priv, 0x405018, 0xc0000000);
895 nv_wr32(priv, 0x402000, 0xc0000000);
897 units = nv_rd32(priv, 0x001540);
898 for (i = 0; i < 16; i++) {
899 if (!(units & (1 << i)))
902 if (nv_device(priv)->chipset < 0xa0) {
903 nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000);
904 nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000);
905 nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000);
907 nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000);
908 nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000);
909 nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000);
913 nv_wr32(priv, 0x400108, 0xffffffff);
914 nv_wr32(priv, 0x400138, 0xffffffff);
915 nv_wr32(priv, 0x400100, 0xffffffff);
916 nv_wr32(priv, 0x40013c, 0xffffffff);
917 nv_wr32(priv, 0x400500, 0x00010001);
919 /* upload context program, initialise ctxctl defaults */
920 ret = nv50_grctx_init(nv_device(priv), &priv->size);
924 nv_wr32(priv, 0x400824, 0x00000000);
925 nv_wr32(priv, 0x400828, 0x00000000);
926 nv_wr32(priv, 0x40082c, 0x00000000);
927 nv_wr32(priv, 0x400830, 0x00000000);
928 nv_wr32(priv, 0x40032c, 0x00000000);
929 nv_wr32(priv, 0x400330, 0x00000000);
931 /* some unknown zcull magic */
932 switch (nv_device(priv)->chipset & 0xf0) {
936 nv_wr32(priv, 0x402ca8, 0x00000800);
940 nv_wr32(priv, 0x402cc0, 0x00000000);
941 if (nv_device(priv)->chipset == 0xa0 ||
942 nv_device(priv)->chipset == 0xaa ||
943 nv_device(priv)->chipset == 0xac) {
944 nv_wr32(priv, 0x402ca8, 0x00000802);
946 nv_wr32(priv, 0x402cc0, 0x00000000);
947 nv_wr32(priv, 0x402ca8, 0x00000002);
953 /* zero out zcull regions */
954 for (i = 0; i < 8; i++) {
955 nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000);
956 nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000);
957 nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000);
958 nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000);
963 struct nouveau_oclass
964 nv50_graph_oclass = {
965 .handle = NV_ENGINE(GR, 0x50),
966 .ofuncs = &(struct nouveau_ofuncs) {
967 .ctor = nv50_graph_ctor,
968 .dtor = _nouveau_graph_dtor,
969 .init = nv50_graph_init,
970 .fini = _nouveau_graph_fini,