drivers/gpu/drm/nouveau/core/engine/graph/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/class.h>
  27 #include <core/client.h>
  28 #include <core/handle.h>
  29 #include <core/engctx.h>
  30 #include <core/enum.h>
  31
  32 #include <subdev/fb.h>
  33 #include <subdev/vm.h>
  34 #include <subdev/timer.h>
  35
  36 #include <engine/fifo.h>
  37 #include <engine/graph.h>
  38
  39 #include "nv50.h"
  40
  41 struct nv50_graph_priv {
  42         struct nouveau_graph base;
  43         spinlock_t lock;
  44         u32 size;
  45 };
  46
  47 struct nv50_graph_chan {
  48         struct nouveau_graph_chan base;
  49 };
  50
  51 static u64
  52 nv50_graph_units(struct nouveau_graph *graph)
  53 {
  54         struct nv50_graph_priv *priv = (void *)graph;
  55
  56         return nv_rd32(priv, 0x1540);
  57 }
  58
  59 /*******************************************************************************
  60  * Graphics object classes
  61  ******************************************************************************/
  62
  63 static int
  64 nv50_graph_object_ctor(struct nouveau_object *parent,
  65                        struct nouveau_object *engine,
  66                        struct nouveau_oclass *oclass, void *data, u32 size,
  67                        struct nouveau_object **pobject)
  68 {
  69         struct nouveau_gpuobj *obj;
  70         int ret;
  71
  72         ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
  73                                     16, 16, 0, &obj);
  74         *pobject = nv_object(obj);
  75         if (ret)
  76                 return ret;
  77
  78         nv_wo32(obj, 0x00, nv_mclass(obj));
  79         nv_wo32(obj, 0x04, 0x00000000);
  80         nv_wo32(obj, 0x08, 0x00000000);
  81         nv_wo32(obj, 0x0c, 0x00000000);
  82         return 0;
  83 }
  84
  85 static struct nouveau_ofuncs
  86 nv50_graph_ofuncs = {
  87         .ctor = nv50_graph_object_ctor,
  88         .dtor = _nouveau_gpuobj_dtor,
  89         .init = _nouveau_gpuobj_init,
  90         .fini = _nouveau_gpuobj_fini,
  91         .rd32 = _nouveau_gpuobj_rd32,
  92         .wr32 = _nouveau_gpuobj_wr32,
  93 };
  94
  95 static struct nouveau_oclass
  96 nv50_graph_sclass[] = {
  97         { 0x0030, &nv50_graph_ofuncs },
  98         { 0x502d, &nv50_graph_ofuncs },
  99         { 0x5039, &nv50_graph_ofuncs },
 100         { 0x5097, &nv50_graph_ofuncs },
 101         { 0x50c0, &nv50_graph_ofuncs },
 102         {}
 103 };
 104
 105 static struct nouveau_oclass
 106 nv84_graph_sclass[] = {
 107         { 0x0030, &nv50_graph_ofuncs },
 108         { 0x502d, &nv50_graph_ofuncs },
 109         { 0x5039, &nv50_graph_ofuncs },
 110         { 0x50c0, &nv50_graph_ofuncs },
 111         { 0x8297, &nv50_graph_ofuncs },
 112         {}
 113 };
 114
 115 static struct nouveau_oclass
 116 nva0_graph_sclass[] = {
 117         { 0x0030, &nv50_graph_ofuncs },
 118         { 0x502d, &nv50_graph_ofuncs },
 119         { 0x5039, &nv50_graph_ofuncs },
 120         { 0x50c0, &nv50_graph_ofuncs },
 121         { 0x8397, &nv50_graph_ofuncs },
 122         {}
 123 };
 124
 125 static struct nouveau_oclass
 126 nva3_graph_sclass[] = {
 127         { 0x0030, &nv50_graph_ofuncs },
 128         { 0x502d, &nv50_graph_ofuncs },
 129         { 0x5039, &nv50_graph_ofuncs },
 130         { 0x50c0, &nv50_graph_ofuncs },
 131         { 0x8597, &nv50_graph_ofuncs },
 132         { 0x85c0, &nv50_graph_ofuncs },
 133         {}
 134 };
 135
 136 static struct nouveau_oclass
 137 nvaf_graph_sclass[] = {
 138         { 0x0030, &nv50_graph_ofuncs },
 139         { 0x502d, &nv50_graph_ofuncs },
 140         { 0x5039, &nv50_graph_ofuncs },
 141         { 0x50c0, &nv50_graph_ofuncs },
 142         { 0x85c0, &nv50_graph_ofuncs },
 143         { 0x8697, &nv50_graph_ofuncs },
 144         {}
 145 };
 146
 147 /*******************************************************************************
 148  * PGRAPH context
 149  ******************************************************************************/
 150
 151 static int
 152 nv50_graph_context_ctor(struct nouveau_object *parent,
 153                         struct nouveau_object *engine,
 154                         struct nouveau_oclass *oclass, void *data, u32 size,
 155                         struct nouveau_object **pobject)
 156 {
 157         struct nv50_graph_priv *priv = (void *)engine;
 158         struct nv50_graph_chan *chan;
 159         int ret;
 160
 161         ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
 162                                            priv->size, 0,
 163                                            NVOBJ_FLAG_ZERO_ALLOC, &chan);
 164         *pobject = nv_object(chan);
 165         if (ret)
 166                 return ret;
 167
 168         nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
 169         return 0;
 170 }
 171
 172 static struct nouveau_oclass
 173 nv50_graph_cclass = {
 174         .handle = NV_ENGCTX(GR, 0x50),
 175         .ofuncs = &(struct nouveau_ofuncs) {
 176                 .ctor = nv50_graph_context_ctor,
 177                 .dtor = _nouveau_graph_context_dtor,
 178                 .init = _nouveau_graph_context_init,
 179                 .fini = _nouveau_graph_context_fini,
 180                 .rd32 = _nouveau_graph_context_rd32,
 181                 .wr32 = _nouveau_graph_context_wr32,
 182         },
 183 };
 184
 185 /*******************************************************************************
 186  * PGRAPH engine/subdev functions
 187  ******************************************************************************/
 188
 189 static const struct nouveau_bitfield nv50_pgraph_status[] = {
 190         { 0x00000001, "BUSY" }, /* set when any bit is set */
 191         { 0x00000002, "DISPATCH" },
 192         { 0x00000004, "UNK2" },
 193         { 0x00000008, "UNK3" },
 194         { 0x00000010, "UNK4" },
 195         { 0x00000020, "UNK5" },
 196         { 0x00000040, "M2MF" },
 197         { 0x00000080, "UNK7" },
 198         { 0x00000100, "CTXPROG" },
 199         { 0x00000200, "VFETCH" },
 200         { 0x00000400, "CCACHE_PREGEOM" },
 201         { 0x00000800, "STRMOUT_VATTR_POSTGEOM" },
 202         { 0x00001000, "VCLIP" },
 203         { 0x00002000, "RATTR_APLANE" },
 204         { 0x00004000, "TRAST" },
 205         { 0x00008000, "CLIPID" },
 206         { 0x00010000, "ZCULL" },
 207         { 0x00020000, "ENG2D" },
 208         { 0x00040000, "RMASK" },
 209         { 0x00080000, "TPC_RAST" },
 210         { 0x00100000, "TPC_PROP" },
 211         { 0x00200000, "TPC_TEX" },
 212         { 0x00400000, "TPC_GEOM" },
 213         { 0x00800000, "TPC_MP" },
 214         { 0x01000000, "ROP" },
 215         {}
 216 };
 217
 218 static const char *const nv50_pgraph_vstatus_0[] = {
 219         "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP",
 220         NULL
 221 };
 222
 223 static const char *const nv50_pgraph_vstatus_1[] = {
 224         "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL
 225 };
 226
 227 static const char *const nv50_pgraph_vstatus_2[] = {
 228         "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK",
 229         "ROP", NULL
 230 };
 231
 232 static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
 233                 const char *const units[], u32 status)
 234 {
 235         int i;
 236
 237         nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
 238
 239         for (i = 0; units[i] && status; i++) {
 240                 if ((status & 7) == 1)
 241                         pr_cont(" %s", units[i]);
 242                 status >>= 3;
 243         }
 244         if (status)
 245                 pr_cont(" (invalid: 0x%x)", status);
 246         pr_cont("\n");
 247 }
 248
 249 static int
 250 nv84_graph_tlb_flush(struct nouveau_engine *engine)
 251 {
 252         struct nouveau_timer *ptimer = nouveau_timer(engine);
 253         struct nv50_graph_priv *priv = (void *)engine;
 254         bool idle, timeout = false;
 255         unsigned long flags;
 256         u64 start;
 257         u32 tmp;
 258
 259         spin_lock_irqsave(&priv->lock, flags);
 260         nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
 261
 262         start = ptimer->read(ptimer);
 263         do {
 264                 idle = true;
 265
 266                 for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
 267                         if ((tmp & 7) == 1)
 268                                 idle = false;
 269                 }
 270
 271                 for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
 272                         if ((tmp & 7) == 1)
 273                                 idle = false;
 274                 }
 275
 276                 for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
 277                         if ((tmp & 7) == 1)
 278                                 idle = false;
 279                 }
 280         } while (!idle &&
 281                  !(timeout = ptimer->read(ptimer) - start > 2000000000));
 282
 283         if (timeout) {
 284                 nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
 285
 286                 tmp = nv_rd32(priv, 0x400700);
 287                 nv_error(priv, "PGRAPH_STATUS  : 0x%08x", tmp);
 288                 nouveau_bitfield_print(nv50_pgraph_status, tmp);
 289                 pr_cont("\n");
 290
 291                 nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0,
 292                                 nv_rd32(priv, 0x400380));
 293                 nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1,
 294                                 nv_rd32(priv, 0x400384));
 295                 nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2,
 296                                 nv_rd32(priv, 0x400388));
 297         }
 298
 299
 300         nv_wr32(priv, 0x100c80, 0x00000001);
 301         if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
 302                 nv_error(priv, "vm flush timeout\n");
 303         nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
 304         spin_unlock_irqrestore(&priv->lock, flags);
 305         return timeout ? -EBUSY : 0;
 306 }
 307
 308 static const struct nouveau_bitfield nv50_mp_exec_errors[] = {
 309         { 0x01, "STACK_UNDERFLOW" },
 310         { 0x02, "STACK_MISMATCH" },
 311         { 0x04, "QUADON_ACTIVE" },
 312         { 0x08, "TIMEOUT" },
 313         { 0x10, "INVALID_OPCODE" },
 314         { 0x20, "PM_OVERFLOW" },
 315         { 0x40, "BREAKPOINT" },
 316         {}
 317 };
 318
 319 static const struct nouveau_bitfield nv50_mpc_traps[] = {
 320         { 0x0000001, "LOCAL_LIMIT_READ" },
 321         { 0x0000010, "LOCAL_LIMIT_WRITE" },
 322         { 0x0000040, "STACK_LIMIT" },
 323         { 0x0000100, "GLOBAL_LIMIT_READ" },
 324         { 0x0001000, "GLOBAL_LIMIT_WRITE" },
 325         { 0x0010000, "MP0" },
 326         { 0x0020000, "MP1" },
 327         { 0x0040000, "GLOBAL_LIMIT_RED" },
 328         { 0x0400000, "GLOBAL_LIMIT_ATOM" },
 329         { 0x4000000, "MP2" },
 330         {}
 331 };
 332
 333 static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
 334         { 0x00000001, "NOTIFY" },
 335         { 0x00000002, "IN" },
 336         { 0x00000004, "OUT" },
 337         {}
 338 };
 339
 340 static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
 341         { 0x00000001, "FAULT" },
 342         {}
 343 };
 344
 345 static const struct nouveau_bitfield nv50_graph_trap_strmout[] = {
 346         { 0x00000001, "FAULT" },
 347         {}
 348 };
 349
 350 static const struct nouveau_bitfield nv50_graph_trap_ccache[] = {
 351         { 0x00000001, "FAULT" },
 352         {}
 353 };
 354
 355 /* There must be a *lot* of these. Will take some time to gather them up. */
 356 const struct nouveau_enum nv50_data_error_names[] = {
 357         { 0x00000003, "INVALID_OPERATION", NULL },
 358         { 0x00000004, "INVALID_VALUE", NULL },
 359         { 0x00000005, "INVALID_ENUM", NULL },
 360         { 0x00000008, "INVALID_OBJECT", NULL },
 361         { 0x00000009, "READ_ONLY_OBJECT", NULL },
 362         { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
 363         { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
 364         { 0x0000000c, "INVALID_BITFIELD", NULL },
 365         { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
 366         { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
 367         { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
 368         { 0x00000010, "RT_DOUBLE_BIND", NULL },
 369         { 0x00000011, "RT_TYPES_MISMATCH", NULL },
 370         { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
 371         { 0x00000015, "FP_TOO_FEW_REGS", NULL },
 372         { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
 373         { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
 374         { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
 375         { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
 376         { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
 377         { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
 378         { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
 379         { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
 380         { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
 381         { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
 382         { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
 383         { 0x00000024, "VP_ZERO_INPUTS", NULL },
 384         { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
 385         { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
 386         { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
 387         { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
 388         { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
 389         { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
 390         { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
 391         { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
 392         { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
 393         { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
 394         { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
 395         { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
 396         { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
 397         { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
 398         { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
 399         {}
 400 };
 401
 402 static const struct nouveau_bitfield nv50_graph_intr_name[] = {
 403         { 0x00000001, "NOTIFY" },
 404         { 0x00000002, "COMPUTE_QUERY" },
 405         { 0x00000010, "ILLEGAL_MTHD" },
 406         { 0x00000020, "ILLEGAL_CLASS" },
 407         { 0x00000040, "DOUBLE_NOTIFY" },
 408         { 0x00001000, "CONTEXT_SWITCH" },
 409         { 0x00010000, "BUFFER_NOTIFY" },
 410         { 0x00100000, "DATA_ERROR" },
 411         { 0x00200000, "TRAP" },
 412         { 0x01000000, "SINGLE_STEP" },
 413         {}
 414 };
 415
 416 static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
 417         { 0x00000004, "SURF_WIDTH_OVERRUN" },
 418         { 0x00000008, "SURF_HEIGHT_OVERRUN" },
 419         { 0x00000010, "DST2D_FAULT" },
 420         { 0x00000020, "ZETA_FAULT" },
 421         { 0x00000040, "RT_FAULT" },
 422         { 0x00000080, "CUDA_FAULT" },
 423         { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
 424         { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
 425         { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
 426         { 0x00000800, "DST2D_LINEAR_MISMATCH" },
 427         { 0x00001000, "RT_LINEAR_MISMATCH" },
 428         {}
 429 };
 430
 431 static void
 432 nv50_priv_prop_trap(struct nv50_graph_priv *priv,
 433                     u32 ustatus_addr, u32 ustatus, u32 tp)
 434 {
 435         u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
 436         u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
 437         u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
 438         u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
 439         u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
 440         u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
 441         u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
 442
 443         /* CUDA memory: l[], g[] or stack. */
 444         if (ustatus & 0x00000080) {
 445                 if (e18 & 0x80000000) {
 446                         /* g[] read fault? */
 447                         nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
 448                                          tp, e14, e10 | ((e18 >> 24) & 0x1f));
 449                         e18 &= ~0x1f000000;
 450                 } else if (e18 & 0xc) {
 451                         /* g[] write fault? */
 452                         nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
 453                                  tp, e14, e10 | ((e18 >> 7) & 0x1f));
 454                         e18 &= ~0x00000f80;
 455                 } else {
 456                         nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
 457                                  tp, e14, e10);
 458                 }
 459                 ustatus &= ~0x00000080;
 460         }
 461         if (ustatus) {
 462                 nv_error(priv, "TRAP_PROP - TP %d -", tp);
 463                 nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
 464                 pr_cont(" - Address %02x%08x\n", e14, e10);
 465         }
 466         nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 467                  tp, e0c, e18, e1c, e20, e24);
 468 }
 469
 470 static void
 471 nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
 472 {
 473         u32 units = nv_rd32(priv, 0x1540);
 474         u32 addr, mp10, status, pc, oplow, ophigh;
 475         int i;
 476         int mps = 0;
 477         for (i = 0; i < 4; i++) {
 478                 if (!(units & 1 << (i+24)))
 479                         continue;
 480                 if (nv_device(priv)->chipset < 0xa0)
 481                         addr = 0x408200 + (tpid << 12) + (i << 7);
 482                 else
 483                         addr = 0x408100 + (tpid << 11) + (i << 7);
 484                 mp10 = nv_rd32(priv, addr + 0x10);
 485                 status = nv_rd32(priv, addr + 0x14);
 486                 if (!status)
 487                         continue;
 488                 if (display) {
 489                         nv_rd32(priv, addr + 0x20);
 490                         pc = nv_rd32(priv, addr + 0x24);
 491                         oplow = nv_rd32(priv, addr + 0x70);
 492                         ophigh = nv_rd32(priv, addr + 0x74);
 493                         nv_error(priv, "TRAP_MP_EXEC - "
 494                                         "TP %d MP %d:", tpid, i);
 495                         nouveau_bitfield_print(nv50_mp_exec_errors, status);
 496                         pr_cont(" at %06x warp %d, opcode %08x %08x\n",
 497                                         pc&0xffffff, pc >> 24,
 498                                         oplow, ophigh);
 499                 }
 500                 nv_wr32(priv, addr + 0x10, mp10);
 501                 nv_wr32(priv, addr + 0x14, 0);
 502                 mps++;
 503         }
 504         if (!mps && display)
 505                 nv_error(priv, "TRAP_MP_EXEC - TP %d: "
 506                                 "No MPs claiming errors?\n", tpid);
 507 }
 508
 509 static void
 510 nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
 511                 u32 ustatus_new, int display, const char *name)
 512 {
 513         int tps = 0;
 514         u32 units = nv_rd32(priv, 0x1540);
 515         int i, r;
 516         u32 ustatus_addr, ustatus;
 517         for (i = 0; i < 16; i++) {
 518                 if (!(units & (1 << i)))
 519                         continue;
 520                 if (nv_device(priv)->chipset < 0xa0)
 521                         ustatus_addr = ustatus_old + (i << 12);
 522                 else
 523                         ustatus_addr = ustatus_new + (i << 11);
 524                 ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff;
 525                 if (!ustatus)
 526                         continue;
 527                 tps++;
 528                 switch (type) {
 529                 case 6: /* texture error... unknown for now */
 530                         if (display) {
 531                                 nv_error(priv, "magic set %d:\n", i);
 532                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 533                                         nv_error(priv, "\t0x%08x: 0x%08x\n", r,
 534                                                 nv_rd32(priv, r));
 535                         }
 536                         break;
 537                 case 7: /* MP error */
 538                         if (ustatus & 0x04030000) {
 539                                 nv50_priv_mp_trap(priv, i, display);
 540                                 ustatus &= ~0x04030000;
 541                         }
 542                         if (ustatus && display) {
 543                                 nv_error(priv, "%s - TP%d:", name, i);
 544                                 nouveau_bitfield_print(nv50_mpc_traps, ustatus);
 545                                 pr_cont("\n");
 546                                 ustatus = 0;
 547                         }
 548                         break;
 549                 case 8: /* PROP error */
 550                         if (display)
 551                                 nv50_priv_prop_trap(
 552                                                 priv, ustatus_addr, ustatus, i);
 553                         ustatus = 0;
 554                         break;
 555                 }
 556                 if (ustatus) {
 557                         if (display)
 558                                 nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 559                 }
 560                 nv_wr32(priv, ustatus_addr, 0xc0000000);
 561         }
 562
 563         if (!tps && display)
 564                 nv_warn(priv, "%s - No TPs claiming errors?\n", name);
 565 }
 566
 567 static int
 568 nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
 569                         int chid, u64 inst, struct nouveau_object *engctx)
 570 {
 571         u32 status = nv_rd32(priv, 0x400108);
 572         u32 ustatus;
 573
 574         if (!status && display) {
 575                 nv_error(priv, "TRAP: no units reporting traps?\n");
 576                 return 1;
 577         }
 578
 579         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 580          * COND, QUERY. If you get a trap from it, the command is still stuck
 581          * in DISPATCH and you need to do something about it. */
 582         if (status & 0x001) {
 583                 ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff;
 584                 if (!ustatus && display) {
 585                         nv_error(priv, "TRAP_DISPATCH - no ustatus?\n");
 586                 }
 587
 588                 nv_wr32(priv, 0x400500, 0x00000000);
 589
 590                 /* Known to be triggered by screwed up NOTIFY and COND... */
 591                 if (ustatus & 0x00000001) {
 592                         u32 addr = nv_rd32(priv, 0x400808);
 593                         u32 subc = (addr & 0x00070000) >> 16;
 594                         u32 mthd = (addr & 0x00001ffc);
 595                         u32 datal = nv_rd32(priv, 0x40080c);
 596                         u32 datah = nv_rd32(priv, 0x400810);
 597                         u32 class = nv_rd32(priv, 0x400814);
 598                         u32 r848 = nv_rd32(priv, 0x400848);
 599
 600                         nv_error(priv, "TRAP DISPATCH_FAULT\n");
 601                         if (display && (addr & 0x80000000)) {
 602                                 nv_error(priv,
 603                                          "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
 604                                          chid, inst,
 605                                          nouveau_client_name(engctx), subc,
 606                                          class, mthd, datah, datal, addr, r848);
 607                         } else
 608                         if (display) {
 609                                 nv_error(priv, "no stuck command?\n");
 610                         }
 611
 612                         nv_wr32(priv, 0x400808, 0);
 613                         nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3);
 614                         nv_wr32(priv, 0x400848, 0);
 615                         ustatus &= ~0x00000001;
 616                 }
 617
 618                 if (ustatus & 0x00000002) {
 619                         u32 addr = nv_rd32(priv, 0x40084c);
 620                         u32 subc = (addr & 0x00070000) >> 16;
 621                         u32 mthd = (addr & 0x00001ffc);
 622                         u32 data = nv_rd32(priv, 0x40085c);
 623                         u32 class = nv_rd32(priv, 0x400814);
 624
 625                         nv_error(priv, "TRAP DISPATCH_QUERY\n");
 626                         if (display && (addr & 0x80000000)) {
 627                                 nv_error(priv,
 628                                          "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
 629                                          chid, inst,
 630                                          nouveau_client_name(engctx), subc,
 631                                          class, mthd, data, addr);
 632                         } else
 633                         if (display) {
 634                                 nv_error(priv, "no stuck command?\n");
 635                         }
 636
 637                         nv_wr32(priv, 0x40084c, 0);
 638                         ustatus &= ~0x00000002;
 639                 }
 640
 641                 if (ustatus && display) {
 642                         nv_error(priv, "TRAP_DISPATCH (unknown "
 643                                       "0x%08x)\n", ustatus);
 644                 }
 645
 646                 nv_wr32(priv, 0x400804, 0xc0000000);
 647                 nv_wr32(priv, 0x400108, 0x001);
 648                 status &= ~0x001;
 649                 if (!status)
 650                         return 0;
 651         }
 652
 653         /* M2MF: Memory to memory copy engine. */
 654         if (status & 0x002) {
 655                 u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
 656                 if (display) {
 657                         nv_error(priv, "TRAP_M2MF");
 658                         nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
 659                         pr_cont("\n");
 660                         nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
 661                                 nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
 662                                 nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
 663
 664                 }
 665
 666                 /* No sane way found yet -- just reset the bugger. */
 667                 nv_wr32(priv, 0x400040, 2);
 668                 nv_wr32(priv, 0x400040, 0);
 669                 nv_wr32(priv, 0x406800, 0xc0000000);
 670                 nv_wr32(priv, 0x400108, 0x002);
 671                 status &= ~0x002;
 672         }
 673
 674         /* VFETCH: Fetches data from vertex buffers. */
 675         if (status & 0x004) {
 676                 u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
 677                 if (display) {
 678                         nv_error(priv, "TRAP_VFETCH");
 679                         nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
 680                         pr_cont("\n");
 681                         nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
 682                                 nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
 683                                 nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
 684                 }
 685
 686                 nv_wr32(priv, 0x400c04, 0xc0000000);
 687                 nv_wr32(priv, 0x400108, 0x004);
 688                 status &= ~0x004;
 689         }
 690
 691         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 692         if (status & 0x008) {
 693                 ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
 694                 if (display) {
 695                         nv_error(priv, "TRAP_STRMOUT");
 696                         nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
 697                         pr_cont("\n");
 698                         nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
 699                                 nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
 700                                 nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
 701
 702                 }
 703
 704                 /* No sane way found yet -- just reset the bugger. */
 705                 nv_wr32(priv, 0x400040, 0x80);
 706                 nv_wr32(priv, 0x400040, 0);
 707                 nv_wr32(priv, 0x401800, 0xc0000000);
 708                 nv_wr32(priv, 0x400108, 0x008);
 709                 status &= ~0x008;
 710         }
 711
 712         /* CCACHE: Handles code and c[] caches and fills them. */
 713         if (status & 0x010) {
 714                 ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
 715                 if (display) {
 716                         nv_error(priv, "TRAP_CCACHE");
 717                         nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
 718                         pr_cont("\n");
 719                         nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
 720                                      " %08x %08x %08x\n",
 721                                 nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
 722                                 nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c),
 723                                 nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014),
 724                                 nv_rd32(priv, 0x40501c));
 725
 726                 }
 727
 728                 nv_wr32(priv, 0x405018, 0xc0000000);
 729                 nv_wr32(priv, 0x400108, 0x010);
 730                 status &= ~0x010;
 731         }
 732
 733         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 734          * remaining, so try to handle it anyway. Perhaps related to that
 735          * unknown DMA slot on tesla? */
 736         if (status & 0x20) {
 737                 ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff;
 738                 if (display)
 739                         nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus);
 740                 nv_wr32(priv, 0x402000, 0xc0000000);
 741                 /* no status modifiction on purpose */
 742         }
 743
 744         /* TEXTURE: CUDA texturing units */
 745         if (status & 0x040) {
 746                 nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display,
 747                                     "TRAP_TEXTURE");
 748                 nv_wr32(priv, 0x400108, 0x040);
 749                 status &= ~0x040;
 750         }
 751
 752         /* MP: CUDA execution engines. */
 753         if (status & 0x080) {
 754                 nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display,
 755                                     "TRAP_MP");
 756                 nv_wr32(priv, 0x400108, 0x080);
 757                 status &= ~0x080;
 758         }
 759
 760         /* PROP:  Handles TP-initiated uncached memory accesses:
 761          * l[], g[], stack, 2d surfaces, render targets. */
 762         if (status & 0x100) {
 763                 nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
 764                                     "TRAP_PROP");
 765                 nv_wr32(priv, 0x400108, 0x100);
 766                 status &= ~0x100;
 767         }
 768
 769         if (status) {
 770                 if (display)
 771                         nv_error(priv, "TRAP: unknown 0x%08x\n", status);
 772                 nv_wr32(priv, 0x400108, status);
 773         }
 774
 775         return 1;
 776 }
 777
 778 static void
 779 nv50_graph_intr(struct nouveau_subdev *subdev)
 780 {
 781         struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
 782         struct nouveau_engine *engine = nv_engine(subdev);
 783         struct nouveau_object *engctx;
 784         struct nouveau_handle *handle = NULL;
 785         struct nv50_graph_priv *priv = (void *)subdev;
 786         u32 stat = nv_rd32(priv, 0x400100);
 787         u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
 788         u32 addr = nv_rd32(priv, 0x400704);
 789         u32 subc = (addr & 0x00070000) >> 16;
 790         u32 mthd = (addr & 0x00001ffc);
 791         u32 data = nv_rd32(priv, 0x400708);
 792         u32 class = nv_rd32(priv, 0x400814);
 793         u32 show = stat, show_bitfield = stat;
 794         int chid;
 795
 796         engctx = nouveau_engctx_get(engine, inst);
 797         chid   = pfifo->chid(pfifo, engctx);
 798
 799         if (stat & 0x00000010) {
 800                 handle = nouveau_handle_get_class(engctx, class);
 801                 if (handle && !nv_call(handle->object, mthd, data))
 802                         show &= ~0x00000010;
 803                 nouveau_handle_put(handle);
 804         }
 805
 806         if (show & 0x00100000) {
 807                 u32 ecode = nv_rd32(priv, 0x400110);
 808                 nv_error(priv, "DATA_ERROR ");
 809                 nouveau_enum_print(nv50_data_error_names, ecode);
 810                 pr_cont("\n");
 811                 show_bitfield &= ~0x00100000;
 812         }
 813
 814         if (stat & 0x00200000) {
 815                 if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
 816                                 engctx))
 817                         show &= ~0x00200000;
 818                 show_bitfield &= ~0x00200000;
 819         }
 820
 821         nv_wr32(priv, 0x400100, stat);
 822         nv_wr32(priv, 0x400500, 0x00010001);
 823
 824         if (show) {
 825                 show &= show_bitfield;
 826                 if (show) {
 827                         nv_error(priv, "%s", "");
 828                         nouveau_bitfield_print(nv50_graph_intr_name, show);
 829                         pr_cont("\n");
 830                 }
 831                 nv_error(priv,
 832                          "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
 833                          chid, (u64)inst << 12, nouveau_client_name(engctx),
 834                          subc, class, mthd, data);
 835         }
 836
 837         if (nv_rd32(priv, 0x400824) & (1 << 31))
 838                 nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
 839
 840         nouveau_engctx_put(engctx);
 841 }
 842
 843 static int
 844 nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 845                struct nouveau_oclass *oclass, void *data, u32 size,
 846                struct nouveau_object **pobject)
 847 {
 848         struct nv50_graph_priv *priv;
 849         int ret;
 850
 851         ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
 852         *pobject = nv_object(priv);
 853         if (ret)
 854                 return ret;
 855
 856         nv_subdev(priv)->unit = 0x00201000;
 857         nv_subdev(priv)->intr = nv50_graph_intr;
 858         nv_engine(priv)->cclass = &nv50_graph_cclass;
 859
 860         priv->base.units = nv50_graph_units;
 861
 862         switch (nv_device(priv)->chipset) {
 863         case 0x50:
 864                 nv_engine(priv)->sclass = nv50_graph_sclass;
 865                 break;
 866         case 0x84:
 867         case 0x86:
 868         case 0x92:
 869         case 0x94:
 870         case 0x96:
 871         case 0x98:
 872                 nv_engine(priv)->sclass = nv84_graph_sclass;
 873                 break;
 874         case 0xa0:
 875         case 0xaa:
 876         case 0xac:
 877                 nv_engine(priv)->sclass = nva0_graph_sclass;
 878                 break;
 879         case 0xa3:
 880         case 0xa5:
 881         case 0xa8:
 882                 nv_engine(priv)->sclass = nva3_graph_sclass;
 883                 break;
 884         case 0xaf:
 885                 nv_engine(priv)->sclass = nvaf_graph_sclass;
 886                 break;
 887
 888         };
 889
 890         /* unfortunate hw bug workaround... */
 891         if (nv_device(priv)->chipset != 0x50 &&
 892             nv_device(priv)->chipset != 0xac)
 893                 nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
 894
 895         spin_lock_init(&priv->lock);
 896         return 0;
 897 }
 898
 899 static int
 900 nv50_graph_init(struct nouveau_object *object)
 901 {
 902         struct nv50_graph_priv *priv = (void *)object;
 903         int ret, units, i;
 904
 905         ret = nouveau_graph_init(&priv->base);
 906         if (ret)
 907                 return ret;
 908
 909         /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
 910         nv_wr32(priv, 0x40008c, 0x00000004);
 911
 912         /* reset/enable traps and interrupts */
 913         nv_wr32(priv, 0x400804, 0xc0000000);
 914         nv_wr32(priv, 0x406800, 0xc0000000);
 915         nv_wr32(priv, 0x400c04, 0xc0000000);
 916         nv_wr32(priv, 0x401800, 0xc0000000);
 917         nv_wr32(priv, 0x405018, 0xc0000000);
 918         nv_wr32(priv, 0x402000, 0xc0000000);
 919
 920         units = nv_rd32(priv, 0x001540);
 921         for (i = 0; i < 16; i++) {
 922                 if (!(units & (1 << i)))
 923                         continue;
 924
 925                 if (nv_device(priv)->chipset < 0xa0) {
 926                         nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000);
 927                         nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000);
 928                         nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000);
 929                 } else {
 930                         nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000);
 931                         nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000);
 932                         nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000);
 933                 }
 934         }
 935
 936         nv_wr32(priv, 0x400108, 0xffffffff);
 937         nv_wr32(priv, 0x400138, 0xffffffff);
 938         nv_wr32(priv, 0x400100, 0xffffffff);
 939         nv_wr32(priv, 0x40013c, 0xffffffff);
 940         nv_wr32(priv, 0x400500, 0x00010001);
 941
 942         /* upload context program, initialise ctxctl defaults */
 943         ret = nv50_grctx_init(nv_device(priv), &priv->size);
 944         if (ret)
 945                 return ret;
 946
 947         nv_wr32(priv, 0x400824, 0x00000000);
 948         nv_wr32(priv, 0x400828, 0x00000000);
 949         nv_wr32(priv, 0x40082c, 0x00000000);
 950         nv_wr32(priv, 0x400830, 0x00000000);
 951         nv_wr32(priv, 0x40032c, 0x00000000);
 952         nv_wr32(priv, 0x400330, 0x00000000);
 953
 954         /* some unknown zcull magic */
 955         switch (nv_device(priv)->chipset & 0xf0) {
 956         case 0x50:
 957         case 0x80:
 958         case 0x90:
 959                 nv_wr32(priv, 0x402ca8, 0x00000800);
 960                 break;
 961         case 0xa0:
 962         default:
 963                 nv_wr32(priv, 0x402cc0, 0x00000000);
 964                 if (nv_device(priv)->chipset == 0xa0 ||
 965                     nv_device(priv)->chipset == 0xaa ||
 966                     nv_device(priv)->chipset == 0xac) {
 967                         nv_wr32(priv, 0x402ca8, 0x00000802);
 968                 } else {
 969                         nv_wr32(priv, 0x402cc0, 0x00000000);
 970                         nv_wr32(priv, 0x402ca8, 0x00000002);
 971                 }
 972
 973                 break;
 974         }
 975
 976         /* zero out zcull regions */
 977         for (i = 0; i < 8; i++) {
 978                 nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000);
 979                 nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000);
 980                 nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000);
 981                 nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000);
 982         }
 983         return 0;
 984 }
 985
 986 struct nouveau_oclass
 987 nv50_graph_oclass = {
 988         .handle = NV_ENGINE(GR, 0x50),
 989         .ofuncs = &(struct nouveau_ofuncs) {
 990                 .ctor = nv50_graph_ctor,
 991                 .dtor = _nouveau_graph_dtor,
 992                 .init = nv50_graph_init,
 993                 .fini = _nouveau_graph_fini,
 994         },
 995 };