2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/dma-mapping.h>
31 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_plane_helper.h>
39 #include <drm/drm_scdc_helper.h>
40 #include <drm/drm_edid.h>
42 #include <nvif/class.h>
43 #include <nvif/cl0002.h>
44 #include <nvif/cl5070.h>
45 #include <nvif/cl507d.h>
46 #include <nvif/event.h>
48 #include "nouveau_drv.h"
49 #include "nouveau_dma.h"
50 #include "nouveau_gem.h"
51 #include "nouveau_connector.h"
52 #include "nouveau_encoder.h"
53 #include "nouveau_fence.h"
54 #include "nouveau_fbcon.h"
56 #include <subdev/bios/dp.h>
58 /******************************************************************************
60 *****************************************************************************/
62 struct nv50_outp_atom {
63 struct list_head head;
65 struct drm_encoder *encoder;
68 union nv50_outp_atom_mask {
76 /******************************************************************************
78 *****************************************************************************/
81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
82 const s32 *oclass, u8 head, void *data, u32 size,
83 struct nv50_chan *chan)
85 struct nvif_sclass *sclass;
88 chan->device = device;
90 ret = n = nvif_object_sclass_get(disp, &sclass);
95 for (i = 0; i < n; i++) {
96 if (sclass[i].oclass == oclass[0]) {
97 ret = nvif_object_init(disp, 0, oclass[0],
98 data, size, &chan->user);
100 nvif_object_map(&chan->user, NULL, 0);
101 nvif_object_sclass_put(&sclass);
108 nvif_object_sclass_put(&sclass);
113 nv50_chan_destroy(struct nv50_chan *chan)
115 nvif_object_fini(&chan->user);
118 /******************************************************************************
120 *****************************************************************************/
123 nv50_dmac_destroy(struct nv50_dmac *dmac)
125 nvif_object_fini(&dmac->vram);
126 nvif_object_fini(&dmac->sync);
128 nv50_chan_destroy(&dmac->base);
130 nvif_mem_fini(&dmac->push);
134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
135 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
136 struct nv50_dmac *dmac)
138 struct nouveau_cli *cli = (void *)device->object.client;
139 struct nv50_disp_core_channel_dma_v0 *args = data;
140 u8 type = NVIF_MEM_COHERENT;
143 mutex_init(&dmac->lock);
145 /* Pascal added support for 47-bit physical addresses, but some
146 * parts of EVO still only accept 40-bit PAs.
148 * To avoid issues on systems with large amounts of RAM, and on
149 * systems where an IOMMU maps pages at a high address, we need
150 * to allocate push buffers in VRAM instead.
152 * This appears to match NVIDIA's behaviour on Pascal.
154 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
155 type |= NVIF_MEM_VRAM;
157 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
161 dmac->ptr = dmac->push.object.map.ptr;
163 args->pushbuf = nvif_handle(&dmac->push.object);
165 ret = nv50_chan_create(device, disp, oclass, head, data, size,
173 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
174 &(struct nv_dma_v0) {
175 .target = NV_DMA_V0_TARGET_VRAM,
176 .access = NV_DMA_V0_ACCESS_RDWR,
177 .start = syncbuf + 0x0000,
178 .limit = syncbuf + 0x0fff,
179 }, sizeof(struct nv_dma_v0),
184 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
185 &(struct nv_dma_v0) {
186 .target = NV_DMA_V0_TARGET_VRAM,
187 .access = NV_DMA_V0_ACCESS_RDWR,
189 .limit = device->info.ram_user - 1,
190 }, sizeof(struct nv_dma_v0),
198 /******************************************************************************
199 * EVO channel helpers
200 *****************************************************************************/
202 evo_wait(struct nv50_dmac *evoc, int nr)
204 struct nv50_dmac *dmac = evoc;
205 struct nvif_device *device = dmac->base.device;
206 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
208 mutex_lock(&dmac->lock);
209 if (put + nr >= (PAGE_SIZE / 4) - 8) {
210 dmac->ptr[put] = 0x20000000;
212 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
213 if (nvif_msec(device, 2000,
214 if (!nvif_rd32(&dmac->base.user, 0x0004))
217 mutex_unlock(&dmac->lock);
218 pr_err("nouveau: evo channel stalled\n");
225 return dmac->ptr + put;
229 evo_kick(u32 *push, struct nv50_dmac *evoc)
231 struct nv50_dmac *dmac = evoc;
233 /* Push buffer fetches are not coherent with BAR1, we need to ensure
234 * writes have been flushed right through to VRAM before writing PUT.
236 if (dmac->push.type & NVIF_MEM_VRAM) {
237 struct nvif_device *device = dmac->base.device;
238 nvif_wr32(&device->object, 0x070000, 0x00000001);
239 nvif_msec(device, 2000,
240 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
245 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
246 mutex_unlock(&dmac->lock);
249 /******************************************************************************
250 * Output path helpers
251 *****************************************************************************/
253 nv50_outp_release(struct nouveau_encoder *nv_encoder)
255 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
257 struct nv50_disp_mthd_v1 base;
260 .base.method = NV50_DISP_MTHD_V1_RELEASE,
261 .base.hasht = nv_encoder->dcb->hasht,
262 .base.hashm = nv_encoder->dcb->hashm,
265 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
267 nv_encoder->link = 0;
271 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
273 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
274 struct nv50_disp *disp = nv50_disp(drm->dev);
276 struct nv50_disp_mthd_v1 base;
277 struct nv50_disp_acquire_v0 info;
280 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
281 .base.hasht = nv_encoder->dcb->hasht,
282 .base.hashm = nv_encoder->dcb->hashm,
286 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
288 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
292 nv_encoder->or = args.info.or;
293 nv_encoder->link = args.info.link;
298 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
299 struct drm_crtc_state *crtc_state,
300 struct drm_connector_state *conn_state,
301 struct drm_display_mode *native_mode)
303 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
304 struct drm_display_mode *mode = &crtc_state->mode;
305 struct drm_connector *connector = conn_state->connector;
306 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
307 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
309 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
310 asyc->scaler.full = false;
314 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
315 switch (connector->connector_type) {
316 case DRM_MODE_CONNECTOR_LVDS:
317 case DRM_MODE_CONNECTOR_eDP:
318 /* Force use of scaler for non-EDID modes. */
319 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
322 asyc->scaler.full = true;
331 if (!drm_mode_equal(adjusted_mode, mode)) {
332 drm_mode_copy(adjusted_mode, mode);
333 crtc_state->mode_changed = true;
340 nv50_outp_atomic_check(struct drm_encoder *encoder,
341 struct drm_crtc_state *crtc_state,
342 struct drm_connector_state *conn_state)
344 struct nouveau_connector *nv_connector =
345 nouveau_connector(conn_state->connector);
346 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
347 nv_connector->native_mode);
350 /******************************************************************************
352 *****************************************************************************/
354 nv50_dac_disable(struct drm_encoder *encoder)
356 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
357 struct nv50_core *core = nv50_disp(encoder->dev)->core;
358 if (nv_encoder->crtc)
359 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
360 nv_encoder->crtc = NULL;
361 nv50_outp_release(nv_encoder);
365 nv50_dac_enable(struct drm_encoder *encoder)
367 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
368 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
369 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
370 struct nv50_core *core = nv50_disp(encoder->dev)->core;
372 nv50_outp_acquire(nv_encoder);
374 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
377 nv_encoder->crtc = encoder->crtc;
380 static enum drm_connector_status
381 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
383 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
384 struct nv50_disp *disp = nv50_disp(encoder->dev);
386 struct nv50_disp_mthd_v1 base;
387 struct nv50_disp_dac_load_v0 load;
390 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
391 .base.hasht = nv_encoder->dcb->hasht,
392 .base.hashm = nv_encoder->dcb->hashm,
396 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
397 if (args.load.data == 0)
398 args.load.data = 340;
400 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
401 if (ret || !args.load.load)
402 return connector_status_disconnected;
404 return connector_status_connected;
407 static const struct drm_encoder_helper_funcs
409 .atomic_check = nv50_outp_atomic_check,
410 .enable = nv50_dac_enable,
411 .disable = nv50_dac_disable,
412 .detect = nv50_dac_detect
416 nv50_dac_destroy(struct drm_encoder *encoder)
418 drm_encoder_cleanup(encoder);
422 static const struct drm_encoder_funcs
424 .destroy = nv50_dac_destroy,
428 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
430 struct nouveau_drm *drm = nouveau_drm(connector->dev);
431 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
432 struct nvkm_i2c_bus *bus;
433 struct nouveau_encoder *nv_encoder;
434 struct drm_encoder *encoder;
435 int type = DRM_MODE_ENCODER_DAC;
437 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
440 nv_encoder->dcb = dcbe;
442 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
444 nv_encoder->i2c = &bus->i2c;
446 encoder = to_drm_encoder(nv_encoder);
447 encoder->possible_crtcs = dcbe->heads;
448 encoder->possible_clones = 0;
449 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
450 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
451 drm_encoder_helper_add(encoder, &nv50_dac_help);
453 drm_connector_attach_encoder(connector, encoder);
457 /******************************************************************************
459 *****************************************************************************/
461 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
463 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
464 struct nv50_disp *disp = nv50_disp(encoder->dev);
466 struct nv50_disp_mthd_v1 base;
467 struct nv50_disp_sor_hda_eld_v0 eld;
470 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
471 .base.hasht = nv_encoder->dcb->hasht,
472 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
473 (0x0100 << nv_crtc->index),
476 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
480 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
482 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
483 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
484 struct nouveau_connector *nv_connector;
485 struct nv50_disp *disp = nv50_disp(encoder->dev);
488 struct nv50_disp_mthd_v1 mthd;
489 struct nv50_disp_sor_hda_eld_v0 eld;
491 u8 data[sizeof(nv_connector->base.eld)];
493 .base.mthd.version = 1,
494 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
495 .base.mthd.hasht = nv_encoder->dcb->hasht,
496 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
497 (0x0100 << nv_crtc->index),
500 nv_connector = nouveau_encoder_connector_get(nv_encoder);
501 if (!drm_detect_monitor_audio(nv_connector->edid))
504 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
506 nvif_mthd(&disp->disp->object, 0, &args,
507 sizeof(args.base) + drm_eld_size(args.data));
510 /******************************************************************************
512 *****************************************************************************/
514 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
516 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
517 struct nv50_disp *disp = nv50_disp(encoder->dev);
519 struct nv50_disp_mthd_v1 base;
520 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
523 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
524 .base.hasht = nv_encoder->dcb->hasht,
525 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
526 (0x0100 << nv_crtc->index),
529 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
533 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
535 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
536 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
537 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
538 struct nv50_disp *disp = nv50_disp(encoder->dev);
540 struct nv50_disp_mthd_v1 base;
541 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
542 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
545 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
546 .base.hasht = nv_encoder->dcb->hasht,
547 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
548 (0x0100 << nv_crtc->index),
550 .pwr.rekey = 56, /* binary driver, and tegra, constant */
552 struct nouveau_connector *nv_connector;
553 struct drm_hdmi_info *hdmi;
555 union hdmi_infoframe avi_frame;
556 union hdmi_infoframe vendor_frame;
557 bool scdc_supported, high_tmds_clock_ratio = false, scrambling = false;
562 nv_connector = nouveau_encoder_connector_get(nv_encoder);
563 if (!drm_detect_hdmi_monitor(nv_connector->edid))
566 hdmi = &nv_connector->base.display_info.hdmi;
567 scdc_supported = hdmi->scdc.supported;
569 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
572 /* We have an AVI InfoFrame, populate it to the display */
573 args.pwr.avi_infoframe_length
574 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
577 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
578 &nv_connector->base, mode);
580 /* We have a Vendor InfoFrame, populate it to the display */
581 args.pwr.vendor_infoframe_length
582 = hdmi_infoframe_pack(&vendor_frame,
584 + args.pwr.avi_infoframe_length,
588 max_ac_packet = mode->htotal - mode->hdisplay;
589 max_ac_packet -= args.pwr.rekey;
590 max_ac_packet -= 18; /* constant from tegra */
591 args.pwr.max_ac_packet = max_ac_packet / 32;
593 if (hdmi->scdc.scrambling.supported) {
594 high_tmds_clock_ratio = mode->clock > 340000;
595 scrambling = high_tmds_clock_ratio ||
596 hdmi->scdc.scrambling.low_rates;
600 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
601 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
603 size = sizeof(args.base)
605 + args.pwr.avi_infoframe_length
606 + args.pwr.vendor_infoframe_length;
607 nvif_mthd(&disp->disp->object, 0, &args, size);
609 nv50_audio_enable(encoder, mode);
611 /* If SCDC is supported by the downstream monitor, update
612 * divider / scrambling settings to what we programmed above.
614 if (!hdmi->scdc.scrambling.supported)
617 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
619 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
622 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
623 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
624 config |= SCDC_SCRAMBLING_ENABLE * scrambling;
625 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
627 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
631 /******************************************************************************
633 *****************************************************************************/
634 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
635 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
636 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
639 struct nouveau_encoder *outp;
641 struct drm_dp_mst_topology_mgr mgr;
642 struct nv50_msto *msto[4];
650 struct nv50_mstm *mstm;
651 struct drm_dp_mst_port *port;
652 struct drm_connector connector;
654 struct drm_display_mode *native;
661 struct drm_encoder encoder;
663 struct nv50_head *head;
664 struct nv50_mstc *mstc;
668 static struct drm_dp_payload *
669 nv50_msto_payload(struct nv50_msto *msto)
671 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
672 struct nv50_mstc *mstc = msto->mstc;
673 struct nv50_mstm *mstm = mstc->mstm;
674 int vcpi = mstc->port->vcpi.vcpi, i;
676 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
677 for (i = 0; i < mstm->mgr.max_payloads; i++) {
678 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
679 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
680 mstm->outp->base.base.name, i, payload->vcpi,
681 payload->start_slot, payload->num_slots);
684 for (i = 0; i < mstm->mgr.max_payloads; i++) {
685 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
686 if (payload->vcpi == vcpi)
694 nv50_msto_cleanup(struct nv50_msto *msto)
696 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
697 struct nv50_mstc *mstc = msto->mstc;
698 struct nv50_mstm *mstm = mstc->mstm;
700 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
701 if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
702 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
703 if (msto->disabled) {
706 msto->disabled = false;
711 nv50_msto_prepare(struct nv50_msto *msto)
713 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
714 struct nv50_mstc *mstc = msto->mstc;
715 struct nv50_mstm *mstm = mstc->mstm;
717 struct nv50_disp_mthd_v1 base;
718 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
721 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
722 .base.hasht = mstm->outp->dcb->hasht,
723 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
724 (0x0100 << msto->head->base.index),
727 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
728 if (mstc->port && mstc->port->vcpi.vcpi > 0) {
729 struct drm_dp_payload *payload = nv50_msto_payload(msto);
731 args.vcpi.start_slot = payload->start_slot;
732 args.vcpi.num_slots = payload->num_slots;
733 args.vcpi.pbn = mstc->port->vcpi.pbn;
734 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
738 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
739 msto->encoder.name, msto->head->base.base.name,
740 args.vcpi.start_slot, args.vcpi.num_slots,
741 args.vcpi.pbn, args.vcpi.aligned_pbn);
742 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
746 nv50_msto_atomic_check(struct drm_encoder *encoder,
747 struct drm_crtc_state *crtc_state,
748 struct drm_connector_state *conn_state)
750 struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
751 struct nv50_mstm *mstm = mstc->mstm;
752 int bpp = conn_state->connector->display_info.bpc * 3;
755 mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
757 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
761 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
766 nv50_msto_enable(struct drm_encoder *encoder)
768 struct nv50_head *head = nv50_head(encoder->crtc);
769 struct nv50_msto *msto = nv50_msto(encoder);
770 struct nv50_mstc *mstc = NULL;
771 struct nv50_mstm *mstm = NULL;
772 struct drm_connector *connector;
773 struct drm_connector_list_iter conn_iter;
778 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
779 drm_for_each_connector_iter(connector, &conn_iter) {
780 if (connector->state->best_encoder == &msto->encoder) {
781 mstc = nv50_mstc(connector);
786 drm_connector_list_iter_end(&conn_iter);
791 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
792 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
796 nv50_outp_acquire(mstm->outp);
798 if (mstm->outp->link & 1)
803 switch (mstc->connector.display_info.bpc) {
804 case 6: depth = 0x2; break;
805 case 8: depth = 0x5; break;
807 default: depth = 0x6; break;
810 mstm->outp->update(mstm->outp, head->base.index,
811 nv50_head_atom(head->base.base.state), proto, depth);
815 mstm->modified = true;
819 nv50_msto_disable(struct drm_encoder *encoder)
821 struct nv50_msto *msto = nv50_msto(encoder);
822 struct nv50_mstc *mstc = msto->mstc;
823 struct nv50_mstm *mstm = mstc->mstm;
826 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
828 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
829 mstm->modified = true;
831 mstm->disabled = true;
832 msto->disabled = true;
835 static const struct drm_encoder_helper_funcs
837 .disable = nv50_msto_disable,
838 .enable = nv50_msto_enable,
839 .atomic_check = nv50_msto_atomic_check,
843 nv50_msto_destroy(struct drm_encoder *encoder)
845 struct nv50_msto *msto = nv50_msto(encoder);
846 drm_encoder_cleanup(&msto->encoder);
850 static const struct drm_encoder_funcs
852 .destroy = nv50_msto_destroy,
856 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
857 struct nv50_msto **pmsto)
859 struct nv50_msto *msto;
862 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
865 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
866 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
873 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
874 msto->encoder.possible_crtcs = heads;
878 static struct drm_encoder *
879 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
880 struct drm_connector_state *connector_state)
882 struct nv50_head *head = nv50_head(connector_state->crtc);
883 struct nv50_mstc *mstc = nv50_mstc(connector);
885 struct nv50_mstm *mstm = mstc->mstm;
886 return &mstm->msto[head->base.index]->encoder;
891 static struct drm_encoder *
892 nv50_mstc_best_encoder(struct drm_connector *connector)
894 struct nv50_mstc *mstc = nv50_mstc(connector);
896 struct nv50_mstm *mstm = mstc->mstm;
897 return &mstm->msto[0]->encoder;
902 static enum drm_mode_status
903 nv50_mstc_mode_valid(struct drm_connector *connector,
904 struct drm_display_mode *mode)
910 nv50_mstc_get_modes(struct drm_connector *connector)
912 struct nv50_mstc *mstc = nv50_mstc(connector);
915 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
916 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
918 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
920 if (!mstc->connector.display_info.bpc)
921 mstc->connector.display_info.bpc = 8;
924 drm_mode_destroy(mstc->connector.dev, mstc->native);
925 mstc->native = nouveau_conn_native_mode(&mstc->connector);
929 static const struct drm_connector_helper_funcs
931 .get_modes = nv50_mstc_get_modes,
932 .mode_valid = nv50_mstc_mode_valid,
933 .best_encoder = nv50_mstc_best_encoder,
934 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
937 static enum drm_connector_status
938 nv50_mstc_detect(struct drm_connector *connector, bool force)
940 struct nv50_mstc *mstc = nv50_mstc(connector);
942 return connector_status_disconnected;
943 return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
947 nv50_mstc_destroy(struct drm_connector *connector)
949 struct nv50_mstc *mstc = nv50_mstc(connector);
950 drm_connector_cleanup(&mstc->connector);
954 static const struct drm_connector_funcs
956 .reset = nouveau_conn_reset,
957 .detect = nv50_mstc_detect,
958 .fill_modes = drm_helper_probe_single_connector_modes,
959 .destroy = nv50_mstc_destroy,
960 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
961 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
962 .atomic_set_property = nouveau_conn_atomic_set_property,
963 .atomic_get_property = nouveau_conn_atomic_get_property,
967 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
968 const char *path, struct nv50_mstc **pmstc)
970 struct drm_device *dev = mstm->outp->base.base.dev;
971 struct nv50_mstc *mstc;
974 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
979 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
980 DRM_MODE_CONNECTOR_DisplayPort);
987 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
989 mstc->connector.funcs->reset(&mstc->connector);
990 nouveau_conn_attach_properties(&mstc->connector);
992 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
993 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
995 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
996 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
997 drm_connector_set_path_property(&mstc->connector, path);
1002 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1004 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1005 struct drm_encoder *encoder;
1008 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1009 ret = drm_dp_check_act_status(&mstm->mgr);
1011 ret = drm_dp_update_payload_part2(&mstm->mgr);
1013 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1014 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1015 struct nv50_msto *msto = nv50_msto(encoder);
1016 struct nv50_mstc *mstc = msto->mstc;
1017 if (mstc && mstc->mstm == mstm)
1018 nv50_msto_cleanup(msto);
1022 mstm->modified = false;
1026 nv50_mstm_prepare(struct nv50_mstm *mstm)
1028 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1029 struct drm_encoder *encoder;
1032 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1033 ret = drm_dp_update_payload_part1(&mstm->mgr);
1035 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1036 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1037 struct nv50_msto *msto = nv50_msto(encoder);
1038 struct nv50_mstc *mstc = msto->mstc;
1039 if (mstc && mstc->mstm == mstm)
1040 nv50_msto_prepare(msto);
1044 if (mstm->disabled) {
1046 nv50_outp_release(mstm->outp);
1047 mstm->disabled = false;
1052 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
1054 struct nv50_mstm *mstm = nv50_mstm(mgr);
1055 drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
1059 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1060 struct drm_connector *connector)
1062 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1063 struct nv50_mstc *mstc = nv50_mstc(connector);
1065 drm_connector_unregister(&mstc->connector);
1067 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1069 drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1071 drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1073 drm_connector_put(&mstc->connector);
1077 nv50_mstm_register_connector(struct drm_connector *connector)
1079 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1081 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1083 drm_connector_register(connector);
1086 static struct drm_connector *
1087 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1088 struct drm_dp_mst_port *port, const char *path)
1090 struct nv50_mstm *mstm = nv50_mstm(mgr);
1091 struct nv50_mstc *mstc;
1094 ret = nv50_mstc_new(mstm, port, path, &mstc);
1097 mstc->connector.funcs->destroy(&mstc->connector);
1101 return &mstc->connector;
1104 static const struct drm_dp_mst_topology_cbs
1106 .add_connector = nv50_mstm_add_connector,
1107 .register_connector = nv50_mstm_register_connector,
1108 .destroy_connector = nv50_mstm_destroy_connector,
1109 .hotplug = nv50_mstm_hotplug,
1113 nv50_mstm_service(struct nv50_mstm *mstm)
1115 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1116 bool handled = true;
1124 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1126 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1130 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1134 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1139 nv50_mstm_remove(struct nv50_mstm *mstm)
1142 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1146 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1148 struct nouveau_encoder *outp = mstm->outp;
1150 struct nv50_disp_mthd_v1 base;
1151 struct nv50_disp_sor_dp_mst_link_v0 mst;
1154 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1155 .base.hasht = outp->dcb->hasht,
1156 .base.hashm = outp->dcb->hashm,
1159 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1160 struct nvif_object *disp = &drm->display->disp.object;
1164 /* Even if we're enabling MST, start with disabling the
1165 * branching unit to clear any sink-side MST topology state
1166 * that wasn't set by us
1168 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1173 /* Now, start initializing */
1174 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1181 return nvif_mthd(disp, 0, &args, sizeof(args));
1185 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1187 struct drm_dp_aux *aux;
1189 bool old_state, new_state;
1195 mutex_lock(&mstm->mgr.lock);
1197 old_state = mstm->mgr.mst_state;
1198 new_state = old_state;
1199 aux = mstm->mgr.aux;
1202 /* Just check that the MST hub is still as we expect it */
1203 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1204 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1205 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1208 } else if (dpcd[0] >= 0x12) {
1209 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1213 if (!(dpcd[1] & DP_MST_CAP))
1219 if (new_state == old_state) {
1220 mutex_unlock(&mstm->mgr.lock);
1224 ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1228 mutex_unlock(&mstm->mgr.lock);
1230 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1232 return nv50_mstm_enable(mstm, dpcd[0], 0);
1237 mutex_unlock(&mstm->mgr.lock);
1242 nv50_mstm_fini(struct nv50_mstm *mstm)
1244 if (mstm && mstm->mgr.mst_state)
1245 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1249 nv50_mstm_init(struct nv50_mstm *mstm)
1251 if (mstm && mstm->mgr.mst_state)
1252 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1256 nv50_mstm_del(struct nv50_mstm **pmstm)
1258 struct nv50_mstm *mstm = *pmstm;
1266 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1267 int conn_base_id, struct nv50_mstm **pmstm)
1269 const int max_payloads = hweight8(outp->dcb->heads);
1270 struct drm_device *dev = outp->base.base.dev;
1271 struct nv50_mstm *mstm;
1275 /* This is a workaround for some monitors not functioning
1276 * correctly in MST mode on initial module load. I think
1277 * some bad interaction with the VBIOS may be responsible.
1279 * A good ol' off and on again seems to work here ;)
1281 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1282 if (ret >= 0 && dpcd >= 0x12)
1283 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1285 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1288 mstm->mgr.cbs = &nv50_mstm;
1290 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1291 max_payloads, conn_base_id);
1295 for (i = 0; i < max_payloads; i++) {
1296 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1305 /******************************************************************************
1307 *****************************************************************************/
1309 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1310 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1312 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1313 struct nv50_core *core = disp->core;
1316 nv_encoder->ctrl &= ~BIT(head);
1317 if (!(nv_encoder->ctrl & 0x0000000f))
1318 nv_encoder->ctrl = 0;
1320 nv_encoder->ctrl |= proto << 8;
1321 nv_encoder->ctrl |= BIT(head);
1322 asyh->or.depth = depth;
1325 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1329 nv50_sor_disable(struct drm_encoder *encoder)
1331 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1332 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1334 nv_encoder->crtc = NULL;
1337 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1341 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1343 pwr &= ~DP_SET_POWER_MASK;
1344 pwr |= DP_SET_POWER_D3;
1345 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1349 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1350 nv50_audio_disable(encoder, nv_crtc);
1351 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1352 nv50_outp_release(nv_encoder);
1357 nv50_sor_enable(struct drm_encoder *encoder)
1359 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1360 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1361 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1362 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1364 struct nv50_disp_mthd_v1 base;
1365 struct nv50_disp_sor_lvds_script_v0 lvds;
1368 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1369 .base.hasht = nv_encoder->dcb->hasht,
1370 .base.hashm = nv_encoder->dcb->hashm,
1372 struct nv50_disp *disp = nv50_disp(encoder->dev);
1373 struct drm_device *dev = encoder->dev;
1374 struct nouveau_drm *drm = nouveau_drm(dev);
1375 struct nouveau_connector *nv_connector;
1376 struct nvbios *bios = &drm->vbios;
1380 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1381 nv_encoder->crtc = encoder->crtc;
1382 nv50_outp_acquire(nv_encoder);
1384 switch (nv_encoder->dcb->type) {
1385 case DCB_OUTPUT_TMDS:
1386 if (nv_encoder->link & 1) {
1388 /* Only enable dual-link if:
1389 * - Need to (i.e. rate > 165MHz)
1391 * - Not an HDMI monitor, since there's no dual-link
1394 if (mode->clock >= 165000 &&
1395 nv_encoder->dcb->duallink_possible &&
1396 !drm_detect_hdmi_monitor(nv_connector->edid))
1402 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1404 case DCB_OUTPUT_LVDS:
1407 if (bios->fp_no_ddc) {
1408 if (bios->fp.dual_link)
1409 lvds.lvds.script |= 0x0100;
1410 if (bios->fp.if_is_24bit)
1411 lvds.lvds.script |= 0x0200;
1413 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1414 if (((u8 *)nv_connector->edid)[121] == 2)
1415 lvds.lvds.script |= 0x0100;
1417 if (mode->clock >= bios->fp.duallink_transition_clk) {
1418 lvds.lvds.script |= 0x0100;
1421 if (lvds.lvds.script & 0x0100) {
1422 if (bios->fp.strapless_is_24bit & 2)
1423 lvds.lvds.script |= 0x0200;
1425 if (bios->fp.strapless_is_24bit & 1)
1426 lvds.lvds.script |= 0x0200;
1429 if (nv_connector->base.display_info.bpc == 8)
1430 lvds.lvds.script |= 0x0200;
1433 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1436 if (nv_connector->base.display_info.bpc == 6)
1439 if (nv_connector->base.display_info.bpc == 8)
1444 if (nv_encoder->link & 1)
1449 nv50_audio_enable(encoder, mode);
1456 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1459 static const struct drm_encoder_helper_funcs
1461 .atomic_check = nv50_outp_atomic_check,
1462 .enable = nv50_sor_enable,
1463 .disable = nv50_sor_disable,
1467 nv50_sor_destroy(struct drm_encoder *encoder)
1469 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1470 nv50_mstm_del(&nv_encoder->dp.mstm);
1471 drm_encoder_cleanup(encoder);
1475 static const struct drm_encoder_funcs
1477 .destroy = nv50_sor_destroy,
1481 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1483 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1484 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1485 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1486 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1487 struct nouveau_encoder *nv_encoder;
1488 struct drm_encoder *encoder;
1489 u8 ver, hdr, cnt, len;
1493 switch (dcbe->type) {
1494 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1495 case DCB_OUTPUT_TMDS:
1498 type = DRM_MODE_ENCODER_TMDS;
1502 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1505 nv_encoder->dcb = dcbe;
1506 nv_encoder->update = nv50_sor_update;
1508 encoder = to_drm_encoder(nv_encoder);
1509 encoder->possible_crtcs = dcbe->heads;
1510 encoder->possible_clones = 0;
1511 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1512 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1513 drm_encoder_helper_add(encoder, &nv50_sor_help);
1515 drm_connector_attach_encoder(connector, encoder);
1517 if (dcbe->type == DCB_OUTPUT_DP) {
1518 struct nv50_disp *disp = nv50_disp(encoder->dev);
1519 struct nvkm_i2c_aux *aux =
1520 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1522 if (disp->disp->object.oclass < GF110_DISP) {
1523 /* HW has no support for address-only
1524 * transactions, so we're required to
1525 * use custom I2C-over-AUX code.
1527 nv_encoder->i2c = &aux->i2c;
1529 nv_encoder->i2c = &nv_connector->aux.ddc;
1531 nv_encoder->aux = aux;
1534 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1535 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1536 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1537 nv_connector->base.base.id,
1538 &nv_encoder->dp.mstm);
1543 struct nvkm_i2c_bus *bus =
1544 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1546 nv_encoder->i2c = &bus->i2c;
1552 /******************************************************************************
1554 *****************************************************************************/
1556 nv50_pior_atomic_check(struct drm_encoder *encoder,
1557 struct drm_crtc_state *crtc_state,
1558 struct drm_connector_state *conn_state)
1560 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1563 crtc_state->adjusted_mode.clock *= 2;
1568 nv50_pior_disable(struct drm_encoder *encoder)
1570 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1571 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1572 if (nv_encoder->crtc)
1573 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1574 nv_encoder->crtc = NULL;
1575 nv50_outp_release(nv_encoder);
1579 nv50_pior_enable(struct drm_encoder *encoder)
1581 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1582 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1583 struct nouveau_connector *nv_connector;
1584 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1585 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1586 u8 owner = 1 << nv_crtc->index;
1589 nv50_outp_acquire(nv_encoder);
1591 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1592 switch (nv_connector->base.display_info.bpc) {
1593 case 10: asyh->or.depth = 0x6; break;
1594 case 8: asyh->or.depth = 0x5; break;
1595 case 6: asyh->or.depth = 0x2; break;
1596 default: asyh->or.depth = 0x0; break;
1599 switch (nv_encoder->dcb->type) {
1600 case DCB_OUTPUT_TMDS:
1609 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1610 nv_encoder->crtc = encoder->crtc;
1613 static const struct drm_encoder_helper_funcs
1615 .atomic_check = nv50_pior_atomic_check,
1616 .enable = nv50_pior_enable,
1617 .disable = nv50_pior_disable,
1621 nv50_pior_destroy(struct drm_encoder *encoder)
1623 drm_encoder_cleanup(encoder);
1627 static const struct drm_encoder_funcs
1629 .destroy = nv50_pior_destroy,
1633 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1635 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1636 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1637 struct nvkm_i2c_bus *bus = NULL;
1638 struct nvkm_i2c_aux *aux = NULL;
1639 struct i2c_adapter *ddc;
1640 struct nouveau_encoder *nv_encoder;
1641 struct drm_encoder *encoder;
1644 switch (dcbe->type) {
1645 case DCB_OUTPUT_TMDS:
1646 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1647 ddc = bus ? &bus->i2c : NULL;
1648 type = DRM_MODE_ENCODER_TMDS;
1651 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1652 ddc = aux ? &aux->i2c : NULL;
1653 type = DRM_MODE_ENCODER_TMDS;
1659 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1662 nv_encoder->dcb = dcbe;
1663 nv_encoder->i2c = ddc;
1664 nv_encoder->aux = aux;
1666 encoder = to_drm_encoder(nv_encoder);
1667 encoder->possible_crtcs = dcbe->heads;
1668 encoder->possible_clones = 0;
1669 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1670 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1671 drm_encoder_helper_add(encoder, &nv50_pior_help);
1673 drm_connector_attach_encoder(connector, encoder);
1677 /******************************************************************************
1679 *****************************************************************************/
1682 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1684 struct nouveau_drm *drm = nouveau_drm(state->dev);
1685 struct nv50_disp *disp = nv50_disp(drm->dev);
1686 struct nv50_core *core = disp->core;
1687 struct nv50_mstm *mstm;
1688 struct drm_encoder *encoder;
1690 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1692 drm_for_each_encoder(encoder, drm->dev) {
1693 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1694 mstm = nouveau_encoder(encoder)->dp.mstm;
1695 if (mstm && mstm->modified)
1696 nv50_mstm_prepare(mstm);
1700 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1701 core->func->update(core, interlock, true);
1702 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1703 disp->core->chan.base.device))
1704 NV_ERROR(drm, "core notifier timeout\n");
1706 drm_for_each_encoder(encoder, drm->dev) {
1707 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1708 mstm = nouveau_encoder(encoder)->dp.mstm;
1709 if (mstm && mstm->modified)
1710 nv50_mstm_cleanup(mstm);
1716 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1718 struct drm_plane_state *new_plane_state;
1719 struct drm_plane *plane;
1722 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1723 struct nv50_wndw *wndw = nv50_wndw(plane);
1724 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1725 if (wndw->func->update)
1726 wndw->func->update(wndw, interlock);
1732 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1734 struct drm_device *dev = state->dev;
1735 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1736 struct drm_crtc *crtc;
1737 struct drm_plane_state *new_plane_state;
1738 struct drm_plane *plane;
1739 struct nouveau_drm *drm = nouveau_drm(dev);
1740 struct nv50_disp *disp = nv50_disp(dev);
1741 struct nv50_atom *atom = nv50_atom(state);
1742 struct nv50_outp_atom *outp, *outt;
1743 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1746 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1747 drm_atomic_helper_wait_for_fences(dev, state, false);
1748 drm_atomic_helper_wait_for_dependencies(state);
1749 drm_atomic_helper_update_legacy_modeset_state(dev, state);
1751 if (atom->lock_core)
1752 mutex_lock(&disp->mutex);
1754 /* Disable head(s). */
1755 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1756 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1757 struct nv50_head *head = nv50_head(crtc);
1759 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1760 asyh->clr.mask, asyh->set.mask);
1761 if (old_crtc_state->active && !new_crtc_state->active)
1762 drm_crtc_vblank_off(crtc);
1764 if (asyh->clr.mask) {
1765 nv50_head_flush_clr(head, asyh, atom->flush_disable);
1766 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1770 /* Disable plane(s). */
1771 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1772 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1773 struct nv50_wndw *wndw = nv50_wndw(plane);
1775 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1776 asyw->clr.mask, asyw->set.mask);
1777 if (!asyw->clr.mask)
1780 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1783 /* Disable output path(s). */
1784 list_for_each_entry(outp, &atom->outp, head) {
1785 const struct drm_encoder_helper_funcs *help;
1786 struct drm_encoder *encoder;
1788 encoder = outp->encoder;
1789 help = encoder->helper_private;
1791 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1792 outp->clr.mask, outp->set.mask);
1794 if (outp->clr.mask) {
1795 help->disable(encoder);
1796 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1797 if (outp->flush_disable) {
1798 nv50_disp_atomic_commit_wndw(state, interlock);
1799 nv50_disp_atomic_commit_core(state, interlock);
1800 memset(interlock, 0x00, sizeof(interlock));
1805 /* Flush disable. */
1806 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1807 if (atom->flush_disable) {
1808 nv50_disp_atomic_commit_wndw(state, interlock);
1809 nv50_disp_atomic_commit_core(state, interlock);
1810 memset(interlock, 0x00, sizeof(interlock));
1814 /* Update output path(s). */
1815 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1816 const struct drm_encoder_helper_funcs *help;
1817 struct drm_encoder *encoder;
1819 encoder = outp->encoder;
1820 help = encoder->helper_private;
1822 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1823 outp->set.mask, outp->clr.mask);
1825 if (outp->set.mask) {
1826 help->enable(encoder);
1827 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1830 list_del(&outp->head);
1834 /* Update head(s). */
1835 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1836 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1837 struct nv50_head *head = nv50_head(crtc);
1839 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1840 asyh->set.mask, asyh->clr.mask);
1842 if (asyh->set.mask) {
1843 nv50_head_flush_set(head, asyh);
1844 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1847 if (new_crtc_state->active) {
1848 if (!old_crtc_state->active)
1849 drm_crtc_vblank_on(crtc);
1850 if (new_crtc_state->event)
1851 drm_crtc_vblank_get(crtc);
1855 /* Update plane(s). */
1856 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1857 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1858 struct nv50_wndw *wndw = nv50_wndw(plane);
1860 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1861 asyw->set.mask, asyw->clr.mask);
1862 if ( !asyw->set.mask &&
1863 (!asyw->clr.mask || atom->flush_disable))
1866 nv50_wndw_flush_set(wndw, interlock, asyw);
1870 nv50_disp_atomic_commit_wndw(state, interlock);
1872 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1873 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1874 interlock[NV50_DISP_INTERLOCK_OVLY] ||
1875 interlock[NV50_DISP_INTERLOCK_WNDW] ||
1876 !atom->state.legacy_cursor_update)
1877 nv50_disp_atomic_commit_core(state, interlock);
1879 disp->core->func->update(disp->core, interlock, false);
1882 if (atom->lock_core)
1883 mutex_unlock(&disp->mutex);
1885 /* Wait for HW to signal completion. */
1886 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1887 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1888 struct nv50_wndw *wndw = nv50_wndw(plane);
1889 int ret = nv50_wndw_wait_armed(wndw, asyw);
1891 NV_ERROR(drm, "%s: timeout\n", plane->name);
1894 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1895 if (new_crtc_state->event) {
1896 unsigned long flags;
1897 /* Get correct count/ts if racing with vblank irq */
1898 if (new_crtc_state->active)
1899 drm_crtc_accurate_vblank_count(crtc);
1900 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1901 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1902 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1904 new_crtc_state->event = NULL;
1905 if (new_crtc_state->active)
1906 drm_crtc_vblank_put(crtc);
1910 drm_atomic_helper_commit_hw_done(state);
1911 drm_atomic_helper_cleanup_planes(dev, state);
1912 drm_atomic_helper_commit_cleanup_done(state);
1913 drm_atomic_state_put(state);
1917 nv50_disp_atomic_commit_work(struct work_struct *work)
1919 struct drm_atomic_state *state =
1920 container_of(work, typeof(*state), commit_work);
1921 nv50_disp_atomic_commit_tail(state);
1925 nv50_disp_atomic_commit(struct drm_device *dev,
1926 struct drm_atomic_state *state, bool nonblock)
1928 struct nouveau_drm *drm = nouveau_drm(dev);
1929 struct drm_plane_state *new_plane_state;
1930 struct drm_plane *plane;
1931 struct drm_crtc *crtc;
1932 bool active = false;
1935 ret = pm_runtime_get_sync(dev->dev);
1936 if (ret < 0 && ret != -EACCES)
1939 ret = drm_atomic_helper_setup_commit(state, nonblock);
1943 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
1945 ret = drm_atomic_helper_prepare_planes(dev, state);
1950 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
1955 ret = drm_atomic_helper_swap_state(state, true);
1959 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1960 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1961 struct nv50_wndw *wndw = nv50_wndw(plane);
1963 if (asyw->set.image)
1964 nv50_wndw_ntfy_enable(wndw, asyw);
1967 drm_atomic_state_get(state);
1970 queue_work(system_unbound_wq, &state->commit_work);
1972 nv50_disp_atomic_commit_tail(state);
1974 drm_for_each_crtc(crtc, dev) {
1975 if (crtc->state->active) {
1976 if (!drm->have_disp_power_ref) {
1977 drm->have_disp_power_ref = true;
1985 if (!active && drm->have_disp_power_ref) {
1986 pm_runtime_put_autosuspend(dev->dev);
1987 drm->have_disp_power_ref = false;
1992 drm_atomic_helper_cleanup_planes(dev, state);
1994 pm_runtime_put_autosuspend(dev->dev);
1998 static struct nv50_outp_atom *
1999 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2001 struct nv50_outp_atom *outp;
2003 list_for_each_entry(outp, &atom->outp, head) {
2004 if (outp->encoder == encoder)
2008 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2010 return ERR_PTR(-ENOMEM);
2012 list_add(&outp->head, &atom->outp);
2013 outp->encoder = encoder;
2018 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2019 struct drm_connector_state *old_connector_state)
2021 struct drm_encoder *encoder = old_connector_state->best_encoder;
2022 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2023 struct drm_crtc *crtc;
2024 struct nv50_outp_atom *outp;
2026 if (!(crtc = old_connector_state->crtc))
2029 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2030 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2031 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2032 outp = nv50_disp_outp_atomic_add(atom, encoder);
2034 return PTR_ERR(outp);
2036 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2037 outp->flush_disable = true;
2038 atom->flush_disable = true;
2040 outp->clr.ctrl = true;
2041 atom->lock_core = true;
2048 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2049 struct drm_connector_state *connector_state)
2051 struct drm_encoder *encoder = connector_state->best_encoder;
2052 struct drm_crtc_state *new_crtc_state;
2053 struct drm_crtc *crtc;
2054 struct nv50_outp_atom *outp;
2056 if (!(crtc = connector_state->crtc))
2059 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2060 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2061 outp = nv50_disp_outp_atomic_add(atom, encoder);
2063 return PTR_ERR(outp);
2065 outp->set.ctrl = true;
2066 atom->lock_core = true;
2073 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2075 struct nv50_atom *atom = nv50_atom(state);
2076 struct drm_connector_state *old_connector_state, *new_connector_state;
2077 struct drm_connector *connector;
2078 struct drm_crtc_state *new_crtc_state;
2079 struct drm_crtc *crtc;
2082 /* We need to handle colour management on a per-plane basis. */
2083 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2084 if (new_crtc_state->color_mgmt_changed) {
2085 ret = drm_atomic_add_affected_planes(state, crtc);
2091 ret = drm_atomic_helper_check(dev, state);
2095 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2096 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2100 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2109 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2111 struct nv50_atom *atom = nv50_atom(state);
2112 struct nv50_outp_atom *outp, *outt;
2114 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2115 list_del(&outp->head);
2119 drm_atomic_state_default_clear(state);
2123 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2125 struct nv50_atom *atom = nv50_atom(state);
2126 drm_atomic_state_default_release(&atom->state);
2130 static struct drm_atomic_state *
2131 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2133 struct nv50_atom *atom;
2134 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2135 drm_atomic_state_init(dev, &atom->state) < 0) {
2139 INIT_LIST_HEAD(&atom->outp);
2140 return &atom->state;
2143 static const struct drm_mode_config_funcs
2145 .fb_create = nouveau_user_framebuffer_create,
2146 .output_poll_changed = nouveau_fbcon_output_poll_changed,
2147 .atomic_check = nv50_disp_atomic_check,
2148 .atomic_commit = nv50_disp_atomic_commit,
2149 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2150 .atomic_state_clear = nv50_disp_atomic_state_clear,
2151 .atomic_state_free = nv50_disp_atomic_state_free,
2154 /******************************************************************************
2156 *****************************************************************************/
2159 nv50_display_fini(struct drm_device *dev)
2161 struct nouveau_encoder *nv_encoder;
2162 struct drm_encoder *encoder;
2163 struct drm_plane *plane;
2165 drm_for_each_plane(plane, dev) {
2166 struct nv50_wndw *wndw = nv50_wndw(plane);
2167 if (plane->funcs != &nv50_wndw)
2169 nv50_wndw_fini(wndw);
2172 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2173 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2174 nv_encoder = nouveau_encoder(encoder);
2175 nv50_mstm_fini(nv_encoder->dp.mstm);
2181 nv50_display_init(struct drm_device *dev)
2183 struct nv50_core *core = nv50_disp(dev)->core;
2184 struct drm_encoder *encoder;
2185 struct drm_plane *plane;
2187 core->func->init(core);
2189 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2190 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2191 struct nouveau_encoder *nv_encoder =
2192 nouveau_encoder(encoder);
2193 nv50_mstm_init(nv_encoder->dp.mstm);
2197 drm_for_each_plane(plane, dev) {
2198 struct nv50_wndw *wndw = nv50_wndw(plane);
2199 if (plane->funcs != &nv50_wndw)
2201 nv50_wndw_init(wndw);
2208 nv50_display_destroy(struct drm_device *dev)
2210 struct nv50_disp *disp = nv50_disp(dev);
2212 nv50_core_del(&disp->core);
2214 nouveau_bo_unmap(disp->sync);
2216 nouveau_bo_unpin(disp->sync);
2217 nouveau_bo_ref(NULL, &disp->sync);
2219 nouveau_display(dev)->priv = NULL;
2224 nv50_display_create(struct drm_device *dev)
2226 struct nvif_device *device = &nouveau_drm(dev)->client.device;
2227 struct nouveau_drm *drm = nouveau_drm(dev);
2228 struct dcb_table *dcb = &drm->vbios.dcb;
2229 struct drm_connector *connector, *tmp;
2230 struct nv50_disp *disp;
2231 struct dcb_output *dcbe;
2234 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2238 mutex_init(&disp->mutex);
2240 nouveau_display(dev)->priv = disp;
2241 nouveau_display(dev)->dtor = nv50_display_destroy;
2242 nouveau_display(dev)->init = nv50_display_init;
2243 nouveau_display(dev)->fini = nv50_display_fini;
2244 disp->disp = &nouveau_display(dev)->disp;
2245 dev->mode_config.funcs = &nv50_disp_func;
2246 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2248 /* small shared memory area we use for notifiers and semaphores */
2249 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2250 0, 0x0000, NULL, NULL, &disp->sync);
2252 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2254 ret = nouveau_bo_map(disp->sync);
2256 nouveau_bo_unpin(disp->sync);
2259 nouveau_bo_ref(NULL, &disp->sync);
2265 /* allocate master evo channel */
2266 ret = nv50_core_new(drm, &disp->core);
2270 /* create crtc objects to represent the hw heads */
2271 if (disp->disp->object.oclass >= GV100_DISP)
2272 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2274 if (disp->disp->object.oclass >= GF110_DISP)
2275 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2279 for (i = 0; i < fls(crtcs); i++) {
2280 if (!(crtcs & (1 << i)))
2282 ret = nv50_head_create(dev, i);
2287 /* create encoder/connector objects based on VBIOS DCB table */
2288 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2289 connector = nouveau_connector_create(dev, dcbe->connector);
2290 if (IS_ERR(connector))
2293 if (dcbe->location == DCB_LOC_ON_CHIP) {
2294 switch (dcbe->type) {
2295 case DCB_OUTPUT_TMDS:
2296 case DCB_OUTPUT_LVDS:
2298 ret = nv50_sor_create(connector, dcbe);
2300 case DCB_OUTPUT_ANALOG:
2301 ret = nv50_dac_create(connector, dcbe);
2308 ret = nv50_pior_create(connector, dcbe);
2312 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2313 dcbe->location, dcbe->type,
2314 ffs(dcbe->or) - 1, ret);
2319 /* cull any connectors we created that don't have an encoder */
2320 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2321 if (connector->encoder_ids[0])
2324 NV_WARN(drm, "%s has no encoders, removing\n",
2326 connector->funcs->destroy(connector);
2329 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2330 dev->vblank_disable_immediate = true;
2334 nv50_display_destroy(dev);