drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_dp_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_fb_helper.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <drm/drm_vblank.h>
  41
  42 #include <nvif/class.h>
  43 #include <nvif/cl0002.h>
  44 #include <nvif/cl5070.h>
  45 #include <nvif/cl507d.h>
  46 #include <nvif/event.h>
  47
  48 #include "nouveau_drv.h"
  49 #include "nouveau_dma.h"
  50 #include "nouveau_gem.h"
  51 #include "nouveau_connector.h"
  52 #include "nouveau_encoder.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55
  56 #include <subdev/bios/dp.h>
  57
  58 /******************************************************************************
  59  * Atomic state
  60  *****************************************************************************/
  61
  62 struct nv50_outp_atom {
  63         struct list_head head;
  64
  65         struct drm_encoder *encoder;
  66         bool flush_disable;
  67
  68         union nv50_outp_atom_mask {
  69                 struct {
  70                         bool ctrl:1;
  71                 };
  72                 u8 mask;
  73         } set, clr;
  74 };
  75
  76 /******************************************************************************
  77  * EVO channel
  78  *****************************************************************************/
  79
  80 static int
  81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  82                  const s32 *oclass, u8 head, void *data, u32 size,
  83                  struct nv50_chan *chan)
  84 {
  85         struct nvif_sclass *sclass;
  86         int ret, i, n;
  87
  88         chan->device = device;
  89
  90         ret = n = nvif_object_sclass_get(disp, &sclass);
  91         if (ret < 0)
  92                 return ret;
  93
  94         while (oclass[0]) {
  95                 for (i = 0; i < n; i++) {
  96                         if (sclass[i].oclass == oclass[0]) {
  97                                 ret = nvif_object_init(disp, 0, oclass[0],
  98                                                        data, size, &chan->user);
  99                                 if (ret == 0)
 100                                         nvif_object_map(&chan->user, NULL, 0);
 101                                 nvif_object_sclass_put(&sclass);
 102                                 return ret;
 103                         }
 104                 }
 105                 oclass++;
 106         }
 107
 108         nvif_object_sclass_put(&sclass);
 109         return -ENOSYS;
 110 }
 111
 112 static void
 113 nv50_chan_destroy(struct nv50_chan *chan)
 114 {
 115         nvif_object_fini(&chan->user);
 116 }
 117
 118 /******************************************************************************
 119  * DMA EVO channel
 120  *****************************************************************************/
 121
 122 void
 123 nv50_dmac_destroy(struct nv50_dmac *dmac)
 124 {
 125         nvif_object_fini(&dmac->vram);
 126         nvif_object_fini(&dmac->sync);
 127
 128         nv50_chan_destroy(&dmac->base);
 129
 130         nvif_mem_fini(&dmac->push);
 131 }
 132
 133 int
 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 135                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 136                  struct nv50_dmac *dmac)
 137 {
 138         struct nouveau_cli *cli = (void *)device->object.client;
 139         struct nv50_disp_core_channel_dma_v0 *args = data;
 140         u8 type = NVIF_MEM_COHERENT;
 141         int ret;
 142
 143         mutex_init(&dmac->lock);
 144
 145         /* Pascal added support for 47-bit physical addresses, but some
 146          * parts of EVO still only accept 40-bit PAs.
 147          *
 148          * To avoid issues on systems with large amounts of RAM, and on
 149          * systems where an IOMMU maps pages at a high address, we need
 150          * to allocate push buffers in VRAM instead.
 151          *
 152          * This appears to match NVIDIA's behaviour on Pascal.
 153          */
 154         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 155                 type |= NVIF_MEM_VRAM;
 156
 157         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 158         if (ret)
 159                 return ret;
 160
 161         dmac->ptr = dmac->push.object.map.ptr;
 162
 163         args->pushbuf = nvif_handle(&dmac->push.object);
 164
 165         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 166                                &dmac->base);
 167         if (ret)
 168                 return ret;
 169
 170         if (!syncbuf)
 171                 return 0;
 172
 173         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 174                                &(struct nv_dma_v0) {
 175                                         .target = NV_DMA_V0_TARGET_VRAM,
 176                                         .access = NV_DMA_V0_ACCESS_RDWR,
 177                                         .start = syncbuf + 0x0000,
 178                                         .limit = syncbuf + 0x0fff,
 179                                }, sizeof(struct nv_dma_v0),
 180                                &dmac->sync);
 181         if (ret)
 182                 return ret;
 183
 184         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 185                                &(struct nv_dma_v0) {
 186                                         .target = NV_DMA_V0_TARGET_VRAM,
 187                                         .access = NV_DMA_V0_ACCESS_RDWR,
 188                                         .start = 0,
 189                                         .limit = device->info.ram_user - 1,
 190                                }, sizeof(struct nv_dma_v0),
 191                                &dmac->vram);
 192         if (ret)
 193                 return ret;
 194
 195         return ret;
 196 }
 197
 198 /******************************************************************************
 199  * EVO channel helpers
 200  *****************************************************************************/
 201 static void
 202 evo_flush(struct nv50_dmac *dmac)
 203 {
 204         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 205          * writes have been flushed right through to VRAM before writing PUT.
 206          */
 207         if (dmac->push.type & NVIF_MEM_VRAM) {
 208                 struct nvif_device *device = dmac->base.device;
 209                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 210                 nvif_msec(device, 2000,
 211                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 212                                 break;
 213                 );
 214         }
 215 }
 216
 217 u32 *
 218 evo_wait(struct nv50_dmac *evoc, int nr)
 219 {
 220         struct nv50_dmac *dmac = evoc;
 221         struct nvif_device *device = dmac->base.device;
 222         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 223
 224         mutex_lock(&dmac->lock);
 225         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 226                 dmac->ptr[put] = 0x20000000;
 227                 evo_flush(dmac);
 228
 229                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 230                 if (nvif_msec(device, 2000,
 231                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 232                                 break;
 233                 ) < 0) {
 234                         mutex_unlock(&dmac->lock);
 235                         pr_err("nouveau: evo channel stalled\n");
 236                         return NULL;
 237                 }
 238
 239                 put = 0;
 240         }
 241
 242         return dmac->ptr + put;
 243 }
 244
 245 void
 246 evo_kick(u32 *push, struct nv50_dmac *evoc)
 247 {
 248         struct nv50_dmac *dmac = evoc;
 249
 250         evo_flush(dmac);
 251
 252         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 253         mutex_unlock(&dmac->lock);
 254 }
 255
 256 /******************************************************************************
 257  * Output path helpers
 258  *****************************************************************************/
 259 static void
 260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 261 {
 262         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 263         struct {
 264                 struct nv50_disp_mthd_v1 base;
 265         } args = {
 266                 .base.version = 1,
 267                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 268                 .base.hasht  = nv_encoder->dcb->hasht,
 269                 .base.hashm  = nv_encoder->dcb->hashm,
 270         };
 271
 272         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 273         nv_encoder->or = -1;
 274         nv_encoder->link = 0;
 275 }
 276
 277 static int
 278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 279 {
 280         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 281         struct nv50_disp *disp = nv50_disp(drm->dev);
 282         struct {
 283                 struct nv50_disp_mthd_v1 base;
 284                 struct nv50_disp_acquire_v0 info;
 285         } args = {
 286                 .base.version = 1,
 287                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 288                 .base.hasht  = nv_encoder->dcb->hasht,
 289                 .base.hashm  = nv_encoder->dcb->hashm,
 290         };
 291         int ret;
 292
 293         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 294         if (ret) {
 295                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 296                 return ret;
 297         }
 298
 299         nv_encoder->or = args.info.or;
 300         nv_encoder->link = args.info.link;
 301         return 0;
 302 }
 303
 304 static int
 305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 306                             struct drm_crtc_state *crtc_state,
 307                             struct drm_connector_state *conn_state,
 308                             struct drm_display_mode *native_mode)
 309 {
 310         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 311         struct drm_display_mode *mode = &crtc_state->mode;
 312         struct drm_connector *connector = conn_state->connector;
 313         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 314         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 315
 316         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 317         asyc->scaler.full = false;
 318         if (!native_mode)
 319                 return 0;
 320
 321         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 322                 switch (connector->connector_type) {
 323                 case DRM_MODE_CONNECTOR_LVDS:
 324                 case DRM_MODE_CONNECTOR_eDP:
 325                         /* Don't force scaler for EDID modes with
 326                          * same size as the native one (e.g. different
 327                          * refresh rate)
 328                          */
 329                         if (mode->hdisplay == native_mode->hdisplay &&
 330                             mode->vdisplay == native_mode->vdisplay &&
 331                             mode->type & DRM_MODE_TYPE_DRIVER)
 332                                 break;
 333                         mode = native_mode;
 334                         asyc->scaler.full = true;
 335                         break;
 336                 default:
 337                         break;
 338                 }
 339         } else {
 340                 mode = native_mode;
 341         }
 342
 343         if (!drm_mode_equal(adjusted_mode, mode)) {
 344                 drm_mode_copy(adjusted_mode, mode);
 345                 crtc_state->mode_changed = true;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int
 352 nv50_outp_atomic_check(struct drm_encoder *encoder,
 353                        struct drm_crtc_state *crtc_state,
 354                        struct drm_connector_state *conn_state)
 355 {
 356         struct drm_connector *connector = conn_state->connector;
 357         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 358         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 359         int ret;
 360
 361         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 362                                           nv_connector->native_mode);
 363         if (ret)
 364                 return ret;
 365
 366         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 367                 asyh->or.bpc = connector->display_info.bpc;
 368
 369         return 0;
 370 }
 371
 372 /******************************************************************************
 373  * DAC
 374  *****************************************************************************/
 375 static void
 376 nv50_dac_disable(struct drm_encoder *encoder)
 377 {
 378         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 379         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 380         if (nv_encoder->crtc)
 381                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 382         nv_encoder->crtc = NULL;
 383         nv50_outp_release(nv_encoder);
 384 }
 385
 386 static void
 387 nv50_dac_enable(struct drm_encoder *encoder)
 388 {
 389         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 390         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 391         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 392         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 393
 394         nv50_outp_acquire(nv_encoder);
 395
 396         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 397         asyh->or.depth = 0;
 398
 399         nv_encoder->crtc = encoder->crtc;
 400 }
 401
 402 static enum drm_connector_status
 403 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 404 {
 405         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 406         struct nv50_disp *disp = nv50_disp(encoder->dev);
 407         struct {
 408                 struct nv50_disp_mthd_v1 base;
 409                 struct nv50_disp_dac_load_v0 load;
 410         } args = {
 411                 .base.version = 1,
 412                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 413                 .base.hasht  = nv_encoder->dcb->hasht,
 414                 .base.hashm  = nv_encoder->dcb->hashm,
 415         };
 416         int ret;
 417
 418         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 419         if (args.load.data == 0)
 420                 args.load.data = 340;
 421
 422         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 423         if (ret || !args.load.load)
 424                 return connector_status_disconnected;
 425
 426         return connector_status_connected;
 427 }
 428
 429 static const struct drm_encoder_helper_funcs
 430 nv50_dac_help = {
 431         .atomic_check = nv50_outp_atomic_check,
 432         .enable = nv50_dac_enable,
 433         .disable = nv50_dac_disable,
 434         .detect = nv50_dac_detect
 435 };
 436
 437 static void
 438 nv50_dac_destroy(struct drm_encoder *encoder)
 439 {
 440         drm_encoder_cleanup(encoder);
 441         kfree(encoder);
 442 }
 443
 444 static const struct drm_encoder_funcs
 445 nv50_dac_func = {
 446         .destroy = nv50_dac_destroy,
 447 };
 448
 449 static int
 450 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 451 {
 452         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 453         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 454         struct nvkm_i2c_bus *bus;
 455         struct nouveau_encoder *nv_encoder;
 456         struct drm_encoder *encoder;
 457         int type = DRM_MODE_ENCODER_DAC;
 458
 459         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 460         if (!nv_encoder)
 461                 return -ENOMEM;
 462         nv_encoder->dcb = dcbe;
 463
 464         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 465         if (bus)
 466                 nv_encoder->i2c = &bus->i2c;
 467
 468         encoder = to_drm_encoder(nv_encoder);
 469         encoder->possible_crtcs = dcbe->heads;
 470         encoder->possible_clones = 0;
 471         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 472                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 473         drm_encoder_helper_add(encoder, &nv50_dac_help);
 474
 475         drm_connector_attach_encoder(connector, encoder);
 476         return 0;
 477 }
 478
 479 /******************************************************************************
 480  * Audio
 481  *****************************************************************************/
 482 static void
 483 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 484 {
 485         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 486         struct nv50_disp *disp = nv50_disp(encoder->dev);
 487         struct {
 488                 struct nv50_disp_mthd_v1 base;
 489                 struct nv50_disp_sor_hda_eld_v0 eld;
 490         } args = {
 491                 .base.version = 1,
 492                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 493                 .base.hasht   = nv_encoder->dcb->hasht,
 494                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 495                                 (0x0100 << nv_crtc->index),
 496         };
 497
 498         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 499 }
 500
 501 static void
 502 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 503 {
 504         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 505         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 506         struct nouveau_connector *nv_connector;
 507         struct nv50_disp *disp = nv50_disp(encoder->dev);
 508         struct __packed {
 509                 struct {
 510                         struct nv50_disp_mthd_v1 mthd;
 511                         struct nv50_disp_sor_hda_eld_v0 eld;
 512                 } base;
 513                 u8 data[sizeof(nv_connector->base.eld)];
 514         } args = {
 515                 .base.mthd.version = 1,
 516                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 517                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 518                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 519                                      (0x0100 << nv_crtc->index),
 520         };
 521
 522         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 523         if (!drm_detect_monitor_audio(nv_connector->edid))
 524                 return;
 525
 526         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 527
 528         nvif_mthd(&disp->disp->object, 0, &args,
 529                   sizeof(args.base) + drm_eld_size(args.data));
 530 }
 531
 532 /******************************************************************************
 533  * HDMI
 534  *****************************************************************************/
 535 static void
 536 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 537 {
 538         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 539         struct nv50_disp *disp = nv50_disp(encoder->dev);
 540         struct {
 541                 struct nv50_disp_mthd_v1 base;
 542                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 543         } args = {
 544                 .base.version = 1,
 545                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 546                 .base.hasht  = nv_encoder->dcb->hasht,
 547                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 548                                (0x0100 << nv_crtc->index),
 549         };
 550
 551         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 552 }
 553
 554 static void
 555 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 556 {
 557         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 558         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 559         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 560         struct nv50_disp *disp = nv50_disp(encoder->dev);
 561         struct {
 562                 struct nv50_disp_mthd_v1 base;
 563                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 564                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 565         } args = {
 566                 .base.version = 1,
 567                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 568                 .base.hasht  = nv_encoder->dcb->hasht,
 569                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 570                                (0x0100 << nv_crtc->index),
 571                 .pwr.state = 1,
 572                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 573         };
 574         struct nouveau_connector *nv_connector;
 575         struct drm_hdmi_info *hdmi;
 576         u32 max_ac_packet;
 577         union hdmi_infoframe avi_frame;
 578         union hdmi_infoframe vendor_frame;
 579         bool high_tmds_clock_ratio = false, scrambling = false;
 580         u8 config;
 581         int ret;
 582         int size;
 583
 584         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 585         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 586                 return;
 587
 588         hdmi = &nv_connector->base.display_info.hdmi;
 589
 590         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 591                                                        &nv_connector->base, mode);
 592         if (!ret) {
 593                 /* We have an AVI InfoFrame, populate it to the display */
 594                 args.pwr.avi_infoframe_length
 595                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 596         }
 597
 598         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 599                                                           &nv_connector->base, mode);
 600         if (!ret) {
 601                 /* We have a Vendor InfoFrame, populate it to the display */
 602                 args.pwr.vendor_infoframe_length
 603                         = hdmi_infoframe_pack(&vendor_frame,
 604                                               args.infoframes
 605                                               + args.pwr.avi_infoframe_length,
 606                                               17);
 607         }
 608
 609         max_ac_packet  = mode->htotal - mode->hdisplay;
 610         max_ac_packet -= args.pwr.rekey;
 611         max_ac_packet -= 18; /* constant from tegra */
 612         args.pwr.max_ac_packet = max_ac_packet / 32;
 613
 614         if (hdmi->scdc.scrambling.supported) {
 615                 high_tmds_clock_ratio = mode->clock > 340000;
 616                 scrambling = high_tmds_clock_ratio ||
 617                         hdmi->scdc.scrambling.low_rates;
 618         }
 619
 620         args.pwr.scdc =
 621                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 622                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 623
 624         size = sizeof(args.base)
 625                 + sizeof(args.pwr)
 626                 + args.pwr.avi_infoframe_length
 627                 + args.pwr.vendor_infoframe_length;
 628         nvif_mthd(&disp->disp->object, 0, &args, size);
 629
 630         nv50_audio_enable(encoder, mode);
 631
 632         /* If SCDC is supported by the downstream monitor, update
 633          * divider / scrambling settings to what we programmed above.
 634          */
 635         if (!hdmi->scdc.scrambling.supported)
 636                 return;
 637
 638         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 639         if (ret < 0) {
 640                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 641                 return;
 642         }
 643         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 644         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 645         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 646         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 647         if (ret < 0)
 648                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 649                          config, ret);
 650 }
 651
 652 /******************************************************************************
 653  * MST
 654  *****************************************************************************/
 655 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 656 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 657 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 658
 659 struct nv50_mstm {
 660         struct nouveau_encoder *outp;
 661
 662         struct drm_dp_mst_topology_mgr mgr;
 663         struct nv50_msto *msto[4];
 664
 665         bool modified;
 666         bool disabled;
 667         int links;
 668 };
 669
 670 struct nv50_mstc {
 671         struct nv50_mstm *mstm;
 672         struct drm_dp_mst_port *port;
 673         struct drm_connector connector;
 674
 675         struct drm_display_mode *native;
 676         struct edid *edid;
 677 };
 678
 679 struct nv50_msto {
 680         struct drm_encoder encoder;
 681
 682         struct nv50_head *head;
 683         struct nv50_mstc *mstc;
 684         bool disabled;
 685 };
 686
 687 static struct drm_dp_payload *
 688 nv50_msto_payload(struct nv50_msto *msto)
 689 {
 690         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 691         struct nv50_mstc *mstc = msto->mstc;
 692         struct nv50_mstm *mstm = mstc->mstm;
 693         int vcpi = mstc->port->vcpi.vcpi, i;
 694
 695         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 696
 697         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 698         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 699                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 700                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 701                           mstm->outp->base.base.name, i, payload->vcpi,
 702                           payload->start_slot, payload->num_slots);
 703         }
 704
 705         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 706                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 707                 if (payload->vcpi == vcpi)
 708                         return payload;
 709         }
 710
 711         return NULL;
 712 }
 713
 714 static void
 715 nv50_msto_cleanup(struct nv50_msto *msto)
 716 {
 717         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 718         struct nv50_mstc *mstc = msto->mstc;
 719         struct nv50_mstm *mstm = mstc->mstm;
 720
 721         if (!msto->disabled)
 722                 return;
 723
 724         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 725
 726         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 727
 728         msto->mstc = NULL;
 729         msto->head = NULL;
 730         msto->disabled = false;
 731 }
 732
 733 static void
 734 nv50_msto_prepare(struct nv50_msto *msto)
 735 {
 736         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 737         struct nv50_mstc *mstc = msto->mstc;
 738         struct nv50_mstm *mstm = mstc->mstm;
 739         struct {
 740                 struct nv50_disp_mthd_v1 base;
 741                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 742         } args = {
 743                 .base.version = 1,
 744                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 745                 .base.hasht  = mstm->outp->dcb->hasht,
 746                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 747                                (0x0100 << msto->head->base.index),
 748         };
 749
 750         mutex_lock(&mstm->mgr.payload_lock);
 751
 752         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 753         if (mstc->port->vcpi.vcpi > 0) {
 754                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 755                 if (payload) {
 756                         args.vcpi.start_slot = payload->start_slot;
 757                         args.vcpi.num_slots = payload->num_slots;
 758                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 759                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 760                 }
 761         }
 762
 763         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 764                   msto->encoder.name, msto->head->base.base.name,
 765                   args.vcpi.start_slot, args.vcpi.num_slots,
 766                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 767
 768         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 769         mutex_unlock(&mstm->mgr.payload_lock);
 770 }
 771
 772 static int
 773 nv50_msto_atomic_check(struct drm_encoder *encoder,
 774                        struct drm_crtc_state *crtc_state,
 775                        struct drm_connector_state *conn_state)
 776 {
 777         struct drm_atomic_state *state = crtc_state->state;
 778         struct drm_connector *connector = conn_state->connector;
 779         struct nv50_mstc *mstc = nv50_mstc(connector);
 780         struct nv50_mstm *mstm = mstc->mstm;
 781         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 782         int slots;
 783         int ret;
 784
 785         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 786                                           mstc->native);
 787         if (ret)
 788                 return ret;
 789
 790         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
 791                 return 0;
 792
 793         /*
 794          * When restoring duplicated states, we need to make sure that the bw
 795          * remains the same and avoid recalculating it, as the connector's bpc
 796          * may have changed after the state was duplicated
 797          */
 798         if (!state->duplicated) {
 799                 const int clock = crtc_state->adjusted_mode.clock;
 800
 801                 /*
 802                  * XXX: Since we don't use HDR in userspace quite yet, limit
 803                  * the bpc to 8 to save bandwidth on the topology. In the
 804                  * future, we'll want to properly fix this by dynamically
 805                  * selecting the highest possible bpc that would fit in the
 806                  * topology
 807                  */
 808                 asyh->or.bpc = min(connector->display_info.bpc, 8U);
 809                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, false);
 810         }
 811
 812         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
 813                                               asyh->dp.pbn, 0);
 814         if (slots < 0)
 815                 return slots;
 816
 817         asyh->dp.tu = slots;
 818
 819         return 0;
 820 }
 821
 822 static u8
 823 nv50_dp_bpc_to_depth(unsigned int bpc)
 824 {
 825         switch (bpc) {
 826         case  6: return 0x2;
 827         case  8: return 0x5;
 828         case 10: /* fall-through */
 829         default: return 0x6;
 830         }
 831 }
 832
 833 static void
 834 nv50_msto_enable(struct drm_encoder *encoder)
 835 {
 836         struct nv50_head *head = nv50_head(encoder->crtc);
 837         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
 838         struct nv50_msto *msto = nv50_msto(encoder);
 839         struct nv50_mstc *mstc = NULL;
 840         struct nv50_mstm *mstm = NULL;
 841         struct drm_connector *connector;
 842         struct drm_connector_list_iter conn_iter;
 843         u8 proto;
 844         bool r;
 845
 846         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 847         drm_for_each_connector_iter(connector, &conn_iter) {
 848                 if (connector->state->best_encoder == &msto->encoder) {
 849                         mstc = nv50_mstc(connector);
 850                         mstm = mstc->mstm;
 851                         break;
 852                 }
 853         }
 854         drm_connector_list_iter_end(&conn_iter);
 855
 856         if (WARN_ON(!mstc))
 857                 return;
 858
 859         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
 860                                      armh->dp.tu);
 861         if (!r)
 862                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
 863
 864         if (!mstm->links++)
 865                 nv50_outp_acquire(mstm->outp);
 866
 867         if (mstm->outp->link & 1)
 868                 proto = 0x8;
 869         else
 870                 proto = 0x9;
 871
 872         mstm->outp->update(mstm->outp, head->base.index, armh, proto,
 873                            nv50_dp_bpc_to_depth(armh->or.bpc));
 874
 875         msto->head = head;
 876         msto->mstc = mstc;
 877         mstm->modified = true;
 878 }
 879
 880 static void
 881 nv50_msto_disable(struct drm_encoder *encoder)
 882 {
 883         struct nv50_msto *msto = nv50_msto(encoder);
 884         struct nv50_mstc *mstc = msto->mstc;
 885         struct nv50_mstm *mstm = mstc->mstm;
 886
 887         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 888
 889         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 890         mstm->modified = true;
 891         if (!--mstm->links)
 892                 mstm->disabled = true;
 893         msto->disabled = true;
 894 }
 895
 896 static const struct drm_encoder_helper_funcs
 897 nv50_msto_help = {
 898         .disable = nv50_msto_disable,
 899         .enable = nv50_msto_enable,
 900         .atomic_check = nv50_msto_atomic_check,
 901 };
 902
 903 static void
 904 nv50_msto_destroy(struct drm_encoder *encoder)
 905 {
 906         struct nv50_msto *msto = nv50_msto(encoder);
 907         drm_encoder_cleanup(&msto->encoder);
 908         kfree(msto);
 909 }
 910
 911 static const struct drm_encoder_funcs
 912 nv50_msto = {
 913         .destroy = nv50_msto_destroy,
 914 };
 915
 916 static int
 917 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 918               struct nv50_msto **pmsto)
 919 {
 920         struct nv50_msto *msto;
 921         int ret;
 922
 923         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 924                 return -ENOMEM;
 925
 926         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 927                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 928         if (ret) {
 929                 kfree(*pmsto);
 930                 *pmsto = NULL;
 931                 return ret;
 932         }
 933
 934         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 935         msto->encoder.possible_crtcs = heads;
 936         return 0;
 937 }
 938
 939 static struct drm_encoder *
 940 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 941                               struct drm_connector_state *connector_state)
 942 {
 943         struct nv50_head *head = nv50_head(connector_state->crtc);
 944         struct nv50_mstc *mstc = nv50_mstc(connector);
 945
 946         return &mstc->mstm->msto[head->base.index]->encoder;
 947 }
 948
 949 static enum drm_mode_status
 950 nv50_mstc_mode_valid(struct drm_connector *connector,
 951                      struct drm_display_mode *mode)
 952 {
 953         return MODE_OK;
 954 }
 955
 956 static int
 957 nv50_mstc_get_modes(struct drm_connector *connector)
 958 {
 959         struct nv50_mstc *mstc = nv50_mstc(connector);
 960         int ret = 0;
 961
 962         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 963         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 964         if (mstc->edid)
 965                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 966
 967         if (!mstc->connector.display_info.bpc)
 968                 mstc->connector.display_info.bpc = 8;
 969
 970         if (mstc->native)
 971                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 972         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 973         return ret;
 974 }
 975
 976 static int
 977 nv50_mstc_atomic_check(struct drm_connector *connector,
 978                        struct drm_atomic_state *state)
 979 {
 980         struct nv50_mstc *mstc = nv50_mstc(connector);
 981         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
 982         struct drm_connector_state *new_conn_state =
 983                 drm_atomic_get_new_connector_state(state, connector);
 984         struct drm_connector_state *old_conn_state =
 985                 drm_atomic_get_old_connector_state(state, connector);
 986         struct drm_crtc_state *crtc_state;
 987         struct drm_crtc *new_crtc = new_conn_state->crtc;
 988
 989         if (!old_conn_state->crtc)
 990                 return 0;
 991
 992         /* We only want to free VCPI if this state disables the CRTC on this
 993          * connector
 994          */
 995         if (new_crtc) {
 996                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
 997
 998                 if (!crtc_state ||
 999                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1000                     crtc_state->enable)
1001                         return 0;
1002         }
1003
1004         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1005 }
1006
1007 static int
1008 nv50_mstc_detect(struct drm_connector *connector,
1009                  struct drm_modeset_acquire_ctx *ctx, bool force)
1010 {
1011         struct nv50_mstc *mstc = nv50_mstc(connector);
1012         int ret;
1013
1014         if (drm_connector_is_unregistered(connector))
1015                 return connector_status_disconnected;
1016
1017         ret = pm_runtime_get_sync(connector->dev->dev);
1018         if (ret < 0 && ret != -EACCES)
1019                 return connector_status_disconnected;
1020
1021         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1022                                      mstc->port);
1023
1024         pm_runtime_mark_last_busy(connector->dev->dev);
1025         pm_runtime_put_autosuspend(connector->dev->dev);
1026         return ret;
1027 }
1028
1029 static const struct drm_connector_helper_funcs
1030 nv50_mstc_help = {
1031         .get_modes = nv50_mstc_get_modes,
1032         .mode_valid = nv50_mstc_mode_valid,
1033         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1034         .atomic_check = nv50_mstc_atomic_check,
1035         .detect_ctx = nv50_mstc_detect,
1036 };
1037
1038 static void
1039 nv50_mstc_destroy(struct drm_connector *connector)
1040 {
1041         struct nv50_mstc *mstc = nv50_mstc(connector);
1042
1043         drm_connector_cleanup(&mstc->connector);
1044         drm_dp_mst_put_port_malloc(mstc->port);
1045
1046         kfree(mstc);
1047 }
1048
1049 static const struct drm_connector_funcs
1050 nv50_mstc = {
1051         .reset = nouveau_conn_reset,
1052         .fill_modes = drm_helper_probe_single_connector_modes,
1053         .destroy = nv50_mstc_destroy,
1054         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1055         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1056         .atomic_set_property = nouveau_conn_atomic_set_property,
1057         .atomic_get_property = nouveau_conn_atomic_get_property,
1058 };
1059
1060 static int
1061 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1062               const char *path, struct nv50_mstc **pmstc)
1063 {
1064         struct drm_device *dev = mstm->outp->base.base.dev;
1065         struct nv50_mstc *mstc;
1066         int ret, i;
1067
1068         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1069                 return -ENOMEM;
1070         mstc->mstm = mstm;
1071         mstc->port = port;
1072
1073         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1074                                  DRM_MODE_CONNECTOR_DisplayPort);
1075         if (ret) {
1076                 kfree(*pmstc);
1077                 *pmstc = NULL;
1078                 return ret;
1079         }
1080
1081         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1082
1083         mstc->connector.funcs->reset(&mstc->connector);
1084         nouveau_conn_attach_properties(&mstc->connector);
1085
1086         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
1087                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1088
1089         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1090         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1091         drm_connector_set_path_property(&mstc->connector, path);
1092         drm_dp_mst_get_port_malloc(port);
1093         return 0;
1094 }
1095
1096 static void
1097 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1098 {
1099         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1100         struct drm_encoder *encoder;
1101         int ret;
1102
1103         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1104         ret = drm_dp_check_act_status(&mstm->mgr);
1105
1106         ret = drm_dp_update_payload_part2(&mstm->mgr);
1107
1108         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1109                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1110                         struct nv50_msto *msto = nv50_msto(encoder);
1111                         struct nv50_mstc *mstc = msto->mstc;
1112                         if (mstc && mstc->mstm == mstm)
1113                                 nv50_msto_cleanup(msto);
1114                 }
1115         }
1116
1117         mstm->modified = false;
1118 }
1119
1120 static void
1121 nv50_mstm_prepare(struct nv50_mstm *mstm)
1122 {
1123         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1124         struct drm_encoder *encoder;
1125         int ret;
1126
1127         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1128         ret = drm_dp_update_payload_part1(&mstm->mgr);
1129
1130         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1131                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1132                         struct nv50_msto *msto = nv50_msto(encoder);
1133                         struct nv50_mstc *mstc = msto->mstc;
1134                         if (mstc && mstc->mstm == mstm)
1135                                 nv50_msto_prepare(msto);
1136                 }
1137         }
1138
1139         if (mstm->disabled) {
1140                 if (!mstm->links)
1141                         nv50_outp_release(mstm->outp);
1142                 mstm->disabled = false;
1143         }
1144 }
1145
1146 static void
1147 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1148                             struct drm_connector *connector)
1149 {
1150         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1151         struct nv50_mstc *mstc = nv50_mstc(connector);
1152
1153         drm_connector_unregister(&mstc->connector);
1154
1155         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1156
1157         drm_connector_put(&mstc->connector);
1158 }
1159
1160 static void
1161 nv50_mstm_register_connector(struct drm_connector *connector)
1162 {
1163         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1164
1165         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1166
1167         drm_connector_register(connector);
1168 }
1169
1170 static struct drm_connector *
1171 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1172                         struct drm_dp_mst_port *port, const char *path)
1173 {
1174         struct nv50_mstm *mstm = nv50_mstm(mgr);
1175         struct nv50_mstc *mstc;
1176         int ret;
1177
1178         ret = nv50_mstc_new(mstm, port, path, &mstc);
1179         if (ret)
1180                 return NULL;
1181
1182         return &mstc->connector;
1183 }
1184
1185 static const struct drm_dp_mst_topology_cbs
1186 nv50_mstm = {
1187         .add_connector = nv50_mstm_add_connector,
1188         .register_connector = nv50_mstm_register_connector,
1189         .destroy_connector = nv50_mstm_destroy_connector,
1190 };
1191
1192 void
1193 nv50_mstm_service(struct nv50_mstm *mstm)
1194 {
1195         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1196         bool handled = true;
1197         int ret;
1198         u8 esi[8] = {};
1199
1200         if (!aux)
1201                 return;
1202
1203         while (handled) {
1204                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1205                 if (ret != 8) {
1206                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1207                         return;
1208                 }
1209
1210                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1211                 if (!handled)
1212                         break;
1213
1214                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1215         }
1216 }
1217
1218 void
1219 nv50_mstm_remove(struct nv50_mstm *mstm)
1220 {
1221         if (mstm)
1222                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1223 }
1224
1225 static int
1226 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1227 {
1228         struct nouveau_encoder *outp = mstm->outp;
1229         struct {
1230                 struct nv50_disp_mthd_v1 base;
1231                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1232         } args = {
1233                 .base.version = 1,
1234                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1235                 .base.hasht = outp->dcb->hasht,
1236                 .base.hashm = outp->dcb->hashm,
1237                 .mst.state = state,
1238         };
1239         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1240         struct nvif_object *disp = &drm->display->disp.object;
1241         int ret;
1242
1243         if (dpcd >= 0x12) {
1244                 /* Even if we're enabling MST, start with disabling the
1245                  * branching unit to clear any sink-side MST topology state
1246                  * that wasn't set by us
1247                  */
1248                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1249                 if (ret < 0)
1250                         return ret;
1251
1252                 if (state) {
1253                         /* Now, start initializing */
1254                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1255                                                  DP_MST_EN);
1256                         if (ret < 0)
1257                                 return ret;
1258                 }
1259         }
1260
1261         return nvif_mthd(disp, 0, &args, sizeof(args));
1262 }
1263
1264 int
1265 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1266 {
1267         struct drm_dp_aux *aux;
1268         int ret;
1269         bool old_state, new_state;
1270         u8 mstm_ctrl;
1271
1272         if (!mstm)
1273                 return 0;
1274
1275         mutex_lock(&mstm->mgr.lock);
1276
1277         old_state = mstm->mgr.mst_state;
1278         new_state = old_state;
1279         aux = mstm->mgr.aux;
1280
1281         if (old_state) {
1282                 /* Just check that the MST hub is still as we expect it */
1283                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1284                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1285                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1286                         new_state = false;
1287                 }
1288         } else if (dpcd[0] >= 0x12) {
1289                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1290                 if (ret < 0)
1291                         goto probe_error;
1292
1293                 if (!(dpcd[1] & DP_MST_CAP))
1294                         dpcd[0] = 0x11;
1295                 else
1296                         new_state = allow;
1297         }
1298
1299         if (new_state == old_state) {
1300                 mutex_unlock(&mstm->mgr.lock);
1301                 return new_state;
1302         }
1303
1304         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1305         if (ret)
1306                 goto probe_error;
1307
1308         mutex_unlock(&mstm->mgr.lock);
1309
1310         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1311         if (ret)
1312                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1313
1314         return new_state;
1315
1316 probe_error:
1317         mutex_unlock(&mstm->mgr.lock);
1318         return ret;
1319 }
1320
1321 static void
1322 nv50_mstm_fini(struct nv50_mstm *mstm)
1323 {
1324         if (mstm && mstm->mgr.mst_state)
1325                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1326 }
1327
1328 static void
1329 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1330 {
1331         int ret;
1332
1333         if (!mstm || !mstm->mgr.mst_state)
1334                 return;
1335
1336         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1337         if (ret == -1) {
1338                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1339                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1340         }
1341 }
1342
1343 static void
1344 nv50_mstm_del(struct nv50_mstm **pmstm)
1345 {
1346         struct nv50_mstm *mstm = *pmstm;
1347         if (mstm) {
1348                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1349                 kfree(*pmstm);
1350                 *pmstm = NULL;
1351         }
1352 }
1353
1354 static int
1355 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1356               int conn_base_id, struct nv50_mstm **pmstm)
1357 {
1358         const int max_payloads = hweight8(outp->dcb->heads);
1359         struct drm_device *dev = outp->base.base.dev;
1360         struct nv50_mstm *mstm;
1361         int ret, i;
1362         u8 dpcd;
1363
1364         /* This is a workaround for some monitors not functioning
1365          * correctly in MST mode on initial module load.  I think
1366          * some bad interaction with the VBIOS may be responsible.
1367          *
1368          * A good ol' off and on again seems to work here ;)
1369          */
1370         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1371         if (ret >= 0 && dpcd >= 0x12)
1372                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1373
1374         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1375                 return -ENOMEM;
1376         mstm->outp = outp;
1377         mstm->mgr.cbs = &nv50_mstm;
1378
1379         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1380                                            max_payloads, conn_base_id);
1381         if (ret)
1382                 return ret;
1383
1384         for (i = 0; i < max_payloads; i++) {
1385                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1386                                     i, &mstm->msto[i]);
1387                 if (ret)
1388                         return ret;
1389         }
1390
1391         return 0;
1392 }
1393
1394 /******************************************************************************
1395  * SOR
1396  *****************************************************************************/
1397 static void
1398 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1399                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1400 {
1401         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1402         struct nv50_core *core = disp->core;
1403
1404         if (!asyh) {
1405                 nv_encoder->ctrl &= ~BIT(head);
1406                 if (!(nv_encoder->ctrl & 0x0000000f))
1407                         nv_encoder->ctrl = 0;
1408         } else {
1409                 nv_encoder->ctrl |= proto << 8;
1410                 nv_encoder->ctrl |= BIT(head);
1411                 asyh->or.depth = depth;
1412         }
1413
1414         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1415 }
1416
1417 static void
1418 nv50_sor_disable(struct drm_encoder *encoder)
1419 {
1420         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1421         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1422
1423         nv_encoder->crtc = NULL;
1424
1425         if (nv_crtc) {
1426                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1427                 u8 pwr;
1428
1429                 if (aux) {
1430                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1431                         if (ret == 0) {
1432                                 pwr &= ~DP_SET_POWER_MASK;
1433                                 pwr |=  DP_SET_POWER_D3;
1434                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1435                         }
1436                 }
1437
1438                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1439                 nv50_audio_disable(encoder, nv_crtc);
1440                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1441                 nv50_outp_release(nv_encoder);
1442         }
1443 }
1444
1445 static void
1446 nv50_sor_enable(struct drm_encoder *encoder)
1447 {
1448         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1449         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1450         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1451         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1452         struct {
1453                 struct nv50_disp_mthd_v1 base;
1454                 struct nv50_disp_sor_lvds_script_v0 lvds;
1455         } lvds = {
1456                 .base.version = 1,
1457                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1458                 .base.hasht   = nv_encoder->dcb->hasht,
1459                 .base.hashm   = nv_encoder->dcb->hashm,
1460         };
1461         struct nv50_disp *disp = nv50_disp(encoder->dev);
1462         struct drm_device *dev = encoder->dev;
1463         struct nouveau_drm *drm = nouveau_drm(dev);
1464         struct nouveau_connector *nv_connector;
1465         struct nvbios *bios = &drm->vbios;
1466         u8 proto = 0xf;
1467         u8 depth = 0x0;
1468
1469         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1470         nv_encoder->crtc = encoder->crtc;
1471         nv50_outp_acquire(nv_encoder);
1472
1473         switch (nv_encoder->dcb->type) {
1474         case DCB_OUTPUT_TMDS:
1475                 if (nv_encoder->link & 1) {
1476                         proto = 0x1;
1477                         /* Only enable dual-link if:
1478                          *  - Need to (i.e. rate > 165MHz)
1479                          *  - DCB says we can
1480                          *  - Not an HDMI monitor, since there's no dual-link
1481                          *    on HDMI.
1482                          */
1483                         if (mode->clock >= 165000 &&
1484                             nv_encoder->dcb->duallink_possible &&
1485                             !drm_detect_hdmi_monitor(nv_connector->edid))
1486                                 proto |= 0x4;
1487                 } else {
1488                         proto = 0x2;
1489                 }
1490
1491                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1492                 break;
1493         case DCB_OUTPUT_LVDS:
1494                 proto = 0x0;
1495
1496                 if (bios->fp_no_ddc) {
1497                         if (bios->fp.dual_link)
1498                                 lvds.lvds.script |= 0x0100;
1499                         if (bios->fp.if_is_24bit)
1500                                 lvds.lvds.script |= 0x0200;
1501                 } else {
1502                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1503                                 if (((u8 *)nv_connector->edid)[121] == 2)
1504                                         lvds.lvds.script |= 0x0100;
1505                         } else
1506                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1507                                 lvds.lvds.script |= 0x0100;
1508                         }
1509
1510                         if (lvds.lvds.script & 0x0100) {
1511                                 if (bios->fp.strapless_is_24bit & 2)
1512                                         lvds.lvds.script |= 0x0200;
1513                         } else {
1514                                 if (bios->fp.strapless_is_24bit & 1)
1515                                         lvds.lvds.script |= 0x0200;
1516                         }
1517
1518                         if (asyh->or.bpc == 8)
1519                                 lvds.lvds.script |= 0x0200;
1520                 }
1521
1522                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1523                 break;
1524         case DCB_OUTPUT_DP:
1525                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1526
1527                 if (nv_encoder->link & 1)
1528                         proto = 0x8;
1529                 else
1530                         proto = 0x9;
1531
1532                 nv50_audio_enable(encoder, mode);
1533                 break;
1534         default:
1535                 BUG();
1536                 break;
1537         }
1538
1539         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1540 }
1541
1542 static const struct drm_encoder_helper_funcs
1543 nv50_sor_help = {
1544         .atomic_check = nv50_outp_atomic_check,
1545         .enable = nv50_sor_enable,
1546         .disable = nv50_sor_disable,
1547 };
1548
1549 static void
1550 nv50_sor_destroy(struct drm_encoder *encoder)
1551 {
1552         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1553         nv50_mstm_del(&nv_encoder->dp.mstm);
1554         drm_encoder_cleanup(encoder);
1555         kfree(encoder);
1556 }
1557
1558 static const struct drm_encoder_funcs
1559 nv50_sor_func = {
1560         .destroy = nv50_sor_destroy,
1561 };
1562
1563 static int
1564 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1565 {
1566         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1567         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1568         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1569         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1570         struct nouveau_encoder *nv_encoder;
1571         struct drm_encoder *encoder;
1572         u8 ver, hdr, cnt, len;
1573         u32 data;
1574         int type, ret;
1575
1576         switch (dcbe->type) {
1577         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1578         case DCB_OUTPUT_TMDS:
1579         case DCB_OUTPUT_DP:
1580         default:
1581                 type = DRM_MODE_ENCODER_TMDS;
1582                 break;
1583         }
1584
1585         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1586         if (!nv_encoder)
1587                 return -ENOMEM;
1588         nv_encoder->dcb = dcbe;
1589         nv_encoder->update = nv50_sor_update;
1590
1591         encoder = to_drm_encoder(nv_encoder);
1592         encoder->possible_crtcs = dcbe->heads;
1593         encoder->possible_clones = 0;
1594         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1595                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1596         drm_encoder_helper_add(encoder, &nv50_sor_help);
1597
1598         drm_connector_attach_encoder(connector, encoder);
1599
1600         if (dcbe->type == DCB_OUTPUT_DP) {
1601                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1602                 struct nvkm_i2c_aux *aux =
1603                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1604                 if (aux) {
1605                         if (disp->disp->object.oclass < GF110_DISP) {
1606                                 /* HW has no support for address-only
1607                                  * transactions, so we're required to
1608                                  * use custom I2C-over-AUX code.
1609                                  */
1610                                 nv_encoder->i2c = &aux->i2c;
1611                         } else {
1612                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1613                         }
1614                         nv_encoder->aux = aux;
1615                 }
1616
1617                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1618                     (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1619                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1620                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1621                                             nv_connector->base.base.id,
1622                                             &nv_encoder->dp.mstm);
1623                         if (ret)
1624                                 return ret;
1625                 }
1626         } else {
1627                 struct nvkm_i2c_bus *bus =
1628                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1629                 if (bus)
1630                         nv_encoder->i2c = &bus->i2c;
1631         }
1632
1633         return 0;
1634 }
1635
1636 /******************************************************************************
1637  * PIOR
1638  *****************************************************************************/
1639 static int
1640 nv50_pior_atomic_check(struct drm_encoder *encoder,
1641                        struct drm_crtc_state *crtc_state,
1642                        struct drm_connector_state *conn_state)
1643 {
1644         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1645         if (ret)
1646                 return ret;
1647         crtc_state->adjusted_mode.clock *= 2;
1648         return 0;
1649 }
1650
1651 static void
1652 nv50_pior_disable(struct drm_encoder *encoder)
1653 {
1654         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1655         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1656         if (nv_encoder->crtc)
1657                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1658         nv_encoder->crtc = NULL;
1659         nv50_outp_release(nv_encoder);
1660 }
1661
1662 static void
1663 nv50_pior_enable(struct drm_encoder *encoder)
1664 {
1665         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1666         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1667         struct nouveau_connector *nv_connector;
1668         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1669         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1670         u8 owner = 1 << nv_crtc->index;
1671         u8 proto;
1672
1673         nv50_outp_acquire(nv_encoder);
1674
1675         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1676         switch (asyh->or.bpc) {
1677         case 10: asyh->or.depth = 0x6; break;
1678         case  8: asyh->or.depth = 0x5; break;
1679         case  6: asyh->or.depth = 0x2; break;
1680         default: asyh->or.depth = 0x0; break;
1681         }
1682
1683         switch (nv_encoder->dcb->type) {
1684         case DCB_OUTPUT_TMDS:
1685         case DCB_OUTPUT_DP:
1686                 proto = 0x0;
1687                 break;
1688         default:
1689                 BUG();
1690                 break;
1691         }
1692
1693         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1694         nv_encoder->crtc = encoder->crtc;
1695 }
1696
1697 static const struct drm_encoder_helper_funcs
1698 nv50_pior_help = {
1699         .atomic_check = nv50_pior_atomic_check,
1700         .enable = nv50_pior_enable,
1701         .disable = nv50_pior_disable,
1702 };
1703
1704 static void
1705 nv50_pior_destroy(struct drm_encoder *encoder)
1706 {
1707         drm_encoder_cleanup(encoder);
1708         kfree(encoder);
1709 }
1710
1711 static const struct drm_encoder_funcs
1712 nv50_pior_func = {
1713         .destroy = nv50_pior_destroy,
1714 };
1715
1716 static int
1717 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1718 {
1719         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1720         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1721         struct nvkm_i2c_bus *bus = NULL;
1722         struct nvkm_i2c_aux *aux = NULL;
1723         struct i2c_adapter *ddc;
1724         struct nouveau_encoder *nv_encoder;
1725         struct drm_encoder *encoder;
1726         int type;
1727
1728         switch (dcbe->type) {
1729         case DCB_OUTPUT_TMDS:
1730                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1731                 ddc  = bus ? &bus->i2c : NULL;
1732                 type = DRM_MODE_ENCODER_TMDS;
1733                 break;
1734         case DCB_OUTPUT_DP:
1735                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1736                 ddc  = aux ? &aux->i2c : NULL;
1737                 type = DRM_MODE_ENCODER_TMDS;
1738                 break;
1739         default:
1740                 return -ENODEV;
1741         }
1742
1743         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1744         if (!nv_encoder)
1745                 return -ENOMEM;
1746         nv_encoder->dcb = dcbe;
1747         nv_encoder->i2c = ddc;
1748         nv_encoder->aux = aux;
1749
1750         encoder = to_drm_encoder(nv_encoder);
1751         encoder->possible_crtcs = dcbe->heads;
1752         encoder->possible_clones = 0;
1753         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1754                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1755         drm_encoder_helper_add(encoder, &nv50_pior_help);
1756
1757         drm_connector_attach_encoder(connector, encoder);
1758         return 0;
1759 }
1760
1761 /******************************************************************************
1762  * Atomic
1763  *****************************************************************************/
1764
1765 static void
1766 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1767 {
1768         struct nouveau_drm *drm = nouveau_drm(state->dev);
1769         struct nv50_disp *disp = nv50_disp(drm->dev);
1770         struct nv50_core *core = disp->core;
1771         struct nv50_mstm *mstm;
1772         struct drm_encoder *encoder;
1773
1774         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1775
1776         drm_for_each_encoder(encoder, drm->dev) {
1777                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1778                         mstm = nouveau_encoder(encoder)->dp.mstm;
1779                         if (mstm && mstm->modified)
1780                                 nv50_mstm_prepare(mstm);
1781                 }
1782         }
1783
1784         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1785         core->func->update(core, interlock, true);
1786         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1787                                        disp->core->chan.base.device))
1788                 NV_ERROR(drm, "core notifier timeout\n");
1789
1790         drm_for_each_encoder(encoder, drm->dev) {
1791                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1792                         mstm = nouveau_encoder(encoder)->dp.mstm;
1793                         if (mstm && mstm->modified)
1794                                 nv50_mstm_cleanup(mstm);
1795                 }
1796         }
1797 }
1798
1799 static void
1800 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1801 {
1802         struct drm_plane_state *new_plane_state;
1803         struct drm_plane *plane;
1804         int i;
1805
1806         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1807                 struct nv50_wndw *wndw = nv50_wndw(plane);
1808                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1809                         if (wndw->func->update)
1810                                 wndw->func->update(wndw, interlock);
1811                 }
1812         }
1813 }
1814
1815 static void
1816 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1817 {
1818         struct drm_device *dev = state->dev;
1819         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1820         struct drm_crtc *crtc;
1821         struct drm_plane_state *new_plane_state;
1822         struct drm_plane *plane;
1823         struct nouveau_drm *drm = nouveau_drm(dev);
1824         struct nv50_disp *disp = nv50_disp(dev);
1825         struct nv50_atom *atom = nv50_atom(state);
1826         struct nv50_outp_atom *outp, *outt;
1827         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1828         int i;
1829
1830         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1831         drm_atomic_helper_wait_for_fences(dev, state, false);
1832         drm_atomic_helper_wait_for_dependencies(state);
1833         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1834
1835         if (atom->lock_core)
1836                 mutex_lock(&disp->mutex);
1837
1838         /* Disable head(s). */
1839         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1840                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1841                 struct nv50_head *head = nv50_head(crtc);
1842
1843                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1844                           asyh->clr.mask, asyh->set.mask);
1845
1846                 if (old_crtc_state->active && !new_crtc_state->active) {
1847                         pm_runtime_put_noidle(dev->dev);
1848                         drm_crtc_vblank_off(crtc);
1849                 }
1850
1851                 if (asyh->clr.mask) {
1852                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1853                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1854                 }
1855         }
1856
1857         /* Disable plane(s). */
1858         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1859                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1860                 struct nv50_wndw *wndw = nv50_wndw(plane);
1861
1862                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1863                           asyw->clr.mask, asyw->set.mask);
1864                 if (!asyw->clr.mask)
1865                         continue;
1866
1867                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1868         }
1869
1870         /* Disable output path(s). */
1871         list_for_each_entry(outp, &atom->outp, head) {
1872                 const struct drm_encoder_helper_funcs *help;
1873                 struct drm_encoder *encoder;
1874
1875                 encoder = outp->encoder;
1876                 help = encoder->helper_private;
1877
1878                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1879                           outp->clr.mask, outp->set.mask);
1880
1881                 if (outp->clr.mask) {
1882                         help->disable(encoder);
1883                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1884                         if (outp->flush_disable) {
1885                                 nv50_disp_atomic_commit_wndw(state, interlock);
1886                                 nv50_disp_atomic_commit_core(state, interlock);
1887                                 memset(interlock, 0x00, sizeof(interlock));
1888                         }
1889                 }
1890         }
1891
1892         /* Flush disable. */
1893         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1894                 if (atom->flush_disable) {
1895                         nv50_disp_atomic_commit_wndw(state, interlock);
1896                         nv50_disp_atomic_commit_core(state, interlock);
1897                         memset(interlock, 0x00, sizeof(interlock));
1898                 }
1899         }
1900
1901         /* Update output path(s). */
1902         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1903                 const struct drm_encoder_helper_funcs *help;
1904                 struct drm_encoder *encoder;
1905
1906                 encoder = outp->encoder;
1907                 help = encoder->helper_private;
1908
1909                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1910                           outp->set.mask, outp->clr.mask);
1911
1912                 if (outp->set.mask) {
1913                         help->enable(encoder);
1914                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1915                 }
1916
1917                 list_del(&outp->head);
1918                 kfree(outp);
1919         }
1920
1921         /* Update head(s). */
1922         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1923                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1924                 struct nv50_head *head = nv50_head(crtc);
1925
1926                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1927                           asyh->set.mask, asyh->clr.mask);
1928
1929                 if (asyh->set.mask) {
1930                         nv50_head_flush_set(head, asyh);
1931                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1932                 }
1933
1934                 if (new_crtc_state->active) {
1935                         if (!old_crtc_state->active) {
1936                                 drm_crtc_vblank_on(crtc);
1937                                 pm_runtime_get_noresume(dev->dev);
1938                         }
1939                         if (new_crtc_state->event)
1940                                 drm_crtc_vblank_get(crtc);
1941                 }
1942         }
1943
1944         /* Update plane(s). */
1945         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1946                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1947                 struct nv50_wndw *wndw = nv50_wndw(plane);
1948
1949                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1950                           asyw->set.mask, asyw->clr.mask);
1951                 if ( !asyw->set.mask &&
1952                     (!asyw->clr.mask || atom->flush_disable))
1953                         continue;
1954
1955                 nv50_wndw_flush_set(wndw, interlock, asyw);
1956         }
1957
1958         /* Flush update. */
1959         nv50_disp_atomic_commit_wndw(state, interlock);
1960
1961         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1962                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1963                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1964                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1965                     !atom->state.legacy_cursor_update)
1966                         nv50_disp_atomic_commit_core(state, interlock);
1967                 else
1968                         disp->core->func->update(disp->core, interlock, false);
1969         }
1970
1971         if (atom->lock_core)
1972                 mutex_unlock(&disp->mutex);
1973
1974         /* Wait for HW to signal completion. */
1975         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1976                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1977                 struct nv50_wndw *wndw = nv50_wndw(plane);
1978                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1979                 if (ret)
1980                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1981         }
1982
1983         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1984                 if (new_crtc_state->event) {
1985                         unsigned long flags;
1986                         /* Get correct count/ts if racing with vblank irq */
1987                         if (new_crtc_state->active)
1988                                 drm_crtc_accurate_vblank_count(crtc);
1989                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1990                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1991                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1992
1993                         new_crtc_state->event = NULL;
1994                         if (new_crtc_state->active)
1995                                 drm_crtc_vblank_put(crtc);
1996                 }
1997         }
1998
1999         drm_atomic_helper_commit_hw_done(state);
2000         drm_atomic_helper_cleanup_planes(dev, state);
2001         drm_atomic_helper_commit_cleanup_done(state);
2002         drm_atomic_state_put(state);
2003
2004         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2005         pm_runtime_mark_last_busy(dev->dev);
2006         pm_runtime_put_autosuspend(dev->dev);
2007 }
2008
2009 static void
2010 nv50_disp_atomic_commit_work(struct work_struct *work)
2011 {
2012         struct drm_atomic_state *state =
2013                 container_of(work, typeof(*state), commit_work);
2014         nv50_disp_atomic_commit_tail(state);
2015 }
2016
2017 static int
2018 nv50_disp_atomic_commit(struct drm_device *dev,
2019                         struct drm_atomic_state *state, bool nonblock)
2020 {
2021         struct drm_plane_state *new_plane_state;
2022         struct drm_plane *plane;
2023         int ret, i;
2024
2025         ret = pm_runtime_get_sync(dev->dev);
2026         if (ret < 0 && ret != -EACCES)
2027                 return ret;
2028
2029         ret = drm_atomic_helper_setup_commit(state, nonblock);
2030         if (ret)
2031                 goto done;
2032
2033         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2034
2035         ret = drm_atomic_helper_prepare_planes(dev, state);
2036         if (ret)
2037                 goto done;
2038
2039         if (!nonblock) {
2040                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2041                 if (ret)
2042                         goto err_cleanup;
2043         }
2044
2045         ret = drm_atomic_helper_swap_state(state, true);
2046         if (ret)
2047                 goto err_cleanup;
2048
2049         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2050                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2051                 struct nv50_wndw *wndw = nv50_wndw(plane);
2052
2053                 if (asyw->set.image)
2054                         nv50_wndw_ntfy_enable(wndw, asyw);
2055         }
2056
2057         drm_atomic_state_get(state);
2058
2059         /*
2060          * Grab another RPM ref for the commit tail, which will release the
2061          * ref when it's finished
2062          */
2063         pm_runtime_get_noresume(dev->dev);
2064
2065         if (nonblock)
2066                 queue_work(system_unbound_wq, &state->commit_work);
2067         else
2068                 nv50_disp_atomic_commit_tail(state);
2069
2070 err_cleanup:
2071         if (ret)
2072                 drm_atomic_helper_cleanup_planes(dev, state);
2073 done:
2074         pm_runtime_put_autosuspend(dev->dev);
2075         return ret;
2076 }
2077
2078 static struct nv50_outp_atom *
2079 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2080 {
2081         struct nv50_outp_atom *outp;
2082
2083         list_for_each_entry(outp, &atom->outp, head) {
2084                 if (outp->encoder == encoder)
2085                         return outp;
2086         }
2087
2088         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2089         if (!outp)
2090                 return ERR_PTR(-ENOMEM);
2091
2092         list_add(&outp->head, &atom->outp);
2093         outp->encoder = encoder;
2094         return outp;
2095 }
2096
2097 static int
2098 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2099                                 struct drm_connector_state *old_connector_state)
2100 {
2101         struct drm_encoder *encoder = old_connector_state->best_encoder;
2102         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2103         struct drm_crtc *crtc;
2104         struct nv50_outp_atom *outp;
2105
2106         if (!(crtc = old_connector_state->crtc))
2107                 return 0;
2108
2109         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2110         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2111         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2112                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2113                 if (IS_ERR(outp))
2114                         return PTR_ERR(outp);
2115
2116                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2117                         outp->flush_disable = true;
2118                         atom->flush_disable = true;
2119                 }
2120                 outp->clr.ctrl = true;
2121                 atom->lock_core = true;
2122         }
2123
2124         return 0;
2125 }
2126
2127 static int
2128 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2129                                 struct drm_connector_state *connector_state)
2130 {
2131         struct drm_encoder *encoder = connector_state->best_encoder;
2132         struct drm_crtc_state *new_crtc_state;
2133         struct drm_crtc *crtc;
2134         struct nv50_outp_atom *outp;
2135
2136         if (!(crtc = connector_state->crtc))
2137                 return 0;
2138
2139         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2140         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2141                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2142                 if (IS_ERR(outp))
2143                         return PTR_ERR(outp);
2144
2145                 outp->set.ctrl = true;
2146                 atom->lock_core = true;
2147         }
2148
2149         return 0;
2150 }
2151
2152 static int
2153 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2154 {
2155         struct nv50_atom *atom = nv50_atom(state);
2156         struct drm_connector_state *old_connector_state, *new_connector_state;
2157         struct drm_connector *connector;
2158         struct drm_crtc_state *new_crtc_state;
2159         struct drm_crtc *crtc;
2160         int ret, i;
2161
2162         /* We need to handle colour management on a per-plane basis. */
2163         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2164                 if (new_crtc_state->color_mgmt_changed) {
2165                         ret = drm_atomic_add_affected_planes(state, crtc);
2166                         if (ret)
2167                                 return ret;
2168                 }
2169         }
2170
2171         ret = drm_atomic_helper_check(dev, state);
2172         if (ret)
2173                 return ret;
2174
2175         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2176                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2177                 if (ret)
2178                         return ret;
2179
2180                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2181                 if (ret)
2182                         return ret;
2183         }
2184
2185         ret = drm_dp_mst_atomic_check(state);
2186         if (ret)
2187                 return ret;
2188
2189         return 0;
2190 }
2191
2192 static void
2193 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2194 {
2195         struct nv50_atom *atom = nv50_atom(state);
2196         struct nv50_outp_atom *outp, *outt;
2197
2198         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2199                 list_del(&outp->head);
2200                 kfree(outp);
2201         }
2202
2203         drm_atomic_state_default_clear(state);
2204 }
2205
2206 static void
2207 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2208 {
2209         struct nv50_atom *atom = nv50_atom(state);
2210         drm_atomic_state_default_release(&atom->state);
2211         kfree(atom);
2212 }
2213
2214 static struct drm_atomic_state *
2215 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2216 {
2217         struct nv50_atom *atom;
2218         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2219             drm_atomic_state_init(dev, &atom->state) < 0) {
2220                 kfree(atom);
2221                 return NULL;
2222         }
2223         INIT_LIST_HEAD(&atom->outp);
2224         return &atom->state;
2225 }
2226
2227 static const struct drm_mode_config_funcs
2228 nv50_disp_func = {
2229         .fb_create = nouveau_user_framebuffer_create,
2230         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2231         .atomic_check = nv50_disp_atomic_check,
2232         .atomic_commit = nv50_disp_atomic_commit,
2233         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2234         .atomic_state_clear = nv50_disp_atomic_state_clear,
2235         .atomic_state_free = nv50_disp_atomic_state_free,
2236 };
2237
2238 /******************************************************************************
2239  * Init
2240  *****************************************************************************/
2241
2242 static void
2243 nv50_display_fini(struct drm_device *dev, bool suspend)
2244 {
2245         struct nouveau_encoder *nv_encoder;
2246         struct drm_encoder *encoder;
2247         struct drm_plane *plane;
2248
2249         drm_for_each_plane(plane, dev) {
2250                 struct nv50_wndw *wndw = nv50_wndw(plane);
2251                 if (plane->funcs != &nv50_wndw)
2252                         continue;
2253                 nv50_wndw_fini(wndw);
2254         }
2255
2256         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2257                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2258                         nv_encoder = nouveau_encoder(encoder);
2259                         nv50_mstm_fini(nv_encoder->dp.mstm);
2260                 }
2261         }
2262 }
2263
2264 static int
2265 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2266 {
2267         struct nv50_core *core = nv50_disp(dev)->core;
2268         struct drm_encoder *encoder;
2269         struct drm_plane *plane;
2270
2271         core->func->init(core);
2272
2273         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2274                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2275                         struct nouveau_encoder *nv_encoder =
2276                                 nouveau_encoder(encoder);
2277                         nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2278                 }
2279         }
2280
2281         drm_for_each_plane(plane, dev) {
2282                 struct nv50_wndw *wndw = nv50_wndw(plane);
2283                 if (plane->funcs != &nv50_wndw)
2284                         continue;
2285                 nv50_wndw_init(wndw);
2286         }
2287
2288         return 0;
2289 }
2290
2291 static void
2292 nv50_display_destroy(struct drm_device *dev)
2293 {
2294         struct nv50_disp *disp = nv50_disp(dev);
2295
2296         nv50_core_del(&disp->core);
2297
2298         nouveau_bo_unmap(disp->sync);
2299         if (disp->sync)
2300                 nouveau_bo_unpin(disp->sync);
2301         nouveau_bo_ref(NULL, &disp->sync);
2302
2303         nouveau_display(dev)->priv = NULL;
2304         kfree(disp);
2305 }
2306
2307 int
2308 nv50_display_create(struct drm_device *dev)
2309 {
2310         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2311         struct nouveau_drm *drm = nouveau_drm(dev);
2312         struct dcb_table *dcb = &drm->vbios.dcb;
2313         struct drm_connector *connector, *tmp;
2314         struct nv50_disp *disp;
2315         struct dcb_output *dcbe;
2316         int crtcs, ret, i;
2317
2318         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2319         if (!disp)
2320                 return -ENOMEM;
2321
2322         mutex_init(&disp->mutex);
2323
2324         nouveau_display(dev)->priv = disp;
2325         nouveau_display(dev)->dtor = nv50_display_destroy;
2326         nouveau_display(dev)->init = nv50_display_init;
2327         nouveau_display(dev)->fini = nv50_display_fini;
2328         disp->disp = &nouveau_display(dev)->disp;
2329         dev->mode_config.funcs = &nv50_disp_func;
2330         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2331         dev->mode_config.normalize_zpos = true;
2332
2333         /* small shared memory area we use for notifiers and semaphores */
2334         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2335                              0, 0x0000, NULL, NULL, &disp->sync);
2336         if (!ret) {
2337                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2338                 if (!ret) {
2339                         ret = nouveau_bo_map(disp->sync);
2340                         if (ret)
2341                                 nouveau_bo_unpin(disp->sync);
2342                 }
2343                 if (ret)
2344                         nouveau_bo_ref(NULL, &disp->sync);
2345         }
2346
2347         if (ret)
2348                 goto out;
2349
2350         /* allocate master evo channel */
2351         ret = nv50_core_new(drm, &disp->core);
2352         if (ret)
2353                 goto out;
2354
2355         /* create crtc objects to represent the hw heads */
2356         if (disp->disp->object.oclass >= GV100_DISP)
2357                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2358         else
2359         if (disp->disp->object.oclass >= GF110_DISP)
2360                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2361         else
2362                 crtcs = 0x3;
2363
2364         for (i = 0; i < fls(crtcs); i++) {
2365                 if (!(crtcs & (1 << i)))
2366                         continue;
2367                 ret = nv50_head_create(dev, i);
2368                 if (ret)
2369                         goto out;
2370         }
2371
2372         /* create encoder/connector objects based on VBIOS DCB table */
2373         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2374                 connector = nouveau_connector_create(dev, dcbe);
2375                 if (IS_ERR(connector))
2376                         continue;
2377
2378                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2379                         switch (dcbe->type) {
2380                         case DCB_OUTPUT_TMDS:
2381                         case DCB_OUTPUT_LVDS:
2382                         case DCB_OUTPUT_DP:
2383                                 ret = nv50_sor_create(connector, dcbe);
2384                                 break;
2385                         case DCB_OUTPUT_ANALOG:
2386                                 ret = nv50_dac_create(connector, dcbe);
2387                                 break;
2388                         default:
2389                                 ret = -ENODEV;
2390                                 break;
2391                         }
2392                 } else {
2393                         ret = nv50_pior_create(connector, dcbe);
2394                 }
2395
2396                 if (ret) {
2397                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2398                                      dcbe->location, dcbe->type,
2399                                      ffs(dcbe->or) - 1, ret);
2400                         ret = 0;
2401                 }
2402         }
2403
2404         /* cull any connectors we created that don't have an encoder */
2405         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2406                 if (connector->possible_encoders)
2407                         continue;
2408
2409                 NV_WARN(drm, "%s has no encoders, removing\n",
2410                         connector->name);
2411                 connector->funcs->destroy(connector);
2412         }
2413
2414         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2415         dev->vblank_disable_immediate = true;
2416
2417 out:
2418         if (ret)
2419                 nv50_display_destroy(dev);
2420         return ret;
2421 }