drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_dp_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_fb_helper.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <drm/drm_vblank.h>
  41
  42 #include <nvif/class.h>
  43 #include <nvif/cl0002.h>
  44 #include <nvif/cl5070.h>
  45 #include <nvif/cl507d.h>
  46 #include <nvif/event.h>
  47
  48 #include "nouveau_drv.h"
  49 #include "nouveau_dma.h"
  50 #include "nouveau_gem.h"
  51 #include "nouveau_connector.h"
  52 #include "nouveau_encoder.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55
  56 #include <subdev/bios/dp.h>
  57
  58 /******************************************************************************
  59  * Atomic state
  60  *****************************************************************************/
  61
  62 struct nv50_outp_atom {
  63         struct list_head head;
  64
  65         struct drm_encoder *encoder;
  66         bool flush_disable;
  67
  68         union nv50_outp_atom_mask {
  69                 struct {
  70                         bool ctrl:1;
  71                 };
  72                 u8 mask;
  73         } set, clr;
  74 };
  75
  76 /******************************************************************************
  77  * EVO channel
  78  *****************************************************************************/
  79
  80 static int
  81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  82                  const s32 *oclass, u8 head, void *data, u32 size,
  83                  struct nv50_chan *chan)
  84 {
  85         struct nvif_sclass *sclass;
  86         int ret, i, n;
  87
  88         chan->device = device;
  89
  90         ret = n = nvif_object_sclass_get(disp, &sclass);
  91         if (ret < 0)
  92                 return ret;
  93
  94         while (oclass[0]) {
  95                 for (i = 0; i < n; i++) {
  96                         if (sclass[i].oclass == oclass[0]) {
  97                                 ret = nvif_object_init(disp, 0, oclass[0],
  98                                                        data, size, &chan->user);
  99                                 if (ret == 0)
 100                                         nvif_object_map(&chan->user, NULL, 0);
 101                                 nvif_object_sclass_put(&sclass);
 102                                 return ret;
 103                         }
 104                 }
 105                 oclass++;
 106         }
 107
 108         nvif_object_sclass_put(&sclass);
 109         return -ENOSYS;
 110 }
 111
 112 static void
 113 nv50_chan_destroy(struct nv50_chan *chan)
 114 {
 115         nvif_object_fini(&chan->user);
 116 }
 117
 118 /******************************************************************************
 119  * DMA EVO channel
 120  *****************************************************************************/
 121
 122 void
 123 nv50_dmac_destroy(struct nv50_dmac *dmac)
 124 {
 125         nvif_object_fini(&dmac->vram);
 126         nvif_object_fini(&dmac->sync);
 127
 128         nv50_chan_destroy(&dmac->base);
 129
 130         nvif_mem_fini(&dmac->push);
 131 }
 132
 133 int
 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 135                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 136                  struct nv50_dmac *dmac)
 137 {
 138         struct nouveau_cli *cli = (void *)device->object.client;
 139         struct nv50_disp_core_channel_dma_v0 *args = data;
 140         u8 type = NVIF_MEM_COHERENT;
 141         int ret;
 142
 143         mutex_init(&dmac->lock);
 144
 145         /* Pascal added support for 47-bit physical addresses, but some
 146          * parts of EVO still only accept 40-bit PAs.
 147          *
 148          * To avoid issues on systems with large amounts of RAM, and on
 149          * systems where an IOMMU maps pages at a high address, we need
 150          * to allocate push buffers in VRAM instead.
 151          *
 152          * This appears to match NVIDIA's behaviour on Pascal.
 153          */
 154         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 155                 type |= NVIF_MEM_VRAM;
 156
 157         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 158         if (ret)
 159                 return ret;
 160
 161         dmac->ptr = dmac->push.object.map.ptr;
 162
 163         args->pushbuf = nvif_handle(&dmac->push.object);
 164
 165         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 166                                &dmac->base);
 167         if (ret)
 168                 return ret;
 169
 170         if (!syncbuf)
 171                 return 0;
 172
 173         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 174                                &(struct nv_dma_v0) {
 175                                         .target = NV_DMA_V0_TARGET_VRAM,
 176                                         .access = NV_DMA_V0_ACCESS_RDWR,
 177                                         .start = syncbuf + 0x0000,
 178                                         .limit = syncbuf + 0x0fff,
 179                                }, sizeof(struct nv_dma_v0),
 180                                &dmac->sync);
 181         if (ret)
 182                 return ret;
 183
 184         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 185                                &(struct nv_dma_v0) {
 186                                         .target = NV_DMA_V0_TARGET_VRAM,
 187                                         .access = NV_DMA_V0_ACCESS_RDWR,
 188                                         .start = 0,
 189                                         .limit = device->info.ram_user - 1,
 190                                }, sizeof(struct nv_dma_v0),
 191                                &dmac->vram);
 192         if (ret)
 193                 return ret;
 194
 195         return ret;
 196 }
 197
 198 /******************************************************************************
 199  * EVO channel helpers
 200  *****************************************************************************/
 201 static void
 202 evo_flush(struct nv50_dmac *dmac)
 203 {
 204         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 205          * writes have been flushed right through to VRAM before writing PUT.
 206          */
 207         if (dmac->push.type & NVIF_MEM_VRAM) {
 208                 struct nvif_device *device = dmac->base.device;
 209                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 210                 nvif_msec(device, 2000,
 211                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 212                                 break;
 213                 );
 214         }
 215 }
 216
 217 u32 *
 218 evo_wait(struct nv50_dmac *evoc, int nr)
 219 {
 220         struct nv50_dmac *dmac = evoc;
 221         struct nvif_device *device = dmac->base.device;
 222         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 223
 224         mutex_lock(&dmac->lock);
 225         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 226                 dmac->ptr[put] = 0x20000000;
 227                 evo_flush(dmac);
 228
 229                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 230                 if (nvif_msec(device, 2000,
 231                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 232                                 break;
 233                 ) < 0) {
 234                         mutex_unlock(&dmac->lock);
 235                         pr_err("nouveau: evo channel stalled\n");
 236                         return NULL;
 237                 }
 238
 239                 put = 0;
 240         }
 241
 242         return dmac->ptr + put;
 243 }
 244
 245 void
 246 evo_kick(u32 *push, struct nv50_dmac *evoc)
 247 {
 248         struct nv50_dmac *dmac = evoc;
 249
 250         evo_flush(dmac);
 251
 252         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 253         mutex_unlock(&dmac->lock);
 254 }
 255
 256 /******************************************************************************
 257  * Output path helpers
 258  *****************************************************************************/
 259 static void
 260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 261 {
 262         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 263         struct {
 264                 struct nv50_disp_mthd_v1 base;
 265         } args = {
 266                 .base.version = 1,
 267                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 268                 .base.hasht  = nv_encoder->dcb->hasht,
 269                 .base.hashm  = nv_encoder->dcb->hashm,
 270         };
 271
 272         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 273         nv_encoder->or = -1;
 274         nv_encoder->link = 0;
 275 }
 276
 277 static int
 278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 279 {
 280         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 281         struct nv50_disp *disp = nv50_disp(drm->dev);
 282         struct {
 283                 struct nv50_disp_mthd_v1 base;
 284                 struct nv50_disp_acquire_v0 info;
 285         } args = {
 286                 .base.version = 1,
 287                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 288                 .base.hasht  = nv_encoder->dcb->hasht,
 289                 .base.hashm  = nv_encoder->dcb->hashm,
 290         };
 291         int ret;
 292
 293         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 294         if (ret) {
 295                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 296                 return ret;
 297         }
 298
 299         nv_encoder->or = args.info.or;
 300         nv_encoder->link = args.info.link;
 301         return 0;
 302 }
 303
 304 static int
 305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 306                             struct drm_crtc_state *crtc_state,
 307                             struct drm_connector_state *conn_state,
 308                             struct drm_display_mode *native_mode)
 309 {
 310         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 311         struct drm_display_mode *mode = &crtc_state->mode;
 312         struct drm_connector *connector = conn_state->connector;
 313         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 314         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 315
 316         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 317         asyc->scaler.full = false;
 318         if (!native_mode)
 319                 return 0;
 320
 321         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 322                 switch (connector->connector_type) {
 323                 case DRM_MODE_CONNECTOR_LVDS:
 324                 case DRM_MODE_CONNECTOR_eDP:
 325                         /* Don't force scaler for EDID modes with
 326                          * same size as the native one (e.g. different
 327                          * refresh rate)
 328                          */
 329                         if (mode->hdisplay == native_mode->hdisplay &&
 330                             mode->vdisplay == native_mode->vdisplay &&
 331                             mode->type & DRM_MODE_TYPE_DRIVER)
 332                                 break;
 333                         mode = native_mode;
 334                         asyc->scaler.full = true;
 335                         break;
 336                 default:
 337                         break;
 338                 }
 339         } else {
 340                 mode = native_mode;
 341         }
 342
 343         if (!drm_mode_equal(adjusted_mode, mode)) {
 344                 drm_mode_copy(adjusted_mode, mode);
 345                 crtc_state->mode_changed = true;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int
 352 nv50_outp_atomic_check(struct drm_encoder *encoder,
 353                        struct drm_crtc_state *crtc_state,
 354                        struct drm_connector_state *conn_state)
 355 {
 356         struct drm_connector *connector = conn_state->connector;
 357         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 358         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 359         int ret;
 360
 361         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 362                                           nv_connector->native_mode);
 363         if (ret)
 364                 return ret;
 365
 366         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 367                 asyh->or.bpc = connector->display_info.bpc;
 368
 369         return 0;
 370 }
 371
 372 /******************************************************************************
 373  * DAC
 374  *****************************************************************************/
 375 static void
 376 nv50_dac_disable(struct drm_encoder *encoder)
 377 {
 378         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 379         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 380         if (nv_encoder->crtc)
 381                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 382         nv_encoder->crtc = NULL;
 383         nv50_outp_release(nv_encoder);
 384 }
 385
 386 static void
 387 nv50_dac_enable(struct drm_encoder *encoder)
 388 {
 389         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 390         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 391         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 392         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 393
 394         nv50_outp_acquire(nv_encoder);
 395
 396         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 397         asyh->or.depth = 0;
 398
 399         nv_encoder->crtc = encoder->crtc;
 400 }
 401
 402 static enum drm_connector_status
 403 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 404 {
 405         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 406         struct nv50_disp *disp = nv50_disp(encoder->dev);
 407         struct {
 408                 struct nv50_disp_mthd_v1 base;
 409                 struct nv50_disp_dac_load_v0 load;
 410         } args = {
 411                 .base.version = 1,
 412                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 413                 .base.hasht  = nv_encoder->dcb->hasht,
 414                 .base.hashm  = nv_encoder->dcb->hashm,
 415         };
 416         int ret;
 417
 418         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 419         if (args.load.data == 0)
 420                 args.load.data = 340;
 421
 422         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 423         if (ret || !args.load.load)
 424                 return connector_status_disconnected;
 425
 426         return connector_status_connected;
 427 }
 428
 429 static const struct drm_encoder_helper_funcs
 430 nv50_dac_help = {
 431         .atomic_check = nv50_outp_atomic_check,
 432         .enable = nv50_dac_enable,
 433         .disable = nv50_dac_disable,
 434         .detect = nv50_dac_detect
 435 };
 436
 437 static void
 438 nv50_dac_destroy(struct drm_encoder *encoder)
 439 {
 440         drm_encoder_cleanup(encoder);
 441         kfree(encoder);
 442 }
 443
 444 static const struct drm_encoder_funcs
 445 nv50_dac_func = {
 446         .destroy = nv50_dac_destroy,
 447 };
 448
 449 static int
 450 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 451 {
 452         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 453         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 454         struct nvkm_i2c_bus *bus;
 455         struct nouveau_encoder *nv_encoder;
 456         struct drm_encoder *encoder;
 457         int type = DRM_MODE_ENCODER_DAC;
 458
 459         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 460         if (!nv_encoder)
 461                 return -ENOMEM;
 462         nv_encoder->dcb = dcbe;
 463
 464         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 465         if (bus)
 466                 nv_encoder->i2c = &bus->i2c;
 467
 468         encoder = to_drm_encoder(nv_encoder);
 469         encoder->possible_crtcs = dcbe->heads;
 470         encoder->possible_clones = 0;
 471         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 472                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 473         drm_encoder_helper_add(encoder, &nv50_dac_help);
 474
 475         drm_connector_attach_encoder(connector, encoder);
 476         return 0;
 477 }
 478
 479 /******************************************************************************
 480  * Audio
 481  *****************************************************************************/
 482 static void
 483 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 484 {
 485         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 486         struct nv50_disp *disp = nv50_disp(encoder->dev);
 487         struct {
 488                 struct nv50_disp_mthd_v1 base;
 489                 struct nv50_disp_sor_hda_eld_v0 eld;
 490         } args = {
 491                 .base.version = 1,
 492                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 493                 .base.hasht   = nv_encoder->dcb->hasht,
 494                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 495                                 (0x0100 << nv_crtc->index),
 496         };
 497
 498         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 499 }
 500
 501 static void
 502 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 503 {
 504         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 505         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 506         struct nouveau_connector *nv_connector;
 507         struct nv50_disp *disp = nv50_disp(encoder->dev);
 508         struct __packed {
 509                 struct {
 510                         struct nv50_disp_mthd_v1 mthd;
 511                         struct nv50_disp_sor_hda_eld_v0 eld;
 512                 } base;
 513                 u8 data[sizeof(nv_connector->base.eld)];
 514         } args = {
 515                 .base.mthd.version = 1,
 516                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 517                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 518                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 519                                      (0x0100 << nv_crtc->index),
 520         };
 521
 522         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 523         if (!drm_detect_monitor_audio(nv_connector->edid))
 524                 return;
 525
 526         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 527
 528         nvif_mthd(&disp->disp->object, 0, &args,
 529                   sizeof(args.base) + drm_eld_size(args.data));
 530 }
 531
 532 /******************************************************************************
 533  * HDMI
 534  *****************************************************************************/
 535 static void
 536 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 537 {
 538         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 539         struct nv50_disp *disp = nv50_disp(encoder->dev);
 540         struct {
 541                 struct nv50_disp_mthd_v1 base;
 542                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 543         } args = {
 544                 .base.version = 1,
 545                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 546                 .base.hasht  = nv_encoder->dcb->hasht,
 547                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 548                                (0x0100 << nv_crtc->index),
 549         };
 550
 551         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 552 }
 553
 554 static void
 555 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 556 {
 557         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 558         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 559         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 560         struct nv50_disp *disp = nv50_disp(encoder->dev);
 561         struct {
 562                 struct nv50_disp_mthd_v1 base;
 563                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 564                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 565         } args = {
 566                 .base.version = 1,
 567                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 568                 .base.hasht  = nv_encoder->dcb->hasht,
 569                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 570                                (0x0100 << nv_crtc->index),
 571                 .pwr.state = 1,
 572                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 573         };
 574         struct nouveau_connector *nv_connector;
 575         struct drm_hdmi_info *hdmi;
 576         u32 max_ac_packet;
 577         union hdmi_infoframe avi_frame;
 578         union hdmi_infoframe vendor_frame;
 579         bool high_tmds_clock_ratio = false, scrambling = false;
 580         u8 config;
 581         int ret;
 582         int size;
 583
 584         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 585         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 586                 return;
 587
 588         hdmi = &nv_connector->base.display_info.hdmi;
 589
 590         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 591                                                        &nv_connector->base, mode);
 592         if (!ret) {
 593                 /* We have an AVI InfoFrame, populate it to the display */
 594                 args.pwr.avi_infoframe_length
 595                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 596         }
 597
 598         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 599                                                           &nv_connector->base, mode);
 600         if (!ret) {
 601                 /* We have a Vendor InfoFrame, populate it to the display */
 602                 args.pwr.vendor_infoframe_length
 603                         = hdmi_infoframe_pack(&vendor_frame,
 604                                               args.infoframes
 605                                               + args.pwr.avi_infoframe_length,
 606                                               17);
 607         }
 608
 609         max_ac_packet  = mode->htotal - mode->hdisplay;
 610         max_ac_packet -= args.pwr.rekey;
 611         max_ac_packet -= 18; /* constant from tegra */
 612         args.pwr.max_ac_packet = max_ac_packet / 32;
 613
 614         if (hdmi->scdc.scrambling.supported) {
 615                 high_tmds_clock_ratio = mode->clock > 340000;
 616                 scrambling = high_tmds_clock_ratio ||
 617                         hdmi->scdc.scrambling.low_rates;
 618         }
 619
 620         args.pwr.scdc =
 621                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 622                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 623
 624         size = sizeof(args.base)
 625                 + sizeof(args.pwr)
 626                 + args.pwr.avi_infoframe_length
 627                 + args.pwr.vendor_infoframe_length;
 628         nvif_mthd(&disp->disp->object, 0, &args, size);
 629
 630         nv50_audio_enable(encoder, mode);
 631
 632         /* If SCDC is supported by the downstream monitor, update
 633          * divider / scrambling settings to what we programmed above.
 634          */
 635         if (!hdmi->scdc.scrambling.supported)
 636                 return;
 637
 638         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 639         if (ret < 0) {
 640                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 641                 return;
 642         }
 643         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 644         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 645         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 646         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 647         if (ret < 0)
 648                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 649                          config, ret);
 650 }
 651
 652 /******************************************************************************
 653  * MST
 654  *****************************************************************************/
 655 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 656 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 657 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 658
 659 struct nv50_mstm {
 660         struct nouveau_encoder *outp;
 661
 662         struct drm_dp_mst_topology_mgr mgr;
 663
 664         bool modified;
 665         bool disabled;
 666         int links;
 667 };
 668
 669 struct nv50_mstc {
 670         struct nv50_mstm *mstm;
 671         struct drm_dp_mst_port *port;
 672         struct drm_connector connector;
 673
 674         struct drm_display_mode *native;
 675         struct edid *edid;
 676 };
 677
 678 struct nv50_msto {
 679         struct drm_encoder encoder;
 680
 681         struct nv50_head *head;
 682         struct nv50_mstc *mstc;
 683         bool disabled;
 684 };
 685
 686 static struct drm_dp_payload *
 687 nv50_msto_payload(struct nv50_msto *msto)
 688 {
 689         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 690         struct nv50_mstc *mstc = msto->mstc;
 691         struct nv50_mstm *mstm = mstc->mstm;
 692         int vcpi = mstc->port->vcpi.vcpi, i;
 693
 694         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 695
 696         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 697         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 698                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 699                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 700                           mstm->outp->base.base.name, i, payload->vcpi,
 701                           payload->start_slot, payload->num_slots);
 702         }
 703
 704         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 705                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 706                 if (payload->vcpi == vcpi)
 707                         return payload;
 708         }
 709
 710         return NULL;
 711 }
 712
 713 static void
 714 nv50_msto_cleanup(struct nv50_msto *msto)
 715 {
 716         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 717         struct nv50_mstc *mstc = msto->mstc;
 718         struct nv50_mstm *mstm = mstc->mstm;
 719
 720         if (!msto->disabled)
 721                 return;
 722
 723         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 724
 725         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 726
 727         msto->mstc = NULL;
 728         msto->disabled = false;
 729 }
 730
 731 static void
 732 nv50_msto_prepare(struct nv50_msto *msto)
 733 {
 734         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 735         struct nv50_mstc *mstc = msto->mstc;
 736         struct nv50_mstm *mstm = mstc->mstm;
 737         struct {
 738                 struct nv50_disp_mthd_v1 base;
 739                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 740         } args = {
 741                 .base.version = 1,
 742                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 743                 .base.hasht  = mstm->outp->dcb->hasht,
 744                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 745                                (0x0100 << msto->head->base.index),
 746         };
 747
 748         mutex_lock(&mstm->mgr.payload_lock);
 749
 750         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 751         if (mstc->port->vcpi.vcpi > 0) {
 752                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 753                 if (payload) {
 754                         args.vcpi.start_slot = payload->start_slot;
 755                         args.vcpi.num_slots = payload->num_slots;
 756                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 757                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 758                 }
 759         }
 760
 761         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 762                   msto->encoder.name, msto->head->base.base.name,
 763                   args.vcpi.start_slot, args.vcpi.num_slots,
 764                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 765
 766         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 767         mutex_unlock(&mstm->mgr.payload_lock);
 768 }
 769
 770 static int
 771 nv50_msto_atomic_check(struct drm_encoder *encoder,
 772                        struct drm_crtc_state *crtc_state,
 773                        struct drm_connector_state *conn_state)
 774 {
 775         struct drm_atomic_state *state = crtc_state->state;
 776         struct drm_connector *connector = conn_state->connector;
 777         struct nv50_mstc *mstc = nv50_mstc(connector);
 778         struct nv50_mstm *mstm = mstc->mstm;
 779         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 780         int slots;
 781         int ret;
 782
 783         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 784                                           mstc->native);
 785         if (ret)
 786                 return ret;
 787
 788         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
 789                 return 0;
 790
 791         /*
 792          * When restoring duplicated states, we need to make sure that the bw
 793          * remains the same and avoid recalculating it, as the connector's bpc
 794          * may have changed after the state was duplicated
 795          */
 796         if (!state->duplicated) {
 797                 const int clock = crtc_state->adjusted_mode.clock;
 798
 799                 /*
 800                  * XXX: Since we don't use HDR in userspace quite yet, limit
 801                  * the bpc to 8 to save bandwidth on the topology. In the
 802                  * future, we'll want to properly fix this by dynamically
 803                  * selecting the highest possible bpc that would fit in the
 804                  * topology
 805                  */
 806                 asyh->or.bpc = min(connector->display_info.bpc, 8U);
 807                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, false);
 808         }
 809
 810         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
 811                                               asyh->dp.pbn, 0);
 812         if (slots < 0)
 813                 return slots;
 814
 815         asyh->dp.tu = slots;
 816
 817         return 0;
 818 }
 819
 820 static u8
 821 nv50_dp_bpc_to_depth(unsigned int bpc)
 822 {
 823         switch (bpc) {
 824         case  6: return 0x2;
 825         case  8: return 0x5;
 826         case 10: /* fall-through */
 827         default: return 0x6;
 828         }
 829 }
 830
 831 static void
 832 nv50_msto_enable(struct drm_encoder *encoder)
 833 {
 834         struct nv50_head *head = nv50_head(encoder->crtc);
 835         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
 836         struct nv50_msto *msto = nv50_msto(encoder);
 837         struct nv50_mstc *mstc = NULL;
 838         struct nv50_mstm *mstm = NULL;
 839         struct drm_connector *connector;
 840         struct drm_connector_list_iter conn_iter;
 841         u8 proto;
 842         bool r;
 843
 844         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 845         drm_for_each_connector_iter(connector, &conn_iter) {
 846                 if (connector->state->best_encoder == &msto->encoder) {
 847                         mstc = nv50_mstc(connector);
 848                         mstm = mstc->mstm;
 849                         break;
 850                 }
 851         }
 852         drm_connector_list_iter_end(&conn_iter);
 853
 854         if (WARN_ON(!mstc))
 855                 return;
 856
 857         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
 858                                      armh->dp.tu);
 859         if (!r)
 860                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
 861
 862         if (!mstm->links++)
 863                 nv50_outp_acquire(mstm->outp);
 864
 865         if (mstm->outp->link & 1)
 866                 proto = 0x8;
 867         else
 868                 proto = 0x9;
 869
 870         mstm->outp->update(mstm->outp, head->base.index, armh, proto,
 871                            nv50_dp_bpc_to_depth(armh->or.bpc));
 872
 873         msto->mstc = mstc;
 874         mstm->modified = true;
 875 }
 876
 877 static void
 878 nv50_msto_disable(struct drm_encoder *encoder)
 879 {
 880         struct nv50_msto *msto = nv50_msto(encoder);
 881         struct nv50_mstc *mstc = msto->mstc;
 882         struct nv50_mstm *mstm = mstc->mstm;
 883
 884         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 885
 886         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 887         mstm->modified = true;
 888         if (!--mstm->links)
 889                 mstm->disabled = true;
 890         msto->disabled = true;
 891 }
 892
 893 static const struct drm_encoder_helper_funcs
 894 nv50_msto_help = {
 895         .disable = nv50_msto_disable,
 896         .enable = nv50_msto_enable,
 897         .atomic_check = nv50_msto_atomic_check,
 898 };
 899
 900 static void
 901 nv50_msto_destroy(struct drm_encoder *encoder)
 902 {
 903         struct nv50_msto *msto = nv50_msto(encoder);
 904         drm_encoder_cleanup(&msto->encoder);
 905         kfree(msto);
 906 }
 907
 908 static const struct drm_encoder_funcs
 909 nv50_msto = {
 910         .destroy = nv50_msto_destroy,
 911 };
 912
 913 static struct nv50_msto *
 914 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
 915 {
 916         struct nv50_msto *msto;
 917         int ret;
 918
 919         msto = kzalloc(sizeof(*msto), GFP_KERNEL);
 920         if (!msto)
 921                 return ERR_PTR(-ENOMEM);
 922
 923         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 924                                DRM_MODE_ENCODER_DPMST, "mst-%d", id);
 925         if (ret) {
 926                 kfree(msto);
 927                 return ERR_PTR(ret);
 928         }
 929
 930         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 931         msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
 932         msto->head = head;
 933         return msto;
 934 }
 935
 936 static struct drm_encoder *
 937 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 938                               struct drm_connector_state *connector_state)
 939 {
 940         struct nv50_mstc *mstc = nv50_mstc(connector);
 941         struct drm_crtc *crtc = connector_state->crtc;
 942
 943         if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
 944                 return NULL;
 945
 946         return &nv50_head(crtc)->msto->encoder;
 947 }
 948
 949 static enum drm_mode_status
 950 nv50_mstc_mode_valid(struct drm_connector *connector,
 951                      struct drm_display_mode *mode)
 952 {
 953         return MODE_OK;
 954 }
 955
 956 static int
 957 nv50_mstc_get_modes(struct drm_connector *connector)
 958 {
 959         struct nv50_mstc *mstc = nv50_mstc(connector);
 960         int ret = 0;
 961
 962         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 963         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 964         if (mstc->edid)
 965                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 966
 967         if (!mstc->connector.display_info.bpc)
 968                 mstc->connector.display_info.bpc = 8;
 969
 970         if (mstc->native)
 971                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 972         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 973         return ret;
 974 }
 975
 976 static int
 977 nv50_mstc_atomic_check(struct drm_connector *connector,
 978                        struct drm_atomic_state *state)
 979 {
 980         struct nv50_mstc *mstc = nv50_mstc(connector);
 981         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
 982         struct drm_connector_state *new_conn_state =
 983                 drm_atomic_get_new_connector_state(state, connector);
 984         struct drm_connector_state *old_conn_state =
 985                 drm_atomic_get_old_connector_state(state, connector);
 986         struct drm_crtc_state *crtc_state;
 987         struct drm_crtc *new_crtc = new_conn_state->crtc;
 988
 989         if (!old_conn_state->crtc)
 990                 return 0;
 991
 992         /* We only want to free VCPI if this state disables the CRTC on this
 993          * connector
 994          */
 995         if (new_crtc) {
 996                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
 997
 998                 if (!crtc_state ||
 999                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1000                     crtc_state->enable)
1001                         return 0;
1002         }
1003
1004         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1005 }
1006
1007 static int
1008 nv50_mstc_detect(struct drm_connector *connector,
1009                  struct drm_modeset_acquire_ctx *ctx, bool force)
1010 {
1011         struct nv50_mstc *mstc = nv50_mstc(connector);
1012         int ret;
1013
1014         if (drm_connector_is_unregistered(connector))
1015                 return connector_status_disconnected;
1016
1017         ret = pm_runtime_get_sync(connector->dev->dev);
1018         if (ret < 0 && ret != -EACCES)
1019                 return connector_status_disconnected;
1020
1021         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1022                                      mstc->port);
1023
1024         pm_runtime_mark_last_busy(connector->dev->dev);
1025         pm_runtime_put_autosuspend(connector->dev->dev);
1026         return ret;
1027 }
1028
1029 static const struct drm_connector_helper_funcs
1030 nv50_mstc_help = {
1031         .get_modes = nv50_mstc_get_modes,
1032         .mode_valid = nv50_mstc_mode_valid,
1033         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1034         .atomic_check = nv50_mstc_atomic_check,
1035         .detect_ctx = nv50_mstc_detect,
1036 };
1037
1038 static void
1039 nv50_mstc_destroy(struct drm_connector *connector)
1040 {
1041         struct nv50_mstc *mstc = nv50_mstc(connector);
1042
1043         drm_connector_cleanup(&mstc->connector);
1044         drm_dp_mst_put_port_malloc(mstc->port);
1045
1046         kfree(mstc);
1047 }
1048
1049 static const struct drm_connector_funcs
1050 nv50_mstc = {
1051         .reset = nouveau_conn_reset,
1052         .fill_modes = drm_helper_probe_single_connector_modes,
1053         .destroy = nv50_mstc_destroy,
1054         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1055         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1056         .atomic_set_property = nouveau_conn_atomic_set_property,
1057         .atomic_get_property = nouveau_conn_atomic_get_property,
1058 };
1059
1060 static int
1061 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1062               const char *path, struct nv50_mstc **pmstc)
1063 {
1064         struct drm_device *dev = mstm->outp->base.base.dev;
1065         struct drm_crtc *crtc;
1066         struct nv50_mstc *mstc;
1067         int ret;
1068
1069         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1070                 return -ENOMEM;
1071         mstc->mstm = mstm;
1072         mstc->port = port;
1073
1074         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1075                                  DRM_MODE_CONNECTOR_DisplayPort);
1076         if (ret) {
1077                 kfree(*pmstc);
1078                 *pmstc = NULL;
1079                 return ret;
1080         }
1081
1082         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1083
1084         mstc->connector.funcs->reset(&mstc->connector);
1085         nouveau_conn_attach_properties(&mstc->connector);
1086
1087         drm_for_each_crtc(crtc, dev) {
1088                 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1089                         continue;
1090
1091                 drm_connector_attach_encoder(&mstc->connector,
1092                                              &nv50_head(crtc)->msto->encoder);
1093         }
1094
1095         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1096         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1097         drm_connector_set_path_property(&mstc->connector, path);
1098         drm_dp_mst_get_port_malloc(port);
1099         return 0;
1100 }
1101
1102 static void
1103 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1104 {
1105         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1106         struct drm_encoder *encoder;
1107         int ret;
1108
1109         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1110         ret = drm_dp_check_act_status(&mstm->mgr);
1111
1112         ret = drm_dp_update_payload_part2(&mstm->mgr);
1113
1114         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1115                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1116                         struct nv50_msto *msto = nv50_msto(encoder);
1117                         struct nv50_mstc *mstc = msto->mstc;
1118                         if (mstc && mstc->mstm == mstm)
1119                                 nv50_msto_cleanup(msto);
1120                 }
1121         }
1122
1123         mstm->modified = false;
1124 }
1125
1126 static void
1127 nv50_mstm_prepare(struct nv50_mstm *mstm)
1128 {
1129         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1130         struct drm_encoder *encoder;
1131         int ret;
1132
1133         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1134         ret = drm_dp_update_payload_part1(&mstm->mgr);
1135
1136         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1137                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1138                         struct nv50_msto *msto = nv50_msto(encoder);
1139                         struct nv50_mstc *mstc = msto->mstc;
1140                         if (mstc && mstc->mstm == mstm)
1141                                 nv50_msto_prepare(msto);
1142                 }
1143         }
1144
1145         if (mstm->disabled) {
1146                 if (!mstm->links)
1147                         nv50_outp_release(mstm->outp);
1148                 mstm->disabled = false;
1149         }
1150 }
1151
1152 static void
1153 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1154                             struct drm_connector *connector)
1155 {
1156         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1157         struct nv50_mstc *mstc = nv50_mstc(connector);
1158
1159         drm_connector_unregister(&mstc->connector);
1160
1161         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1162
1163         drm_connector_put(&mstc->connector);
1164 }
1165
1166 static void
1167 nv50_mstm_register_connector(struct drm_connector *connector)
1168 {
1169         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1170
1171         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1172
1173         drm_connector_register(connector);
1174 }
1175
1176 static struct drm_connector *
1177 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1178                         struct drm_dp_mst_port *port, const char *path)
1179 {
1180         struct nv50_mstm *mstm = nv50_mstm(mgr);
1181         struct nv50_mstc *mstc;
1182         int ret;
1183
1184         ret = nv50_mstc_new(mstm, port, path, &mstc);
1185         if (ret)
1186                 return NULL;
1187
1188         return &mstc->connector;
1189 }
1190
1191 static const struct drm_dp_mst_topology_cbs
1192 nv50_mstm = {
1193         .add_connector = nv50_mstm_add_connector,
1194         .register_connector = nv50_mstm_register_connector,
1195         .destroy_connector = nv50_mstm_destroy_connector,
1196 };
1197
1198 void
1199 nv50_mstm_service(struct nv50_mstm *mstm)
1200 {
1201         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1202         bool handled = true;
1203         int ret;
1204         u8 esi[8] = {};
1205
1206         if (!aux)
1207                 return;
1208
1209         while (handled) {
1210                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1211                 if (ret != 8) {
1212                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1213                         return;
1214                 }
1215
1216                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1217                 if (!handled)
1218                         break;
1219
1220                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1221         }
1222 }
1223
1224 void
1225 nv50_mstm_remove(struct nv50_mstm *mstm)
1226 {
1227         if (mstm)
1228                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1229 }
1230
1231 static int
1232 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1233 {
1234         struct nouveau_encoder *outp = mstm->outp;
1235         struct {
1236                 struct nv50_disp_mthd_v1 base;
1237                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1238         } args = {
1239                 .base.version = 1,
1240                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1241                 .base.hasht = outp->dcb->hasht,
1242                 .base.hashm = outp->dcb->hashm,
1243                 .mst.state = state,
1244         };
1245         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1246         struct nvif_object *disp = &drm->display->disp.object;
1247         int ret;
1248
1249         if (dpcd >= 0x12) {
1250                 /* Even if we're enabling MST, start with disabling the
1251                  * branching unit to clear any sink-side MST topology state
1252                  * that wasn't set by us
1253                  */
1254                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1255                 if (ret < 0)
1256                         return ret;
1257
1258                 if (state) {
1259                         /* Now, start initializing */
1260                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1261                                                  DP_MST_EN);
1262                         if (ret < 0)
1263                                 return ret;
1264                 }
1265         }
1266
1267         return nvif_mthd(disp, 0, &args, sizeof(args));
1268 }
1269
1270 int
1271 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1272 {
1273         struct drm_dp_aux *aux;
1274         int ret;
1275         bool old_state, new_state;
1276         u8 mstm_ctrl;
1277
1278         if (!mstm)
1279                 return 0;
1280
1281         mutex_lock(&mstm->mgr.lock);
1282
1283         old_state = mstm->mgr.mst_state;
1284         new_state = old_state;
1285         aux = mstm->mgr.aux;
1286
1287         if (old_state) {
1288                 /* Just check that the MST hub is still as we expect it */
1289                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1290                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1291                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1292                         new_state = false;
1293                 }
1294         } else if (dpcd[0] >= 0x12) {
1295                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1296                 if (ret < 0)
1297                         goto probe_error;
1298
1299                 if (!(dpcd[1] & DP_MST_CAP))
1300                         dpcd[0] = 0x11;
1301                 else
1302                         new_state = allow;
1303         }
1304
1305         if (new_state == old_state) {
1306                 mutex_unlock(&mstm->mgr.lock);
1307                 return new_state;
1308         }
1309
1310         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1311         if (ret)
1312                 goto probe_error;
1313
1314         mutex_unlock(&mstm->mgr.lock);
1315
1316         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1317         if (ret)
1318                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1319
1320         return new_state;
1321
1322 probe_error:
1323         mutex_unlock(&mstm->mgr.lock);
1324         return ret;
1325 }
1326
1327 static void
1328 nv50_mstm_fini(struct nv50_mstm *mstm)
1329 {
1330         if (mstm && mstm->mgr.mst_state)
1331                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1332 }
1333
1334 static void
1335 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1336 {
1337         int ret;
1338
1339         if (!mstm || !mstm->mgr.mst_state)
1340                 return;
1341
1342         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1343         if (ret == -1) {
1344                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1345                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1346         }
1347 }
1348
1349 static void
1350 nv50_mstm_del(struct nv50_mstm **pmstm)
1351 {
1352         struct nv50_mstm *mstm = *pmstm;
1353         if (mstm) {
1354                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1355                 kfree(*pmstm);
1356                 *pmstm = NULL;
1357         }
1358 }
1359
1360 static int
1361 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1362               int conn_base_id, struct nv50_mstm **pmstm)
1363 {
1364         const int max_payloads = hweight8(outp->dcb->heads);
1365         struct drm_device *dev = outp->base.base.dev;
1366         struct nv50_mstm *mstm;
1367         int ret;
1368         u8 dpcd;
1369
1370         /* This is a workaround for some monitors not functioning
1371          * correctly in MST mode on initial module load.  I think
1372          * some bad interaction with the VBIOS may be responsible.
1373          *
1374          * A good ol' off and on again seems to work here ;)
1375          */
1376         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1377         if (ret >= 0 && dpcd >= 0x12)
1378                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1379
1380         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1381                 return -ENOMEM;
1382         mstm->outp = outp;
1383         mstm->mgr.cbs = &nv50_mstm;
1384
1385         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1386                                            max_payloads, conn_base_id);
1387         if (ret)
1388                 return ret;
1389
1390         return 0;
1391 }
1392
1393 /******************************************************************************
1394  * SOR
1395  *****************************************************************************/
1396 static void
1397 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1398                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1399 {
1400         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1401         struct nv50_core *core = disp->core;
1402
1403         if (!asyh) {
1404                 nv_encoder->ctrl &= ~BIT(head);
1405                 if (!(nv_encoder->ctrl & 0x0000000f))
1406                         nv_encoder->ctrl = 0;
1407         } else {
1408                 nv_encoder->ctrl |= proto << 8;
1409                 nv_encoder->ctrl |= BIT(head);
1410                 asyh->or.depth = depth;
1411         }
1412
1413         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1414 }
1415
1416 static void
1417 nv50_sor_disable(struct drm_encoder *encoder)
1418 {
1419         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1420         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1421
1422         nv_encoder->crtc = NULL;
1423
1424         if (nv_crtc) {
1425                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1426                 u8 pwr;
1427
1428                 if (aux) {
1429                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1430                         if (ret == 0) {
1431                                 pwr &= ~DP_SET_POWER_MASK;
1432                                 pwr |=  DP_SET_POWER_D3;
1433                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1434                         }
1435                 }
1436
1437                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1438                 nv50_audio_disable(encoder, nv_crtc);
1439                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1440                 nv50_outp_release(nv_encoder);
1441         }
1442 }
1443
1444 static void
1445 nv50_sor_enable(struct drm_encoder *encoder)
1446 {
1447         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1448         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1449         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1450         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1451         struct {
1452                 struct nv50_disp_mthd_v1 base;
1453                 struct nv50_disp_sor_lvds_script_v0 lvds;
1454         } lvds = {
1455                 .base.version = 1,
1456                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1457                 .base.hasht   = nv_encoder->dcb->hasht,
1458                 .base.hashm   = nv_encoder->dcb->hashm,
1459         };
1460         struct nv50_disp *disp = nv50_disp(encoder->dev);
1461         struct drm_device *dev = encoder->dev;
1462         struct nouveau_drm *drm = nouveau_drm(dev);
1463         struct nouveau_connector *nv_connector;
1464         struct nvbios *bios = &drm->vbios;
1465         u8 proto = 0xf;
1466         u8 depth = 0x0;
1467
1468         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1469         nv_encoder->crtc = encoder->crtc;
1470         nv50_outp_acquire(nv_encoder);
1471
1472         switch (nv_encoder->dcb->type) {
1473         case DCB_OUTPUT_TMDS:
1474                 if (nv_encoder->link & 1) {
1475                         proto = 0x1;
1476                         /* Only enable dual-link if:
1477                          *  - Need to (i.e. rate > 165MHz)
1478                          *  - DCB says we can
1479                          *  - Not an HDMI monitor, since there's no dual-link
1480                          *    on HDMI.
1481                          */
1482                         if (mode->clock >= 165000 &&
1483                             nv_encoder->dcb->duallink_possible &&
1484                             !drm_detect_hdmi_monitor(nv_connector->edid))
1485                                 proto |= 0x4;
1486                 } else {
1487                         proto = 0x2;
1488                 }
1489
1490                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1491                 break;
1492         case DCB_OUTPUT_LVDS:
1493                 proto = 0x0;
1494
1495                 if (bios->fp_no_ddc) {
1496                         if (bios->fp.dual_link)
1497                                 lvds.lvds.script |= 0x0100;
1498                         if (bios->fp.if_is_24bit)
1499                                 lvds.lvds.script |= 0x0200;
1500                 } else {
1501                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1502                                 if (((u8 *)nv_connector->edid)[121] == 2)
1503                                         lvds.lvds.script |= 0x0100;
1504                         } else
1505                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1506                                 lvds.lvds.script |= 0x0100;
1507                         }
1508
1509                         if (lvds.lvds.script & 0x0100) {
1510                                 if (bios->fp.strapless_is_24bit & 2)
1511                                         lvds.lvds.script |= 0x0200;
1512                         } else {
1513                                 if (bios->fp.strapless_is_24bit & 1)
1514                                         lvds.lvds.script |= 0x0200;
1515                         }
1516
1517                         if (asyh->or.bpc == 8)
1518                                 lvds.lvds.script |= 0x0200;
1519                 }
1520
1521                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1522                 break;
1523         case DCB_OUTPUT_DP:
1524                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1525
1526                 if (nv_encoder->link & 1)
1527                         proto = 0x8;
1528                 else
1529                         proto = 0x9;
1530
1531                 nv50_audio_enable(encoder, mode);
1532                 break;
1533         default:
1534                 BUG();
1535                 break;
1536         }
1537
1538         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1539 }
1540
1541 static const struct drm_encoder_helper_funcs
1542 nv50_sor_help = {
1543         .atomic_check = nv50_outp_atomic_check,
1544         .enable = nv50_sor_enable,
1545         .disable = nv50_sor_disable,
1546 };
1547
1548 static void
1549 nv50_sor_destroy(struct drm_encoder *encoder)
1550 {
1551         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1552         nv50_mstm_del(&nv_encoder->dp.mstm);
1553         drm_encoder_cleanup(encoder);
1554         kfree(encoder);
1555 }
1556
1557 static const struct drm_encoder_funcs
1558 nv50_sor_func = {
1559         .destroy = nv50_sor_destroy,
1560 };
1561
1562 static bool nv50_has_mst(struct nouveau_drm *drm)
1563 {
1564         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1565         u32 data;
1566         u8 ver, hdr, cnt, len;
1567
1568         data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1569         return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1570 }
1571
1572 static int
1573 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1574 {
1575         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1576         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1577         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1578         struct nouveau_encoder *nv_encoder;
1579         struct drm_encoder *encoder;
1580         int type, ret;
1581
1582         switch (dcbe->type) {
1583         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1584         case DCB_OUTPUT_TMDS:
1585         case DCB_OUTPUT_DP:
1586         default:
1587                 type = DRM_MODE_ENCODER_TMDS;
1588                 break;
1589         }
1590
1591         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1592         if (!nv_encoder)
1593                 return -ENOMEM;
1594         nv_encoder->dcb = dcbe;
1595         nv_encoder->update = nv50_sor_update;
1596
1597         encoder = to_drm_encoder(nv_encoder);
1598         encoder->possible_crtcs = dcbe->heads;
1599         encoder->possible_clones = 0;
1600         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1601                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1602         drm_encoder_helper_add(encoder, &nv50_sor_help);
1603
1604         drm_connector_attach_encoder(connector, encoder);
1605
1606         if (dcbe->type == DCB_OUTPUT_DP) {
1607                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1608                 struct nvkm_i2c_aux *aux =
1609                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1610                 if (aux) {
1611                         if (disp->disp->object.oclass < GF110_DISP) {
1612                                 /* HW has no support for address-only
1613                                  * transactions, so we're required to
1614                                  * use custom I2C-over-AUX code.
1615                                  */
1616                                 nv_encoder->i2c = &aux->i2c;
1617                         } else {
1618                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1619                         }
1620                         nv_encoder->aux = aux;
1621                 }
1622
1623                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1624                     nv50_has_mst(drm)) {
1625                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1626                                             16, nv_connector->base.base.id,
1627                                             &nv_encoder->dp.mstm);
1628                         if (ret)
1629                                 return ret;
1630                 }
1631         } else {
1632                 struct nvkm_i2c_bus *bus =
1633                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1634                 if (bus)
1635                         nv_encoder->i2c = &bus->i2c;
1636         }
1637
1638         return 0;
1639 }
1640
1641 /******************************************************************************
1642  * PIOR
1643  *****************************************************************************/
1644 static int
1645 nv50_pior_atomic_check(struct drm_encoder *encoder,
1646                        struct drm_crtc_state *crtc_state,
1647                        struct drm_connector_state *conn_state)
1648 {
1649         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1650         if (ret)
1651                 return ret;
1652         crtc_state->adjusted_mode.clock *= 2;
1653         return 0;
1654 }
1655
1656 static void
1657 nv50_pior_disable(struct drm_encoder *encoder)
1658 {
1659         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1660         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1661         if (nv_encoder->crtc)
1662                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1663         nv_encoder->crtc = NULL;
1664         nv50_outp_release(nv_encoder);
1665 }
1666
1667 static void
1668 nv50_pior_enable(struct drm_encoder *encoder)
1669 {
1670         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1671         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1672         struct nouveau_connector *nv_connector;
1673         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1674         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1675         u8 owner = 1 << nv_crtc->index;
1676         u8 proto;
1677
1678         nv50_outp_acquire(nv_encoder);
1679
1680         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1681         switch (asyh->or.bpc) {
1682         case 10: asyh->or.depth = 0x6; break;
1683         case  8: asyh->or.depth = 0x5; break;
1684         case  6: asyh->or.depth = 0x2; break;
1685         default: asyh->or.depth = 0x0; break;
1686         }
1687
1688         switch (nv_encoder->dcb->type) {
1689         case DCB_OUTPUT_TMDS:
1690         case DCB_OUTPUT_DP:
1691                 proto = 0x0;
1692                 break;
1693         default:
1694                 BUG();
1695                 break;
1696         }
1697
1698         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1699         nv_encoder->crtc = encoder->crtc;
1700 }
1701
1702 static const struct drm_encoder_helper_funcs
1703 nv50_pior_help = {
1704         .atomic_check = nv50_pior_atomic_check,
1705         .enable = nv50_pior_enable,
1706         .disable = nv50_pior_disable,
1707 };
1708
1709 static void
1710 nv50_pior_destroy(struct drm_encoder *encoder)
1711 {
1712         drm_encoder_cleanup(encoder);
1713         kfree(encoder);
1714 }
1715
1716 static const struct drm_encoder_funcs
1717 nv50_pior_func = {
1718         .destroy = nv50_pior_destroy,
1719 };
1720
1721 static int
1722 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1723 {
1724         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1725         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1726         struct nvkm_i2c_bus *bus = NULL;
1727         struct nvkm_i2c_aux *aux = NULL;
1728         struct i2c_adapter *ddc;
1729         struct nouveau_encoder *nv_encoder;
1730         struct drm_encoder *encoder;
1731         int type;
1732
1733         switch (dcbe->type) {
1734         case DCB_OUTPUT_TMDS:
1735                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1736                 ddc  = bus ? &bus->i2c : NULL;
1737                 type = DRM_MODE_ENCODER_TMDS;
1738                 break;
1739         case DCB_OUTPUT_DP:
1740                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1741                 ddc  = aux ? &aux->i2c : NULL;
1742                 type = DRM_MODE_ENCODER_TMDS;
1743                 break;
1744         default:
1745                 return -ENODEV;
1746         }
1747
1748         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1749         if (!nv_encoder)
1750                 return -ENOMEM;
1751         nv_encoder->dcb = dcbe;
1752         nv_encoder->i2c = ddc;
1753         nv_encoder->aux = aux;
1754
1755         encoder = to_drm_encoder(nv_encoder);
1756         encoder->possible_crtcs = dcbe->heads;
1757         encoder->possible_clones = 0;
1758         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1759                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1760         drm_encoder_helper_add(encoder, &nv50_pior_help);
1761
1762         drm_connector_attach_encoder(connector, encoder);
1763         return 0;
1764 }
1765
1766 /******************************************************************************
1767  * Atomic
1768  *****************************************************************************/
1769
1770 static void
1771 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1772 {
1773         struct nouveau_drm *drm = nouveau_drm(state->dev);
1774         struct nv50_disp *disp = nv50_disp(drm->dev);
1775         struct nv50_core *core = disp->core;
1776         struct nv50_mstm *mstm;
1777         struct drm_encoder *encoder;
1778
1779         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1780
1781         drm_for_each_encoder(encoder, drm->dev) {
1782                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1783                         mstm = nouveau_encoder(encoder)->dp.mstm;
1784                         if (mstm && mstm->modified)
1785                                 nv50_mstm_prepare(mstm);
1786                 }
1787         }
1788
1789         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1790         core->func->update(core, interlock, true);
1791         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1792                                        disp->core->chan.base.device))
1793                 NV_ERROR(drm, "core notifier timeout\n");
1794
1795         drm_for_each_encoder(encoder, drm->dev) {
1796                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1797                         mstm = nouveau_encoder(encoder)->dp.mstm;
1798                         if (mstm && mstm->modified)
1799                                 nv50_mstm_cleanup(mstm);
1800                 }
1801         }
1802 }
1803
1804 static void
1805 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1806 {
1807         struct drm_plane_state *new_plane_state;
1808         struct drm_plane *plane;
1809         int i;
1810
1811         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1812                 struct nv50_wndw *wndw = nv50_wndw(plane);
1813                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1814                         if (wndw->func->update)
1815                                 wndw->func->update(wndw, interlock);
1816                 }
1817         }
1818 }
1819
1820 static void
1821 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1822 {
1823         struct drm_device *dev = state->dev;
1824         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1825         struct drm_crtc *crtc;
1826         struct drm_plane_state *new_plane_state;
1827         struct drm_plane *plane;
1828         struct nouveau_drm *drm = nouveau_drm(dev);
1829         struct nv50_disp *disp = nv50_disp(dev);
1830         struct nv50_atom *atom = nv50_atom(state);
1831         struct nv50_outp_atom *outp, *outt;
1832         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1833         int i;
1834
1835         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1836         drm_atomic_helper_wait_for_fences(dev, state, false);
1837         drm_atomic_helper_wait_for_dependencies(state);
1838         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1839
1840         if (atom->lock_core)
1841                 mutex_lock(&disp->mutex);
1842
1843         /* Disable head(s). */
1844         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1845                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1846                 struct nv50_head *head = nv50_head(crtc);
1847
1848                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1849                           asyh->clr.mask, asyh->set.mask);
1850
1851                 if (old_crtc_state->active && !new_crtc_state->active) {
1852                         pm_runtime_put_noidle(dev->dev);
1853                         drm_crtc_vblank_off(crtc);
1854                 }
1855
1856                 if (asyh->clr.mask) {
1857                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1858                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1859                 }
1860         }
1861
1862         /* Disable plane(s). */
1863         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1864                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1865                 struct nv50_wndw *wndw = nv50_wndw(plane);
1866
1867                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1868                           asyw->clr.mask, asyw->set.mask);
1869                 if (!asyw->clr.mask)
1870                         continue;
1871
1872                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1873         }
1874
1875         /* Disable output path(s). */
1876         list_for_each_entry(outp, &atom->outp, head) {
1877                 const struct drm_encoder_helper_funcs *help;
1878                 struct drm_encoder *encoder;
1879
1880                 encoder = outp->encoder;
1881                 help = encoder->helper_private;
1882
1883                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1884                           outp->clr.mask, outp->set.mask);
1885
1886                 if (outp->clr.mask) {
1887                         help->disable(encoder);
1888                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1889                         if (outp->flush_disable) {
1890                                 nv50_disp_atomic_commit_wndw(state, interlock);
1891                                 nv50_disp_atomic_commit_core(state, interlock);
1892                                 memset(interlock, 0x00, sizeof(interlock));
1893                         }
1894                 }
1895         }
1896
1897         /* Flush disable. */
1898         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1899                 if (atom->flush_disable) {
1900                         nv50_disp_atomic_commit_wndw(state, interlock);
1901                         nv50_disp_atomic_commit_core(state, interlock);
1902                         memset(interlock, 0x00, sizeof(interlock));
1903                 }
1904         }
1905
1906         /* Update output path(s). */
1907         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1908                 const struct drm_encoder_helper_funcs *help;
1909                 struct drm_encoder *encoder;
1910
1911                 encoder = outp->encoder;
1912                 help = encoder->helper_private;
1913
1914                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1915                           outp->set.mask, outp->clr.mask);
1916
1917                 if (outp->set.mask) {
1918                         help->enable(encoder);
1919                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1920                 }
1921
1922                 list_del(&outp->head);
1923                 kfree(outp);
1924         }
1925
1926         /* Update head(s). */
1927         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1928                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1929                 struct nv50_head *head = nv50_head(crtc);
1930
1931                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1932                           asyh->set.mask, asyh->clr.mask);
1933
1934                 if (asyh->set.mask) {
1935                         nv50_head_flush_set(head, asyh);
1936                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1937                 }
1938
1939                 if (new_crtc_state->active) {
1940                         if (!old_crtc_state->active) {
1941                                 drm_crtc_vblank_on(crtc);
1942                                 pm_runtime_get_noresume(dev->dev);
1943                         }
1944                         if (new_crtc_state->event)
1945                                 drm_crtc_vblank_get(crtc);
1946                 }
1947         }
1948
1949         /* Update plane(s). */
1950         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1951                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1952                 struct nv50_wndw *wndw = nv50_wndw(plane);
1953
1954                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1955                           asyw->set.mask, asyw->clr.mask);
1956                 if ( !asyw->set.mask &&
1957                     (!asyw->clr.mask || atom->flush_disable))
1958                         continue;
1959
1960                 nv50_wndw_flush_set(wndw, interlock, asyw);
1961         }
1962
1963         /* Flush update. */
1964         nv50_disp_atomic_commit_wndw(state, interlock);
1965
1966         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1967                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1968                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1969                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1970                     !atom->state.legacy_cursor_update)
1971                         nv50_disp_atomic_commit_core(state, interlock);
1972                 else
1973                         disp->core->func->update(disp->core, interlock, false);
1974         }
1975
1976         if (atom->lock_core)
1977                 mutex_unlock(&disp->mutex);
1978
1979         /* Wait for HW to signal completion. */
1980         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1981                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1982                 struct nv50_wndw *wndw = nv50_wndw(plane);
1983                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1984                 if (ret)
1985                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1986         }
1987
1988         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1989                 if (new_crtc_state->event) {
1990                         unsigned long flags;
1991                         /* Get correct count/ts if racing with vblank irq */
1992                         if (new_crtc_state->active)
1993                                 drm_crtc_accurate_vblank_count(crtc);
1994                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1995                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1996                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1997
1998                         new_crtc_state->event = NULL;
1999                         if (new_crtc_state->active)
2000                                 drm_crtc_vblank_put(crtc);
2001                 }
2002         }
2003
2004         drm_atomic_helper_commit_hw_done(state);
2005         drm_atomic_helper_cleanup_planes(dev, state);
2006         drm_atomic_helper_commit_cleanup_done(state);
2007         drm_atomic_state_put(state);
2008
2009         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2010         pm_runtime_mark_last_busy(dev->dev);
2011         pm_runtime_put_autosuspend(dev->dev);
2012 }
2013
2014 static void
2015 nv50_disp_atomic_commit_work(struct work_struct *work)
2016 {
2017         struct drm_atomic_state *state =
2018                 container_of(work, typeof(*state), commit_work);
2019         nv50_disp_atomic_commit_tail(state);
2020 }
2021
2022 static int
2023 nv50_disp_atomic_commit(struct drm_device *dev,
2024                         struct drm_atomic_state *state, bool nonblock)
2025 {
2026         struct drm_plane_state *new_plane_state;
2027         struct drm_plane *plane;
2028         int ret, i;
2029
2030         ret = pm_runtime_get_sync(dev->dev);
2031         if (ret < 0 && ret != -EACCES)
2032                 return ret;
2033
2034         ret = drm_atomic_helper_setup_commit(state, nonblock);
2035         if (ret)
2036                 goto done;
2037
2038         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2039
2040         ret = drm_atomic_helper_prepare_planes(dev, state);
2041         if (ret)
2042                 goto done;
2043
2044         if (!nonblock) {
2045                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2046                 if (ret)
2047                         goto err_cleanup;
2048         }
2049
2050         ret = drm_atomic_helper_swap_state(state, true);
2051         if (ret)
2052                 goto err_cleanup;
2053
2054         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2055                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2056                 struct nv50_wndw *wndw = nv50_wndw(plane);
2057
2058                 if (asyw->set.image)
2059                         nv50_wndw_ntfy_enable(wndw, asyw);
2060         }
2061
2062         drm_atomic_state_get(state);
2063
2064         /*
2065          * Grab another RPM ref for the commit tail, which will release the
2066          * ref when it's finished
2067          */
2068         pm_runtime_get_noresume(dev->dev);
2069
2070         if (nonblock)
2071                 queue_work(system_unbound_wq, &state->commit_work);
2072         else
2073                 nv50_disp_atomic_commit_tail(state);
2074
2075 err_cleanup:
2076         if (ret)
2077                 drm_atomic_helper_cleanup_planes(dev, state);
2078 done:
2079         pm_runtime_put_autosuspend(dev->dev);
2080         return ret;
2081 }
2082
2083 static struct nv50_outp_atom *
2084 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2085 {
2086         struct nv50_outp_atom *outp;
2087
2088         list_for_each_entry(outp, &atom->outp, head) {
2089                 if (outp->encoder == encoder)
2090                         return outp;
2091         }
2092
2093         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2094         if (!outp)
2095                 return ERR_PTR(-ENOMEM);
2096
2097         list_add(&outp->head, &atom->outp);
2098         outp->encoder = encoder;
2099         return outp;
2100 }
2101
2102 static int
2103 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2104                                 struct drm_connector_state *old_connector_state)
2105 {
2106         struct drm_encoder *encoder = old_connector_state->best_encoder;
2107         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2108         struct drm_crtc *crtc;
2109         struct nv50_outp_atom *outp;
2110
2111         if (!(crtc = old_connector_state->crtc))
2112                 return 0;
2113
2114         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2115         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2116         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2117                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2118                 if (IS_ERR(outp))
2119                         return PTR_ERR(outp);
2120
2121                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2122                         outp->flush_disable = true;
2123                         atom->flush_disable = true;
2124                 }
2125                 outp->clr.ctrl = true;
2126                 atom->lock_core = true;
2127         }
2128
2129         return 0;
2130 }
2131
2132 static int
2133 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2134                                 struct drm_connector_state *connector_state)
2135 {
2136         struct drm_encoder *encoder = connector_state->best_encoder;
2137         struct drm_crtc_state *new_crtc_state;
2138         struct drm_crtc *crtc;
2139         struct nv50_outp_atom *outp;
2140
2141         if (!(crtc = connector_state->crtc))
2142                 return 0;
2143
2144         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2145         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2146                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2147                 if (IS_ERR(outp))
2148                         return PTR_ERR(outp);
2149
2150                 outp->set.ctrl = true;
2151                 atom->lock_core = true;
2152         }
2153
2154         return 0;
2155 }
2156
2157 static int
2158 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2159 {
2160         struct nv50_atom *atom = nv50_atom(state);
2161         struct drm_connector_state *old_connector_state, *new_connector_state;
2162         struct drm_connector *connector;
2163         struct drm_crtc_state *new_crtc_state;
2164         struct drm_crtc *crtc;
2165         int ret, i;
2166
2167         /* We need to handle colour management on a per-plane basis. */
2168         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2169                 if (new_crtc_state->color_mgmt_changed) {
2170                         ret = drm_atomic_add_affected_planes(state, crtc);
2171                         if (ret)
2172                                 return ret;
2173                 }
2174         }
2175
2176         ret = drm_atomic_helper_check(dev, state);
2177         if (ret)
2178                 return ret;
2179
2180         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2181                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2182                 if (ret)
2183                         return ret;
2184
2185                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2186                 if (ret)
2187                         return ret;
2188         }
2189
2190         ret = drm_dp_mst_atomic_check(state);
2191         if (ret)
2192                 return ret;
2193
2194         return 0;
2195 }
2196
2197 static void
2198 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2199 {
2200         struct nv50_atom *atom = nv50_atom(state);
2201         struct nv50_outp_atom *outp, *outt;
2202
2203         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2204                 list_del(&outp->head);
2205                 kfree(outp);
2206         }
2207
2208         drm_atomic_state_default_clear(state);
2209 }
2210
2211 static void
2212 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2213 {
2214         struct nv50_atom *atom = nv50_atom(state);
2215         drm_atomic_state_default_release(&atom->state);
2216         kfree(atom);
2217 }
2218
2219 static struct drm_atomic_state *
2220 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2221 {
2222         struct nv50_atom *atom;
2223         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2224             drm_atomic_state_init(dev, &atom->state) < 0) {
2225                 kfree(atom);
2226                 return NULL;
2227         }
2228         INIT_LIST_HEAD(&atom->outp);
2229         return &atom->state;
2230 }
2231
2232 static const struct drm_mode_config_funcs
2233 nv50_disp_func = {
2234         .fb_create = nouveau_user_framebuffer_create,
2235         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2236         .atomic_check = nv50_disp_atomic_check,
2237         .atomic_commit = nv50_disp_atomic_commit,
2238         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2239         .atomic_state_clear = nv50_disp_atomic_state_clear,
2240         .atomic_state_free = nv50_disp_atomic_state_free,
2241 };
2242
2243 /******************************************************************************
2244  * Init
2245  *****************************************************************************/
2246
2247 static void
2248 nv50_display_fini(struct drm_device *dev, bool suspend)
2249 {
2250         struct nouveau_encoder *nv_encoder;
2251         struct drm_encoder *encoder;
2252         struct drm_plane *plane;
2253
2254         drm_for_each_plane(plane, dev) {
2255                 struct nv50_wndw *wndw = nv50_wndw(plane);
2256                 if (plane->funcs != &nv50_wndw)
2257                         continue;
2258                 nv50_wndw_fini(wndw);
2259         }
2260
2261         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2262                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2263                         nv_encoder = nouveau_encoder(encoder);
2264                         nv50_mstm_fini(nv_encoder->dp.mstm);
2265                 }
2266         }
2267 }
2268
2269 static int
2270 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2271 {
2272         struct nv50_core *core = nv50_disp(dev)->core;
2273         struct drm_encoder *encoder;
2274         struct drm_plane *plane;
2275
2276         core->func->init(core);
2277
2278         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2279                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2280                         struct nouveau_encoder *nv_encoder =
2281                                 nouveau_encoder(encoder);
2282                         nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2283                 }
2284         }
2285
2286         drm_for_each_plane(plane, dev) {
2287                 struct nv50_wndw *wndw = nv50_wndw(plane);
2288                 if (plane->funcs != &nv50_wndw)
2289                         continue;
2290                 nv50_wndw_init(wndw);
2291         }
2292
2293         return 0;
2294 }
2295
2296 static void
2297 nv50_display_destroy(struct drm_device *dev)
2298 {
2299         struct nv50_disp *disp = nv50_disp(dev);
2300
2301         nv50_core_del(&disp->core);
2302
2303         nouveau_bo_unmap(disp->sync);
2304         if (disp->sync)
2305                 nouveau_bo_unpin(disp->sync);
2306         nouveau_bo_ref(NULL, &disp->sync);
2307
2308         nouveau_display(dev)->priv = NULL;
2309         kfree(disp);
2310 }
2311
2312 int
2313 nv50_display_create(struct drm_device *dev)
2314 {
2315         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2316         struct nouveau_drm *drm = nouveau_drm(dev);
2317         struct dcb_table *dcb = &drm->vbios.dcb;
2318         struct drm_connector *connector, *tmp;
2319         struct nv50_disp *disp;
2320         struct dcb_output *dcbe;
2321         int crtcs, ret, i;
2322         bool has_mst = nv50_has_mst(drm);
2323
2324         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2325         if (!disp)
2326                 return -ENOMEM;
2327
2328         mutex_init(&disp->mutex);
2329
2330         nouveau_display(dev)->priv = disp;
2331         nouveau_display(dev)->dtor = nv50_display_destroy;
2332         nouveau_display(dev)->init = nv50_display_init;
2333         nouveau_display(dev)->fini = nv50_display_fini;
2334         disp->disp = &nouveau_display(dev)->disp;
2335         dev->mode_config.funcs = &nv50_disp_func;
2336         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2337         dev->mode_config.normalize_zpos = true;
2338
2339         /* small shared memory area we use for notifiers and semaphores */
2340         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2341                              0, 0x0000, NULL, NULL, &disp->sync);
2342         if (!ret) {
2343                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2344                 if (!ret) {
2345                         ret = nouveau_bo_map(disp->sync);
2346                         if (ret)
2347                                 nouveau_bo_unpin(disp->sync);
2348                 }
2349                 if (ret)
2350                         nouveau_bo_ref(NULL, &disp->sync);
2351         }
2352
2353         if (ret)
2354                 goto out;
2355
2356         /* allocate master evo channel */
2357         ret = nv50_core_new(drm, &disp->core);
2358         if (ret)
2359                 goto out;
2360
2361         /* create crtc objects to represent the hw heads */
2362         if (disp->disp->object.oclass >= GV100_DISP)
2363                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2364         else
2365         if (disp->disp->object.oclass >= GF110_DISP)
2366                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2367         else
2368                 crtcs = 0x3;
2369
2370         for (i = 0; i < fls(crtcs); i++) {
2371                 struct nv50_head *head;
2372
2373                 if (!(crtcs & (1 << i)))
2374                         continue;
2375
2376                 head = nv50_head_create(dev, i);
2377                 if (IS_ERR(head)) {
2378                         ret = PTR_ERR(head);
2379                         goto out;
2380                 }
2381
2382                 if (has_mst) {
2383                         head->msto = nv50_msto_new(dev, head, i);
2384                         if (IS_ERR(head->msto)) {
2385                                 ret = PTR_ERR(head->msto);
2386                                 head->msto = NULL;
2387                                 goto out;
2388                         }
2389                 }
2390         }
2391
2392         /* create encoder/connector objects based on VBIOS DCB table */
2393         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2394                 connector = nouveau_connector_create(dev, dcbe);
2395                 if (IS_ERR(connector))
2396                         continue;
2397
2398                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2399                         switch (dcbe->type) {
2400                         case DCB_OUTPUT_TMDS:
2401                         case DCB_OUTPUT_LVDS:
2402                         case DCB_OUTPUT_DP:
2403                                 ret = nv50_sor_create(connector, dcbe);
2404                                 break;
2405                         case DCB_OUTPUT_ANALOG:
2406                                 ret = nv50_dac_create(connector, dcbe);
2407                                 break;
2408                         default:
2409                                 ret = -ENODEV;
2410                                 break;
2411                         }
2412                 } else {
2413                         ret = nv50_pior_create(connector, dcbe);
2414                 }
2415
2416                 if (ret) {
2417                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2418                                      dcbe->location, dcbe->type,
2419                                      ffs(dcbe->or) - 1, ret);
2420                         ret = 0;
2421                 }
2422         }
2423
2424         /* cull any connectors we created that don't have an encoder */
2425         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2426                 if (connector->possible_encoders)
2427                         continue;
2428
2429                 NV_WARN(drm, "%s has no encoders, removing\n",
2430                         connector->name);
2431                 connector->funcs->destroy(connector);
2432         }
2433
2434         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2435         dev->vblank_disable_immediate = true;
2436
2437 out:
2438         if (ret)
2439                 nv50_display_destroy(dev);
2440         return ret;
2441 }