drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_edid.h>
  40
  41 #include <nvif/class.h>
  42 #include <nvif/cl0002.h>
  43 #include <nvif/cl5070.h>
  44 #include <nvif/cl507d.h>
  45 #include <nvif/event.h>
  46
  47 #include "nouveau_drv.h"
  48 #include "nouveau_dma.h"
  49 #include "nouveau_gem.h"
  50 #include "nouveau_connector.h"
  51 #include "nouveau_encoder.h"
  52 #include "nouveau_fence.h"
  53 #include "nouveau_fbcon.h"
  54
  55 #include <subdev/bios/dp.h>
  56
  57 /******************************************************************************
  58  * Atomic state
  59  *****************************************************************************/
  60
  61 struct nv50_outp_atom {
  62         struct list_head head;
  63
  64         struct drm_encoder *encoder;
  65         bool flush_disable;
  66
  67         union nv50_outp_atom_mask {
  68                 struct {
  69                         bool ctrl:1;
  70                 };
  71                 u8 mask;
  72         } set, clr;
  73 };
  74
  75 /******************************************************************************
  76  * EVO channel
  77  *****************************************************************************/
  78
  79 static int
  80 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  81                  const s32 *oclass, u8 head, void *data, u32 size,
  82                  struct nv50_chan *chan)
  83 {
  84         struct nvif_sclass *sclass;
  85         int ret, i, n;
  86
  87         chan->device = device;
  88
  89         ret = n = nvif_object_sclass_get(disp, &sclass);
  90         if (ret < 0)
  91                 return ret;
  92
  93         while (oclass[0]) {
  94                 for (i = 0; i < n; i++) {
  95                         if (sclass[i].oclass == oclass[0]) {
  96                                 ret = nvif_object_init(disp, 0, oclass[0],
  97                                                        data, size, &chan->user);
  98                                 if (ret == 0)
  99                                         nvif_object_map(&chan->user, NULL, 0);
 100                                 nvif_object_sclass_put(&sclass);
 101                                 return ret;
 102                         }
 103                 }
 104                 oclass++;
 105         }
 106
 107         nvif_object_sclass_put(&sclass);
 108         return -ENOSYS;
 109 }
 110
 111 static void
 112 nv50_chan_destroy(struct nv50_chan *chan)
 113 {
 114         nvif_object_fini(&chan->user);
 115 }
 116
 117 /******************************************************************************
 118  * DMA EVO channel
 119  *****************************************************************************/
 120
 121 void
 122 nv50_dmac_destroy(struct nv50_dmac *dmac)
 123 {
 124         nvif_object_fini(&dmac->vram);
 125         nvif_object_fini(&dmac->sync);
 126
 127         nv50_chan_destroy(&dmac->base);
 128
 129         nvif_mem_fini(&dmac->push);
 130 }
 131
 132 int
 133 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 134                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 135                  struct nv50_dmac *dmac)
 136 {
 137         struct nouveau_cli *cli = (void *)device->object.client;
 138         struct nv50_disp_core_channel_dma_v0 *args = data;
 139         u8 type = NVIF_MEM_COHERENT;
 140         int ret;
 141
 142         mutex_init(&dmac->lock);
 143
 144         /* Pascal added support for 47-bit physical addresses, but some
 145          * parts of EVO still only accept 40-bit PAs.
 146          *
 147          * To avoid issues on systems with large amounts of RAM, and on
 148          * systems where an IOMMU maps pages at a high address, we need
 149          * to allocate push buffers in VRAM instead.
 150          *
 151          * This appears to match NVIDIA's behaviour on Pascal.
 152          */
 153         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 154                 type |= NVIF_MEM_VRAM;
 155
 156         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 157         if (ret)
 158                 return ret;
 159
 160         dmac->ptr = dmac->push.object.map.ptr;
 161
 162         args->pushbuf = nvif_handle(&dmac->push.object);
 163
 164         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 165                                &dmac->base);
 166         if (ret)
 167                 return ret;
 168
 169         if (!syncbuf)
 170                 return 0;
 171
 172         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 173                                &(struct nv_dma_v0) {
 174                                         .target = NV_DMA_V0_TARGET_VRAM,
 175                                         .access = NV_DMA_V0_ACCESS_RDWR,
 176                                         .start = syncbuf + 0x0000,
 177                                         .limit = syncbuf + 0x0fff,
 178                                }, sizeof(struct nv_dma_v0),
 179                                &dmac->sync);
 180         if (ret)
 181                 return ret;
 182
 183         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 184                                &(struct nv_dma_v0) {
 185                                         .target = NV_DMA_V0_TARGET_VRAM,
 186                                         .access = NV_DMA_V0_ACCESS_RDWR,
 187                                         .start = 0,
 188                                         .limit = device->info.ram_user - 1,
 189                                }, sizeof(struct nv_dma_v0),
 190                                &dmac->vram);
 191         if (ret)
 192                 return ret;
 193
 194         return ret;
 195 }
 196
 197 /******************************************************************************
 198  * EVO channel helpers
 199  *****************************************************************************/
 200 u32 *
 201 evo_wait(struct nv50_dmac *evoc, int nr)
 202 {
 203         struct nv50_dmac *dmac = evoc;
 204         struct nvif_device *device = dmac->base.device;
 205         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 206
 207         mutex_lock(&dmac->lock);
 208         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 209                 dmac->ptr[put] = 0x20000000;
 210
 211                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 212                 if (nvif_msec(device, 2000,
 213                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 214                                 break;
 215                 ) < 0) {
 216                         mutex_unlock(&dmac->lock);
 217                         pr_err("nouveau: evo channel stalled\n");
 218                         return NULL;
 219                 }
 220
 221                 put = 0;
 222         }
 223
 224         return dmac->ptr + put;
 225 }
 226
 227 void
 228 evo_kick(u32 *push, struct nv50_dmac *evoc)
 229 {
 230         struct nv50_dmac *dmac = evoc;
 231
 232         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 233          * writes have been flushed right through to VRAM before writing PUT.
 234          */
 235         if (dmac->push.type & NVIF_MEM_VRAM) {
 236                 struct nvif_device *device = dmac->base.device;
 237                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 238                 nvif_msec(device, 2000,
 239                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 240                                 break;
 241                 );
 242         }
 243
 244         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 245         mutex_unlock(&dmac->lock);
 246 }
 247
 248 /******************************************************************************
 249  * Output path helpers
 250  *****************************************************************************/
 251 static void
 252 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 253 {
 254         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 255         struct {
 256                 struct nv50_disp_mthd_v1 base;
 257         } args = {
 258                 .base.version = 1,
 259                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 260                 .base.hasht  = nv_encoder->dcb->hasht,
 261                 .base.hashm  = nv_encoder->dcb->hashm,
 262         };
 263
 264         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 265         nv_encoder->or = -1;
 266         nv_encoder->link = 0;
 267 }
 268
 269 static int
 270 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 271 {
 272         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 273         struct nv50_disp *disp = nv50_disp(drm->dev);
 274         struct {
 275                 struct nv50_disp_mthd_v1 base;
 276                 struct nv50_disp_acquire_v0 info;
 277         } args = {
 278                 .base.version = 1,
 279                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 280                 .base.hasht  = nv_encoder->dcb->hasht,
 281                 .base.hashm  = nv_encoder->dcb->hashm,
 282         };
 283         int ret;
 284
 285         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 286         if (ret) {
 287                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 288                 return ret;
 289         }
 290
 291         nv_encoder->or = args.info.or;
 292         nv_encoder->link = args.info.link;
 293         return 0;
 294 }
 295
 296 static int
 297 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 298                             struct drm_crtc_state *crtc_state,
 299                             struct drm_connector_state *conn_state,
 300                             struct drm_display_mode *native_mode)
 301 {
 302         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 303         struct drm_display_mode *mode = &crtc_state->mode;
 304         struct drm_connector *connector = conn_state->connector;
 305         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 306         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 307
 308         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 309         asyc->scaler.full = false;
 310         if (!native_mode)
 311                 return 0;
 312
 313         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 314                 switch (connector->connector_type) {
 315                 case DRM_MODE_CONNECTOR_LVDS:
 316                 case DRM_MODE_CONNECTOR_eDP:
 317                         /* Force use of scaler for non-EDID modes. */
 318                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
 319                                 break;
 320                         mode = native_mode;
 321                         asyc->scaler.full = true;
 322                         break;
 323                 default:
 324                         break;
 325                 }
 326         } else {
 327                 mode = native_mode;
 328         }
 329
 330         if (!drm_mode_equal(adjusted_mode, mode)) {
 331                 drm_mode_copy(adjusted_mode, mode);
 332                 crtc_state->mode_changed = true;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static int
 339 nv50_outp_atomic_check(struct drm_encoder *encoder,
 340                        struct drm_crtc_state *crtc_state,
 341                        struct drm_connector_state *conn_state)
 342 {
 343         struct nouveau_connector *nv_connector =
 344                 nouveau_connector(conn_state->connector);
 345         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 346                                            nv_connector->native_mode);
 347 }
 348
 349 /******************************************************************************
 350  * DAC
 351  *****************************************************************************/
 352 static void
 353 nv50_dac_disable(struct drm_encoder *encoder)
 354 {
 355         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 356         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 357         if (nv_encoder->crtc)
 358                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 359         nv_encoder->crtc = NULL;
 360         nv50_outp_release(nv_encoder);
 361 }
 362
 363 static void
 364 nv50_dac_enable(struct drm_encoder *encoder)
 365 {
 366         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 367         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 368         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 369         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 370
 371         nv50_outp_acquire(nv_encoder);
 372
 373         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 374         asyh->or.depth = 0;
 375
 376         nv_encoder->crtc = encoder->crtc;
 377 }
 378
 379 static enum drm_connector_status
 380 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 381 {
 382         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 383         struct nv50_disp *disp = nv50_disp(encoder->dev);
 384         struct {
 385                 struct nv50_disp_mthd_v1 base;
 386                 struct nv50_disp_dac_load_v0 load;
 387         } args = {
 388                 .base.version = 1,
 389                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 390                 .base.hasht  = nv_encoder->dcb->hasht,
 391                 .base.hashm  = nv_encoder->dcb->hashm,
 392         };
 393         int ret;
 394
 395         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 396         if (args.load.data == 0)
 397                 args.load.data = 340;
 398
 399         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 400         if (ret || !args.load.load)
 401                 return connector_status_disconnected;
 402
 403         return connector_status_connected;
 404 }
 405
 406 static const struct drm_encoder_helper_funcs
 407 nv50_dac_help = {
 408         .atomic_check = nv50_outp_atomic_check,
 409         .enable = nv50_dac_enable,
 410         .disable = nv50_dac_disable,
 411         .detect = nv50_dac_detect
 412 };
 413
 414 static void
 415 nv50_dac_destroy(struct drm_encoder *encoder)
 416 {
 417         drm_encoder_cleanup(encoder);
 418         kfree(encoder);
 419 }
 420
 421 static const struct drm_encoder_funcs
 422 nv50_dac_func = {
 423         .destroy = nv50_dac_destroy,
 424 };
 425
 426 static int
 427 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 428 {
 429         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 430         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 431         struct nvkm_i2c_bus *bus;
 432         struct nouveau_encoder *nv_encoder;
 433         struct drm_encoder *encoder;
 434         int type = DRM_MODE_ENCODER_DAC;
 435
 436         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 437         if (!nv_encoder)
 438                 return -ENOMEM;
 439         nv_encoder->dcb = dcbe;
 440
 441         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 442         if (bus)
 443                 nv_encoder->i2c = &bus->i2c;
 444
 445         encoder = to_drm_encoder(nv_encoder);
 446         encoder->possible_crtcs = dcbe->heads;
 447         encoder->possible_clones = 0;
 448         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 449                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 450         drm_encoder_helper_add(encoder, &nv50_dac_help);
 451
 452         drm_connector_attach_encoder(connector, encoder);
 453         return 0;
 454 }
 455
 456 /******************************************************************************
 457  * Audio
 458  *****************************************************************************/
 459 static void
 460 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 461 {
 462         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 463         struct nv50_disp *disp = nv50_disp(encoder->dev);
 464         struct {
 465                 struct nv50_disp_mthd_v1 base;
 466                 struct nv50_disp_sor_hda_eld_v0 eld;
 467         } args = {
 468                 .base.version = 1,
 469                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 470                 .base.hasht   = nv_encoder->dcb->hasht,
 471                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 472                                 (0x0100 << nv_crtc->index),
 473         };
 474
 475         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 476 }
 477
 478 static void
 479 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 480 {
 481         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 482         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 483         struct nouveau_connector *nv_connector;
 484         struct nv50_disp *disp = nv50_disp(encoder->dev);
 485         struct __packed {
 486                 struct {
 487                         struct nv50_disp_mthd_v1 mthd;
 488                         struct nv50_disp_sor_hda_eld_v0 eld;
 489                 } base;
 490                 u8 data[sizeof(nv_connector->base.eld)];
 491         } args = {
 492                 .base.mthd.version = 1,
 493                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 494                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 495                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 496                                      (0x0100 << nv_crtc->index),
 497         };
 498
 499         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 500         if (!drm_detect_monitor_audio(nv_connector->edid))
 501                 return;
 502
 503         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 504
 505         nvif_mthd(&disp->disp->object, 0, &args,
 506                   sizeof(args.base) + drm_eld_size(args.data));
 507 }
 508
 509 /******************************************************************************
 510  * HDMI
 511  *****************************************************************************/
 512 static void
 513 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 514 {
 515         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 516         struct nv50_disp *disp = nv50_disp(encoder->dev);
 517         struct {
 518                 struct nv50_disp_mthd_v1 base;
 519                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 520         } args = {
 521                 .base.version = 1,
 522                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 523                 .base.hasht  = nv_encoder->dcb->hasht,
 524                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 525                                (0x0100 << nv_crtc->index),
 526         };
 527
 528         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 529 }
 530
 531 static void
 532 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 533 {
 534         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 535         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 536         struct nv50_disp *disp = nv50_disp(encoder->dev);
 537         struct {
 538                 struct nv50_disp_mthd_v1 base;
 539                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 540                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 541         } args = {
 542                 .base.version = 1,
 543                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 544                 .base.hasht  = nv_encoder->dcb->hasht,
 545                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 546                                (0x0100 << nv_crtc->index),
 547                 .pwr.state = 1,
 548                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 549         };
 550         struct nouveau_connector *nv_connector;
 551         u32 max_ac_packet;
 552         union hdmi_infoframe avi_frame;
 553         union hdmi_infoframe vendor_frame;
 554         int ret;
 555         int size;
 556
 557         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 558         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 559                 return;
 560
 561         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
 562                                                        false);
 563         if (!ret) {
 564                 /* We have an AVI InfoFrame, populate it to the display */
 565                 args.pwr.avi_infoframe_length
 566                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 567         }
 568
 569         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 570                                                           &nv_connector->base, mode);
 571         if (!ret) {
 572                 /* We have a Vendor InfoFrame, populate it to the display */
 573                 args.pwr.vendor_infoframe_length
 574                         = hdmi_infoframe_pack(&vendor_frame,
 575                                               args.infoframes
 576                                               + args.pwr.avi_infoframe_length,
 577                                               17);
 578         }
 579
 580         max_ac_packet  = mode->htotal - mode->hdisplay;
 581         max_ac_packet -= args.pwr.rekey;
 582         max_ac_packet -= 18; /* constant from tegra */
 583         args.pwr.max_ac_packet = max_ac_packet / 32;
 584
 585         size = sizeof(args.base)
 586                 + sizeof(args.pwr)
 587                 + args.pwr.avi_infoframe_length
 588                 + args.pwr.vendor_infoframe_length;
 589         nvif_mthd(&disp->disp->object, 0, &args, size);
 590         nv50_audio_enable(encoder, mode);
 591 }
 592
 593 /******************************************************************************
 594  * MST
 595  *****************************************************************************/
 596 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 597 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 598 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 599
 600 struct nv50_mstm {
 601         struct nouveau_encoder *outp;
 602
 603         struct drm_dp_mst_topology_mgr mgr;
 604         struct nv50_msto *msto[4];
 605
 606         bool modified;
 607         bool disabled;
 608         int links;
 609 };
 610
 611 struct nv50_mstc {
 612         struct nv50_mstm *mstm;
 613         struct drm_dp_mst_port *port;
 614         struct drm_connector connector;
 615
 616         struct drm_display_mode *native;
 617         struct edid *edid;
 618
 619         int pbn;
 620 };
 621
 622 struct nv50_msto {
 623         struct drm_encoder encoder;
 624
 625         struct nv50_head *head;
 626         struct nv50_mstc *mstc;
 627         bool disabled;
 628 };
 629
 630 static struct drm_dp_payload *
 631 nv50_msto_payload(struct nv50_msto *msto)
 632 {
 633         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 634         struct nv50_mstc *mstc = msto->mstc;
 635         struct nv50_mstm *mstm = mstc->mstm;
 636         int vcpi = mstc->port->vcpi.vcpi, i;
 637
 638         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 639         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 640                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 641                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 642                           mstm->outp->base.base.name, i, payload->vcpi,
 643                           payload->start_slot, payload->num_slots);
 644         }
 645
 646         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 647                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 648                 if (payload->vcpi == vcpi)
 649                         return payload;
 650         }
 651
 652         return NULL;
 653 }
 654
 655 static void
 656 nv50_msto_cleanup(struct nv50_msto *msto)
 657 {
 658         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 659         struct nv50_mstc *mstc = msto->mstc;
 660         struct nv50_mstm *mstm = mstc->mstm;
 661
 662         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 663         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
 664                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 665         if (msto->disabled) {
 666                 msto->mstc = NULL;
 667                 msto->head = NULL;
 668                 msto->disabled = false;
 669         }
 670 }
 671
 672 static void
 673 nv50_msto_prepare(struct nv50_msto *msto)
 674 {
 675         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 676         struct nv50_mstc *mstc = msto->mstc;
 677         struct nv50_mstm *mstm = mstc->mstm;
 678         struct {
 679                 struct nv50_disp_mthd_v1 base;
 680                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 681         } args = {
 682                 .base.version = 1,
 683                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 684                 .base.hasht  = mstm->outp->dcb->hasht,
 685                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 686                                (0x0100 << msto->head->base.index),
 687         };
 688
 689         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 690         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
 691                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 692                 if (payload) {
 693                         args.vcpi.start_slot = payload->start_slot;
 694                         args.vcpi.num_slots = payload->num_slots;
 695                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 696                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 697                 }
 698         }
 699
 700         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 701                   msto->encoder.name, msto->head->base.base.name,
 702                   args.vcpi.start_slot, args.vcpi.num_slots,
 703                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 704         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 705 }
 706
 707 static int
 708 nv50_msto_atomic_check(struct drm_encoder *encoder,
 709                        struct drm_crtc_state *crtc_state,
 710                        struct drm_connector_state *conn_state)
 711 {
 712         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
 713         struct nv50_mstm *mstm = mstc->mstm;
 714         int bpp = conn_state->connector->display_info.bpc * 3;
 715         int slots;
 716
 717         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
 718
 719         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 720         if (slots < 0)
 721                 return slots;
 722
 723         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 724                                            mstc->native);
 725 }
 726
 727 static void
 728 nv50_msto_enable(struct drm_encoder *encoder)
 729 {
 730         struct nv50_head *head = nv50_head(encoder->crtc);
 731         struct nv50_msto *msto = nv50_msto(encoder);
 732         struct nv50_mstc *mstc = NULL;
 733         struct nv50_mstm *mstm = NULL;
 734         struct drm_connector *connector;
 735         struct drm_connector_list_iter conn_iter;
 736         u8 proto, depth;
 737         int slots;
 738         bool r;
 739
 740         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 741         drm_for_each_connector_iter(connector, &conn_iter) {
 742                 if (connector->state->best_encoder == &msto->encoder) {
 743                         mstc = nv50_mstc(connector);
 744                         mstm = mstc->mstm;
 745                         break;
 746                 }
 747         }
 748         drm_connector_list_iter_end(&conn_iter);
 749
 750         if (WARN_ON(!mstc))
 751                 return;
 752
 753         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 754         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
 755         WARN_ON(!r);
 756
 757         if (!mstm->links++)
 758                 nv50_outp_acquire(mstm->outp);
 759
 760         if (mstm->outp->link & 1)
 761                 proto = 0x8;
 762         else
 763                 proto = 0x9;
 764
 765         switch (mstc->connector.display_info.bpc) {
 766         case  6: depth = 0x2; break;
 767         case  8: depth = 0x5; break;
 768         case 10:
 769         default: depth = 0x6; break;
 770         }
 771
 772         mstm->outp->update(mstm->outp, head->base.index,
 773                            nv50_head_atom(head->base.base.state), proto, depth);
 774
 775         msto->head = head;
 776         msto->mstc = mstc;
 777         mstm->modified = true;
 778 }
 779
 780 static void
 781 nv50_msto_disable(struct drm_encoder *encoder)
 782 {
 783         struct nv50_msto *msto = nv50_msto(encoder);
 784         struct nv50_mstc *mstc = msto->mstc;
 785         struct nv50_mstm *mstm = mstc->mstm;
 786
 787         if (mstc->port)
 788                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 789
 790         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 791         mstm->modified = true;
 792         if (!--mstm->links)
 793                 mstm->disabled = true;
 794         msto->disabled = true;
 795 }
 796
 797 static const struct drm_encoder_helper_funcs
 798 nv50_msto_help = {
 799         .disable = nv50_msto_disable,
 800         .enable = nv50_msto_enable,
 801         .atomic_check = nv50_msto_atomic_check,
 802 };
 803
 804 static void
 805 nv50_msto_destroy(struct drm_encoder *encoder)
 806 {
 807         struct nv50_msto *msto = nv50_msto(encoder);
 808         drm_encoder_cleanup(&msto->encoder);
 809         kfree(msto);
 810 }
 811
 812 static const struct drm_encoder_funcs
 813 nv50_msto = {
 814         .destroy = nv50_msto_destroy,
 815 };
 816
 817 static int
 818 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 819               struct nv50_msto **pmsto)
 820 {
 821         struct nv50_msto *msto;
 822         int ret;
 823
 824         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 825                 return -ENOMEM;
 826
 827         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 828                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 829         if (ret) {
 830                 kfree(*pmsto);
 831                 *pmsto = NULL;
 832                 return ret;
 833         }
 834
 835         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 836         msto->encoder.possible_crtcs = heads;
 837         return 0;
 838 }
 839
 840 static struct drm_encoder *
 841 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 842                               struct drm_connector_state *connector_state)
 843 {
 844         struct nv50_head *head = nv50_head(connector_state->crtc);
 845         struct nv50_mstc *mstc = nv50_mstc(connector);
 846         if (mstc->port) {
 847                 struct nv50_mstm *mstm = mstc->mstm;
 848                 return &mstm->msto[head->base.index]->encoder;
 849         }
 850         return NULL;
 851 }
 852
 853 static struct drm_encoder *
 854 nv50_mstc_best_encoder(struct drm_connector *connector)
 855 {
 856         struct nv50_mstc *mstc = nv50_mstc(connector);
 857         if (mstc->port) {
 858                 struct nv50_mstm *mstm = mstc->mstm;
 859                 return &mstm->msto[0]->encoder;
 860         }
 861         return NULL;
 862 }
 863
 864 static enum drm_mode_status
 865 nv50_mstc_mode_valid(struct drm_connector *connector,
 866                      struct drm_display_mode *mode)
 867 {
 868         return MODE_OK;
 869 }
 870
 871 static int
 872 nv50_mstc_get_modes(struct drm_connector *connector)
 873 {
 874         struct nv50_mstc *mstc = nv50_mstc(connector);
 875         int ret = 0;
 876
 877         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 878         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 879         if (mstc->edid)
 880                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 881
 882         if (!mstc->connector.display_info.bpc)
 883                 mstc->connector.display_info.bpc = 8;
 884
 885         if (mstc->native)
 886                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 887         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 888         return ret;
 889 }
 890
 891 static const struct drm_connector_helper_funcs
 892 nv50_mstc_help = {
 893         .get_modes = nv50_mstc_get_modes,
 894         .mode_valid = nv50_mstc_mode_valid,
 895         .best_encoder = nv50_mstc_best_encoder,
 896         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
 897 };
 898
 899 static enum drm_connector_status
 900 nv50_mstc_detect(struct drm_connector *connector, bool force)
 901 {
 902         struct nv50_mstc *mstc = nv50_mstc(connector);
 903         if (!mstc->port)
 904                 return connector_status_disconnected;
 905         return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
 906 }
 907
 908 static void
 909 nv50_mstc_destroy(struct drm_connector *connector)
 910 {
 911         struct nv50_mstc *mstc = nv50_mstc(connector);
 912         drm_connector_cleanup(&mstc->connector);
 913         kfree(mstc);
 914 }
 915
 916 static const struct drm_connector_funcs
 917 nv50_mstc = {
 918         .reset = nouveau_conn_reset,
 919         .detect = nv50_mstc_detect,
 920         .fill_modes = drm_helper_probe_single_connector_modes,
 921         .destroy = nv50_mstc_destroy,
 922         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
 923         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
 924         .atomic_set_property = nouveau_conn_atomic_set_property,
 925         .atomic_get_property = nouveau_conn_atomic_get_property,
 926 };
 927
 928 static int
 929 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
 930               const char *path, struct nv50_mstc **pmstc)
 931 {
 932         struct drm_device *dev = mstm->outp->base.base.dev;
 933         struct nv50_mstc *mstc;
 934         int ret, i;
 935
 936         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
 937                 return -ENOMEM;
 938         mstc->mstm = mstm;
 939         mstc->port = port;
 940
 941         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
 942                                  DRM_MODE_CONNECTOR_DisplayPort);
 943         if (ret) {
 944                 kfree(*pmstc);
 945                 *pmstc = NULL;
 946                 return ret;
 947         }
 948
 949         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
 950
 951         mstc->connector.funcs->reset(&mstc->connector);
 952         nouveau_conn_attach_properties(&mstc->connector);
 953
 954         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
 955                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
 956
 957         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
 958         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
 959         drm_connector_set_path_property(&mstc->connector, path);
 960         return 0;
 961 }
 962
 963 static void
 964 nv50_mstm_cleanup(struct nv50_mstm *mstm)
 965 {
 966         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
 967         struct drm_encoder *encoder;
 968         int ret;
 969
 970         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
 971         ret = drm_dp_check_act_status(&mstm->mgr);
 972
 973         ret = drm_dp_update_payload_part2(&mstm->mgr);
 974
 975         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
 976                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
 977                         struct nv50_msto *msto = nv50_msto(encoder);
 978                         struct nv50_mstc *mstc = msto->mstc;
 979                         if (mstc && mstc->mstm == mstm)
 980                                 nv50_msto_cleanup(msto);
 981                 }
 982         }
 983
 984         mstm->modified = false;
 985 }
 986
 987 static void
 988 nv50_mstm_prepare(struct nv50_mstm *mstm)
 989 {
 990         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
 991         struct drm_encoder *encoder;
 992         int ret;
 993
 994         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
 995         ret = drm_dp_update_payload_part1(&mstm->mgr);
 996
 997         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
 998                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
 999                         struct nv50_msto *msto = nv50_msto(encoder);
1000                         struct nv50_mstc *mstc = msto->mstc;
1001                         if (mstc && mstc->mstm == mstm)
1002                                 nv50_msto_prepare(msto);
1003                 }
1004         }
1005
1006         if (mstm->disabled) {
1007                 if (!mstm->links)
1008                         nv50_outp_release(mstm->outp);
1009                 mstm->disabled = false;
1010         }
1011 }
1012
1013 static void
1014 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
1015 {
1016         struct nv50_mstm *mstm = nv50_mstm(mgr);
1017         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
1018 }
1019
1020 static void
1021 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1022                             struct drm_connector *connector)
1023 {
1024         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1025         struct nv50_mstc *mstc = nv50_mstc(connector);
1026
1027         drm_connector_unregister(&mstc->connector);
1028
1029         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1030
1031         drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1032         mstc->port = NULL;
1033         drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1034
1035         drm_connector_put(&mstc->connector);
1036 }
1037
1038 static void
1039 nv50_mstm_register_connector(struct drm_connector *connector)
1040 {
1041         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1042
1043         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1044
1045         drm_connector_register(connector);
1046 }
1047
1048 static struct drm_connector *
1049 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1050                         struct drm_dp_mst_port *port, const char *path)
1051 {
1052         struct nv50_mstm *mstm = nv50_mstm(mgr);
1053         struct nv50_mstc *mstc;
1054         int ret;
1055
1056         ret = nv50_mstc_new(mstm, port, path, &mstc);
1057         if (ret) {
1058                 if (mstc)
1059                         mstc->connector.funcs->destroy(&mstc->connector);
1060                 return NULL;
1061         }
1062
1063         return &mstc->connector;
1064 }
1065
1066 static const struct drm_dp_mst_topology_cbs
1067 nv50_mstm = {
1068         .add_connector = nv50_mstm_add_connector,
1069         .register_connector = nv50_mstm_register_connector,
1070         .destroy_connector = nv50_mstm_destroy_connector,
1071         .hotplug = nv50_mstm_hotplug,
1072 };
1073
1074 void
1075 nv50_mstm_service(struct nv50_mstm *mstm)
1076 {
1077         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1078         bool handled = true;
1079         int ret;
1080         u8 esi[8] = {};
1081
1082         if (!aux)
1083                 return;
1084
1085         while (handled) {
1086                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1087                 if (ret != 8) {
1088                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1089                         return;
1090                 }
1091
1092                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1093                 if (!handled)
1094                         break;
1095
1096                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1097         }
1098 }
1099
1100 void
1101 nv50_mstm_remove(struct nv50_mstm *mstm)
1102 {
1103         if (mstm)
1104                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1105 }
1106
1107 static int
1108 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1109 {
1110         struct nouveau_encoder *outp = mstm->outp;
1111         struct {
1112                 struct nv50_disp_mthd_v1 base;
1113                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1114         } args = {
1115                 .base.version = 1,
1116                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1117                 .base.hasht = outp->dcb->hasht,
1118                 .base.hashm = outp->dcb->hashm,
1119                 .mst.state = state,
1120         };
1121         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1122         struct nvif_object *disp = &drm->display->disp.object;
1123         int ret;
1124
1125         if (dpcd >= 0x12) {
1126                 /* Even if we're enabling MST, start with disabling the
1127                  * branching unit to clear any sink-side MST topology state
1128                  * that wasn't set by us
1129                  */
1130                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1131                 if (ret < 0)
1132                         return ret;
1133
1134                 if (state) {
1135                         /* Now, start initializing */
1136                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1137                                                  DP_MST_EN);
1138                         if (ret < 0)
1139                                 return ret;
1140                 }
1141         }
1142
1143         return nvif_mthd(disp, 0, &args, sizeof(args));
1144 }
1145
1146 int
1147 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1148 {
1149         struct drm_dp_aux *aux;
1150         int ret;
1151         bool old_state, new_state;
1152         u8 mstm_ctrl;
1153
1154         if (!mstm)
1155                 return 0;
1156
1157         mutex_lock(&mstm->mgr.lock);
1158
1159         old_state = mstm->mgr.mst_state;
1160         new_state = old_state;
1161         aux = mstm->mgr.aux;
1162
1163         if (old_state) {
1164                 /* Just check that the MST hub is still as we expect it */
1165                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1166                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1167                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1168                         new_state = false;
1169                 }
1170         } else if (dpcd[0] >= 0x12) {
1171                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1172                 if (ret < 0)
1173                         goto probe_error;
1174
1175                 if (!(dpcd[1] & DP_MST_CAP))
1176                         dpcd[0] = 0x11;
1177                 else
1178                         new_state = allow;
1179         }
1180
1181         if (new_state == old_state) {
1182                 mutex_unlock(&mstm->mgr.lock);
1183                 return new_state;
1184         }
1185
1186         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1187         if (ret)
1188                 goto probe_error;
1189
1190         mutex_unlock(&mstm->mgr.lock);
1191
1192         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1193         if (ret)
1194                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1195
1196         return new_state;
1197
1198 probe_error:
1199         mutex_unlock(&mstm->mgr.lock);
1200         return ret;
1201 }
1202
1203 static void
1204 nv50_mstm_fini(struct nv50_mstm *mstm)
1205 {
1206         if (mstm && mstm->mgr.mst_state)
1207                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1208 }
1209
1210 static void
1211 nv50_mstm_init(struct nv50_mstm *mstm)
1212 {
1213         if (mstm && mstm->mgr.mst_state)
1214                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1215 }
1216
1217 static void
1218 nv50_mstm_del(struct nv50_mstm **pmstm)
1219 {
1220         struct nv50_mstm *mstm = *pmstm;
1221         if (mstm) {
1222                 kfree(*pmstm);
1223                 *pmstm = NULL;
1224         }
1225 }
1226
1227 static int
1228 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1229               int conn_base_id, struct nv50_mstm **pmstm)
1230 {
1231         const int max_payloads = hweight8(outp->dcb->heads);
1232         struct drm_device *dev = outp->base.base.dev;
1233         struct nv50_mstm *mstm;
1234         int ret, i;
1235         u8 dpcd;
1236
1237         /* This is a workaround for some monitors not functioning
1238          * correctly in MST mode on initial module load.  I think
1239          * some bad interaction with the VBIOS may be responsible.
1240          *
1241          * A good ol' off and on again seems to work here ;)
1242          */
1243         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1244         if (ret >= 0 && dpcd >= 0x12)
1245                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1246
1247         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1248                 return -ENOMEM;
1249         mstm->outp = outp;
1250         mstm->mgr.cbs = &nv50_mstm;
1251
1252         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1253                                            max_payloads, conn_base_id);
1254         if (ret)
1255                 return ret;
1256
1257         for (i = 0; i < max_payloads; i++) {
1258                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1259                                     i, &mstm->msto[i]);
1260                 if (ret)
1261                         return ret;
1262         }
1263
1264         return 0;
1265 }
1266
1267 /******************************************************************************
1268  * SOR
1269  *****************************************************************************/
1270 static void
1271 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1272                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1273 {
1274         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1275         struct nv50_core *core = disp->core;
1276
1277         if (!asyh) {
1278                 nv_encoder->ctrl &= ~BIT(head);
1279                 if (!(nv_encoder->ctrl & 0x0000000f))
1280                         nv_encoder->ctrl = 0;
1281         } else {
1282                 nv_encoder->ctrl |= proto << 8;
1283                 nv_encoder->ctrl |= BIT(head);
1284                 asyh->or.depth = depth;
1285         }
1286
1287         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1288 }
1289
1290 static void
1291 nv50_sor_disable(struct drm_encoder *encoder)
1292 {
1293         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1294         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1295
1296         nv_encoder->crtc = NULL;
1297
1298         if (nv_crtc) {
1299                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1300                 u8 pwr;
1301
1302                 if (aux) {
1303                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1304                         if (ret == 0) {
1305                                 pwr &= ~DP_SET_POWER_MASK;
1306                                 pwr |=  DP_SET_POWER_D3;
1307                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1308                         }
1309                 }
1310
1311                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1312                 nv50_audio_disable(encoder, nv_crtc);
1313                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1314                 nv50_outp_release(nv_encoder);
1315         }
1316 }
1317
1318 static void
1319 nv50_sor_enable(struct drm_encoder *encoder)
1320 {
1321         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1322         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1323         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1324         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1325         struct {
1326                 struct nv50_disp_mthd_v1 base;
1327                 struct nv50_disp_sor_lvds_script_v0 lvds;
1328         } lvds = {
1329                 .base.version = 1,
1330                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1331                 .base.hasht   = nv_encoder->dcb->hasht,
1332                 .base.hashm   = nv_encoder->dcb->hashm,
1333         };
1334         struct nv50_disp *disp = nv50_disp(encoder->dev);
1335         struct drm_device *dev = encoder->dev;
1336         struct nouveau_drm *drm = nouveau_drm(dev);
1337         struct nouveau_connector *nv_connector;
1338         struct nvbios *bios = &drm->vbios;
1339         u8 proto = 0xf;
1340         u8 depth = 0x0;
1341
1342         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1343         nv_encoder->crtc = encoder->crtc;
1344         nv50_outp_acquire(nv_encoder);
1345
1346         switch (nv_encoder->dcb->type) {
1347         case DCB_OUTPUT_TMDS:
1348                 if (nv_encoder->link & 1) {
1349                         proto = 0x1;
1350                         /* Only enable dual-link if:
1351                          *  - Need to (i.e. rate > 165MHz)
1352                          *  - DCB says we can
1353                          *  - Not an HDMI monitor, since there's no dual-link
1354                          *    on HDMI.
1355                          */
1356                         if (mode->clock >= 165000 &&
1357                             nv_encoder->dcb->duallink_possible &&
1358                             !drm_detect_hdmi_monitor(nv_connector->edid))
1359                                 proto |= 0x4;
1360                 } else {
1361                         proto = 0x2;
1362                 }
1363
1364                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1365                 break;
1366         case DCB_OUTPUT_LVDS:
1367                 proto = 0x0;
1368
1369                 if (bios->fp_no_ddc) {
1370                         if (bios->fp.dual_link)
1371                                 lvds.lvds.script |= 0x0100;
1372                         if (bios->fp.if_is_24bit)
1373                                 lvds.lvds.script |= 0x0200;
1374                 } else {
1375                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1376                                 if (((u8 *)nv_connector->edid)[121] == 2)
1377                                         lvds.lvds.script |= 0x0100;
1378                         } else
1379                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1380                                 lvds.lvds.script |= 0x0100;
1381                         }
1382
1383                         if (lvds.lvds.script & 0x0100) {
1384                                 if (bios->fp.strapless_is_24bit & 2)
1385                                         lvds.lvds.script |= 0x0200;
1386                         } else {
1387                                 if (bios->fp.strapless_is_24bit & 1)
1388                                         lvds.lvds.script |= 0x0200;
1389                         }
1390
1391                         if (nv_connector->base.display_info.bpc == 8)
1392                                 lvds.lvds.script |= 0x0200;
1393                 }
1394
1395                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1396                 break;
1397         case DCB_OUTPUT_DP:
1398                 if (nv_connector->base.display_info.bpc == 6)
1399                         depth = 0x2;
1400                 else
1401                 if (nv_connector->base.display_info.bpc == 8)
1402                         depth = 0x5;
1403                 else
1404                         depth = 0x6;
1405
1406                 if (nv_encoder->link & 1)
1407                         proto = 0x8;
1408                 else
1409                         proto = 0x9;
1410
1411                 nv50_audio_enable(encoder, mode);
1412                 break;
1413         default:
1414                 BUG();
1415                 break;
1416         }
1417
1418         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1419 }
1420
1421 static const struct drm_encoder_helper_funcs
1422 nv50_sor_help = {
1423         .atomic_check = nv50_outp_atomic_check,
1424         .enable = nv50_sor_enable,
1425         .disable = nv50_sor_disable,
1426 };
1427
1428 static void
1429 nv50_sor_destroy(struct drm_encoder *encoder)
1430 {
1431         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1432         nv50_mstm_del(&nv_encoder->dp.mstm);
1433         drm_encoder_cleanup(encoder);
1434         kfree(encoder);
1435 }
1436
1437 static const struct drm_encoder_funcs
1438 nv50_sor_func = {
1439         .destroy = nv50_sor_destroy,
1440 };
1441
1442 static int
1443 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1444 {
1445         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1446         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1447         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1448         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1449         struct nouveau_encoder *nv_encoder;
1450         struct drm_encoder *encoder;
1451         u8 ver, hdr, cnt, len;
1452         u32 data;
1453         int type, ret;
1454
1455         switch (dcbe->type) {
1456         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1457         case DCB_OUTPUT_TMDS:
1458         case DCB_OUTPUT_DP:
1459         default:
1460                 type = DRM_MODE_ENCODER_TMDS;
1461                 break;
1462         }
1463
1464         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1465         if (!nv_encoder)
1466                 return -ENOMEM;
1467         nv_encoder->dcb = dcbe;
1468         nv_encoder->update = nv50_sor_update;
1469
1470         encoder = to_drm_encoder(nv_encoder);
1471         encoder->possible_crtcs = dcbe->heads;
1472         encoder->possible_clones = 0;
1473         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1474                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1475         drm_encoder_helper_add(encoder, &nv50_sor_help);
1476
1477         drm_connector_attach_encoder(connector, encoder);
1478
1479         if (dcbe->type == DCB_OUTPUT_DP) {
1480                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1481                 struct nvkm_i2c_aux *aux =
1482                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1483                 if (aux) {
1484                         if (disp->disp->object.oclass < GF110_DISP) {
1485                                 /* HW has no support for address-only
1486                                  * transactions, so we're required to
1487                                  * use custom I2C-over-AUX code.
1488                                  */
1489                                 nv_encoder->i2c = &aux->i2c;
1490                         } else {
1491                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1492                         }
1493                         nv_encoder->aux = aux;
1494                 }
1495
1496                 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1497                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1498                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1499                                             nv_connector->base.base.id,
1500                                             &nv_encoder->dp.mstm);
1501                         if (ret)
1502                                 return ret;
1503                 }
1504         } else {
1505                 struct nvkm_i2c_bus *bus =
1506                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1507                 if (bus)
1508                         nv_encoder->i2c = &bus->i2c;
1509         }
1510
1511         return 0;
1512 }
1513
1514 /******************************************************************************
1515  * PIOR
1516  *****************************************************************************/
1517 static int
1518 nv50_pior_atomic_check(struct drm_encoder *encoder,
1519                        struct drm_crtc_state *crtc_state,
1520                        struct drm_connector_state *conn_state)
1521 {
1522         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1523         if (ret)
1524                 return ret;
1525         crtc_state->adjusted_mode.clock *= 2;
1526         return 0;
1527 }
1528
1529 static void
1530 nv50_pior_disable(struct drm_encoder *encoder)
1531 {
1532         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1533         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1534         if (nv_encoder->crtc)
1535                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1536         nv_encoder->crtc = NULL;
1537         nv50_outp_release(nv_encoder);
1538 }
1539
1540 static void
1541 nv50_pior_enable(struct drm_encoder *encoder)
1542 {
1543         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1544         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1545         struct nouveau_connector *nv_connector;
1546         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1547         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1548         u8 owner = 1 << nv_crtc->index;
1549         u8 proto;
1550
1551         nv50_outp_acquire(nv_encoder);
1552
1553         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1554         switch (nv_connector->base.display_info.bpc) {
1555         case 10: asyh->or.depth = 0x6; break;
1556         case  8: asyh->or.depth = 0x5; break;
1557         case  6: asyh->or.depth = 0x2; break;
1558         default: asyh->or.depth = 0x0; break;
1559         }
1560
1561         switch (nv_encoder->dcb->type) {
1562         case DCB_OUTPUT_TMDS:
1563         case DCB_OUTPUT_DP:
1564                 proto = 0x0;
1565                 break;
1566         default:
1567                 BUG();
1568                 break;
1569         }
1570
1571         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1572         nv_encoder->crtc = encoder->crtc;
1573 }
1574
1575 static const struct drm_encoder_helper_funcs
1576 nv50_pior_help = {
1577         .atomic_check = nv50_pior_atomic_check,
1578         .enable = nv50_pior_enable,
1579         .disable = nv50_pior_disable,
1580 };
1581
1582 static void
1583 nv50_pior_destroy(struct drm_encoder *encoder)
1584 {
1585         drm_encoder_cleanup(encoder);
1586         kfree(encoder);
1587 }
1588
1589 static const struct drm_encoder_funcs
1590 nv50_pior_func = {
1591         .destroy = nv50_pior_destroy,
1592 };
1593
1594 static int
1595 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1596 {
1597         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1598         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1599         struct nvkm_i2c_bus *bus = NULL;
1600         struct nvkm_i2c_aux *aux = NULL;
1601         struct i2c_adapter *ddc;
1602         struct nouveau_encoder *nv_encoder;
1603         struct drm_encoder *encoder;
1604         int type;
1605
1606         switch (dcbe->type) {
1607         case DCB_OUTPUT_TMDS:
1608                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1609                 ddc  = bus ? &bus->i2c : NULL;
1610                 type = DRM_MODE_ENCODER_TMDS;
1611                 break;
1612         case DCB_OUTPUT_DP:
1613                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1614                 ddc  = aux ? &aux->i2c : NULL;
1615                 type = DRM_MODE_ENCODER_TMDS;
1616                 break;
1617         default:
1618                 return -ENODEV;
1619         }
1620
1621         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1622         if (!nv_encoder)
1623                 return -ENOMEM;
1624         nv_encoder->dcb = dcbe;
1625         nv_encoder->i2c = ddc;
1626         nv_encoder->aux = aux;
1627
1628         encoder = to_drm_encoder(nv_encoder);
1629         encoder->possible_crtcs = dcbe->heads;
1630         encoder->possible_clones = 0;
1631         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1632                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1633         drm_encoder_helper_add(encoder, &nv50_pior_help);
1634
1635         drm_connector_attach_encoder(connector, encoder);
1636         return 0;
1637 }
1638
1639 /******************************************************************************
1640  * Atomic
1641  *****************************************************************************/
1642
1643 static void
1644 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1645 {
1646         struct nouveau_drm *drm = nouveau_drm(state->dev);
1647         struct nv50_disp *disp = nv50_disp(drm->dev);
1648         struct nv50_core *core = disp->core;
1649         struct nv50_mstm *mstm;
1650         struct drm_encoder *encoder;
1651
1652         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1653
1654         drm_for_each_encoder(encoder, drm->dev) {
1655                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1656                         mstm = nouveau_encoder(encoder)->dp.mstm;
1657                         if (mstm && mstm->modified)
1658                                 nv50_mstm_prepare(mstm);
1659                 }
1660         }
1661
1662         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1663         core->func->update(core, interlock, true);
1664         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1665                                        disp->core->chan.base.device))
1666                 NV_ERROR(drm, "core notifier timeout\n");
1667
1668         drm_for_each_encoder(encoder, drm->dev) {
1669                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1670                         mstm = nouveau_encoder(encoder)->dp.mstm;
1671                         if (mstm && mstm->modified)
1672                                 nv50_mstm_cleanup(mstm);
1673                 }
1674         }
1675 }
1676
1677 static void
1678 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1679 {
1680         struct drm_plane_state *new_plane_state;
1681         struct drm_plane *plane;
1682         int i;
1683
1684         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1685                 struct nv50_wndw *wndw = nv50_wndw(plane);
1686                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1687                         if (wndw->func->update)
1688                                 wndw->func->update(wndw, interlock);
1689                 }
1690         }
1691 }
1692
1693 static void
1694 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1695 {
1696         struct drm_device *dev = state->dev;
1697         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1698         struct drm_crtc *crtc;
1699         struct drm_plane_state *new_plane_state;
1700         struct drm_plane *plane;
1701         struct nouveau_drm *drm = nouveau_drm(dev);
1702         struct nv50_disp *disp = nv50_disp(dev);
1703         struct nv50_atom *atom = nv50_atom(state);
1704         struct nv50_outp_atom *outp, *outt;
1705         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1706         int i;
1707
1708         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1709         drm_atomic_helper_wait_for_fences(dev, state, false);
1710         drm_atomic_helper_wait_for_dependencies(state);
1711         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1712
1713         if (atom->lock_core)
1714                 mutex_lock(&disp->mutex);
1715
1716         /* Disable head(s). */
1717         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1718                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1719                 struct nv50_head *head = nv50_head(crtc);
1720
1721                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1722                           asyh->clr.mask, asyh->set.mask);
1723                 if (old_crtc_state->active && !new_crtc_state->active)
1724                         drm_crtc_vblank_off(crtc);
1725
1726                 if (asyh->clr.mask) {
1727                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1728                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1729                 }
1730         }
1731
1732         /* Disable plane(s). */
1733         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1734                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1735                 struct nv50_wndw *wndw = nv50_wndw(plane);
1736
1737                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1738                           asyw->clr.mask, asyw->set.mask);
1739                 if (!asyw->clr.mask)
1740                         continue;
1741
1742                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1743         }
1744
1745         /* Disable output path(s). */
1746         list_for_each_entry(outp, &atom->outp, head) {
1747                 const struct drm_encoder_helper_funcs *help;
1748                 struct drm_encoder *encoder;
1749
1750                 encoder = outp->encoder;
1751                 help = encoder->helper_private;
1752
1753                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1754                           outp->clr.mask, outp->set.mask);
1755
1756                 if (outp->clr.mask) {
1757                         help->disable(encoder);
1758                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1759                         if (outp->flush_disable) {
1760                                 nv50_disp_atomic_commit_wndw(state, interlock);
1761                                 nv50_disp_atomic_commit_core(state, interlock);
1762                                 memset(interlock, 0x00, sizeof(interlock));
1763                         }
1764                 }
1765         }
1766
1767         /* Flush disable. */
1768         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1769                 if (atom->flush_disable) {
1770                         nv50_disp_atomic_commit_wndw(state, interlock);
1771                         nv50_disp_atomic_commit_core(state, interlock);
1772                         memset(interlock, 0x00, sizeof(interlock));
1773                 }
1774         }
1775
1776         /* Update output path(s). */
1777         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1778                 const struct drm_encoder_helper_funcs *help;
1779                 struct drm_encoder *encoder;
1780
1781                 encoder = outp->encoder;
1782                 help = encoder->helper_private;
1783
1784                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1785                           outp->set.mask, outp->clr.mask);
1786
1787                 if (outp->set.mask) {
1788                         help->enable(encoder);
1789                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1790                 }
1791
1792                 list_del(&outp->head);
1793                 kfree(outp);
1794         }
1795
1796         /* Update head(s). */
1797         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1798                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1799                 struct nv50_head *head = nv50_head(crtc);
1800
1801                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1802                           asyh->set.mask, asyh->clr.mask);
1803
1804                 if (asyh->set.mask) {
1805                         nv50_head_flush_set(head, asyh);
1806                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1807                 }
1808
1809                 if (new_crtc_state->active) {
1810                         if (!old_crtc_state->active)
1811                                 drm_crtc_vblank_on(crtc);
1812                         if (new_crtc_state->event)
1813                                 drm_crtc_vblank_get(crtc);
1814                 }
1815         }
1816
1817         /* Update plane(s). */
1818         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1819                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1820                 struct nv50_wndw *wndw = nv50_wndw(plane);
1821
1822                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1823                           asyw->set.mask, asyw->clr.mask);
1824                 if ( !asyw->set.mask &&
1825                     (!asyw->clr.mask || atom->flush_disable))
1826                         continue;
1827
1828                 nv50_wndw_flush_set(wndw, interlock, asyw);
1829         }
1830
1831         /* Flush update. */
1832         nv50_disp_atomic_commit_wndw(state, interlock);
1833
1834         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1835                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1836                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1837                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1838                     !atom->state.legacy_cursor_update)
1839                         nv50_disp_atomic_commit_core(state, interlock);
1840                 else
1841                         disp->core->func->update(disp->core, interlock, false);
1842         }
1843
1844         if (atom->lock_core)
1845                 mutex_unlock(&disp->mutex);
1846
1847         /* Wait for HW to signal completion. */
1848         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1849                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1850                 struct nv50_wndw *wndw = nv50_wndw(plane);
1851                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1852                 if (ret)
1853                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1854         }
1855
1856         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1857                 if (new_crtc_state->event) {
1858                         unsigned long flags;
1859                         /* Get correct count/ts if racing with vblank irq */
1860                         if (new_crtc_state->active)
1861                                 drm_crtc_accurate_vblank_count(crtc);
1862                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1863                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1864                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1865
1866                         new_crtc_state->event = NULL;
1867                         if (new_crtc_state->active)
1868                                 drm_crtc_vblank_put(crtc);
1869                 }
1870         }
1871
1872         drm_atomic_helper_commit_hw_done(state);
1873         drm_atomic_helper_cleanup_planes(dev, state);
1874         drm_atomic_helper_commit_cleanup_done(state);
1875         drm_atomic_state_put(state);
1876 }
1877
1878 static void
1879 nv50_disp_atomic_commit_work(struct work_struct *work)
1880 {
1881         struct drm_atomic_state *state =
1882                 container_of(work, typeof(*state), commit_work);
1883         nv50_disp_atomic_commit_tail(state);
1884 }
1885
1886 static int
1887 nv50_disp_atomic_commit(struct drm_device *dev,
1888                         struct drm_atomic_state *state, bool nonblock)
1889 {
1890         struct nouveau_drm *drm = nouveau_drm(dev);
1891         struct drm_plane_state *new_plane_state;
1892         struct drm_plane *plane;
1893         struct drm_crtc *crtc;
1894         bool active = false;
1895         int ret, i;
1896
1897         ret = pm_runtime_get_sync(dev->dev);
1898         if (ret < 0 && ret != -EACCES)
1899                 return ret;
1900
1901         ret = drm_atomic_helper_setup_commit(state, nonblock);
1902         if (ret)
1903                 goto done;
1904
1905         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
1906
1907         ret = drm_atomic_helper_prepare_planes(dev, state);
1908         if (ret)
1909                 goto done;
1910
1911         if (!nonblock) {
1912                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
1913                 if (ret)
1914                         goto err_cleanup;
1915         }
1916
1917         ret = drm_atomic_helper_swap_state(state, true);
1918         if (ret)
1919                 goto err_cleanup;
1920
1921         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1922                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1923                 struct nv50_wndw *wndw = nv50_wndw(plane);
1924
1925                 if (asyw->set.image)
1926                         nv50_wndw_ntfy_enable(wndw, asyw);
1927         }
1928
1929         drm_atomic_state_get(state);
1930
1931         if (nonblock)
1932                 queue_work(system_unbound_wq, &state->commit_work);
1933         else
1934                 nv50_disp_atomic_commit_tail(state);
1935
1936         drm_for_each_crtc(crtc, dev) {
1937                 if (crtc->state->active) {
1938                         if (!drm->have_disp_power_ref) {
1939                                 drm->have_disp_power_ref = true;
1940                                 return 0;
1941                         }
1942                         active = true;
1943                         break;
1944                 }
1945         }
1946
1947         if (!active && drm->have_disp_power_ref) {
1948                 pm_runtime_put_autosuspend(dev->dev);
1949                 drm->have_disp_power_ref = false;
1950         }
1951
1952 err_cleanup:
1953         if (ret)
1954                 drm_atomic_helper_cleanup_planes(dev, state);
1955 done:
1956         pm_runtime_put_autosuspend(dev->dev);
1957         return ret;
1958 }
1959
1960 static struct nv50_outp_atom *
1961 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
1962 {
1963         struct nv50_outp_atom *outp;
1964
1965         list_for_each_entry(outp, &atom->outp, head) {
1966                 if (outp->encoder == encoder)
1967                         return outp;
1968         }
1969
1970         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
1971         if (!outp)
1972                 return ERR_PTR(-ENOMEM);
1973
1974         list_add(&outp->head, &atom->outp);
1975         outp->encoder = encoder;
1976         return outp;
1977 }
1978
1979 static int
1980 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
1981                                 struct drm_connector_state *old_connector_state)
1982 {
1983         struct drm_encoder *encoder = old_connector_state->best_encoder;
1984         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1985         struct drm_crtc *crtc;
1986         struct nv50_outp_atom *outp;
1987
1988         if (!(crtc = old_connector_state->crtc))
1989                 return 0;
1990
1991         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
1992         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
1993         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
1994                 outp = nv50_disp_outp_atomic_add(atom, encoder);
1995                 if (IS_ERR(outp))
1996                         return PTR_ERR(outp);
1997
1998                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1999                         outp->flush_disable = true;
2000                         atom->flush_disable = true;
2001                 }
2002                 outp->clr.ctrl = true;
2003                 atom->lock_core = true;
2004         }
2005
2006         return 0;
2007 }
2008
2009 static int
2010 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2011                                 struct drm_connector_state *connector_state)
2012 {
2013         struct drm_encoder *encoder = connector_state->best_encoder;
2014         struct drm_crtc_state *new_crtc_state;
2015         struct drm_crtc *crtc;
2016         struct nv50_outp_atom *outp;
2017
2018         if (!(crtc = connector_state->crtc))
2019                 return 0;
2020
2021         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2022         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2023                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2024                 if (IS_ERR(outp))
2025                         return PTR_ERR(outp);
2026
2027                 outp->set.ctrl = true;
2028                 atom->lock_core = true;
2029         }
2030
2031         return 0;
2032 }
2033
2034 static int
2035 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2036 {
2037         struct nv50_atom *atom = nv50_atom(state);
2038         struct drm_connector_state *old_connector_state, *new_connector_state;
2039         struct drm_connector *connector;
2040         struct drm_crtc_state *new_crtc_state;
2041         struct drm_crtc *crtc;
2042         int ret, i;
2043
2044         /* We need to handle colour management on a per-plane basis. */
2045         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2046                 if (new_crtc_state->color_mgmt_changed) {
2047                         ret = drm_atomic_add_affected_planes(state, crtc);
2048                         if (ret)
2049                                 return ret;
2050                 }
2051         }
2052
2053         ret = drm_atomic_helper_check(dev, state);
2054         if (ret)
2055                 return ret;
2056
2057         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2058                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2059                 if (ret)
2060                         return ret;
2061
2062                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2063                 if (ret)
2064                         return ret;
2065         }
2066
2067         return 0;
2068 }
2069
2070 static void
2071 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2072 {
2073         struct nv50_atom *atom = nv50_atom(state);
2074         struct nv50_outp_atom *outp, *outt;
2075
2076         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2077                 list_del(&outp->head);
2078                 kfree(outp);
2079         }
2080
2081         drm_atomic_state_default_clear(state);
2082 }
2083
2084 static void
2085 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2086 {
2087         struct nv50_atom *atom = nv50_atom(state);
2088         drm_atomic_state_default_release(&atom->state);
2089         kfree(atom);
2090 }
2091
2092 static struct drm_atomic_state *
2093 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2094 {
2095         struct nv50_atom *atom;
2096         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2097             drm_atomic_state_init(dev, &atom->state) < 0) {
2098                 kfree(atom);
2099                 return NULL;
2100         }
2101         INIT_LIST_HEAD(&atom->outp);
2102         return &atom->state;
2103 }
2104
2105 static const struct drm_mode_config_funcs
2106 nv50_disp_func = {
2107         .fb_create = nouveau_user_framebuffer_create,
2108         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2109         .atomic_check = nv50_disp_atomic_check,
2110         .atomic_commit = nv50_disp_atomic_commit,
2111         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2112         .atomic_state_clear = nv50_disp_atomic_state_clear,
2113         .atomic_state_free = nv50_disp_atomic_state_free,
2114 };
2115
2116 /******************************************************************************
2117  * Init
2118  *****************************************************************************/
2119
2120 void
2121 nv50_display_fini(struct drm_device *dev)
2122 {
2123         struct nouveau_encoder *nv_encoder;
2124         struct drm_encoder *encoder;
2125         struct drm_plane *plane;
2126
2127         drm_for_each_plane(plane, dev) {
2128                 struct nv50_wndw *wndw = nv50_wndw(plane);
2129                 if (plane->funcs != &nv50_wndw)
2130                         continue;
2131                 nv50_wndw_fini(wndw);
2132         }
2133
2134         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2135                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2136                         nv_encoder = nouveau_encoder(encoder);
2137                         nv50_mstm_fini(nv_encoder->dp.mstm);
2138                 }
2139         }
2140 }
2141
2142 int
2143 nv50_display_init(struct drm_device *dev)
2144 {
2145         struct nv50_core *core = nv50_disp(dev)->core;
2146         struct drm_encoder *encoder;
2147         struct drm_plane *plane;
2148
2149         core->func->init(core);
2150
2151         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2152                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2153                         struct nouveau_encoder *nv_encoder =
2154                                 nouveau_encoder(encoder);
2155                         nv50_mstm_init(nv_encoder->dp.mstm);
2156                 }
2157         }
2158
2159         drm_for_each_plane(plane, dev) {
2160                 struct nv50_wndw *wndw = nv50_wndw(plane);
2161                 if (plane->funcs != &nv50_wndw)
2162                         continue;
2163                 nv50_wndw_init(wndw);
2164         }
2165
2166         return 0;
2167 }
2168
2169 void
2170 nv50_display_destroy(struct drm_device *dev)
2171 {
2172         struct nv50_disp *disp = nv50_disp(dev);
2173
2174         nv50_core_del(&disp->core);
2175
2176         nouveau_bo_unmap(disp->sync);
2177         if (disp->sync)
2178                 nouveau_bo_unpin(disp->sync);
2179         nouveau_bo_ref(NULL, &disp->sync);
2180
2181         nouveau_display(dev)->priv = NULL;
2182         kfree(disp);
2183 }
2184
2185 int
2186 nv50_display_create(struct drm_device *dev)
2187 {
2188         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2189         struct nouveau_drm *drm = nouveau_drm(dev);
2190         struct dcb_table *dcb = &drm->vbios.dcb;
2191         struct drm_connector *connector, *tmp;
2192         struct nv50_disp *disp;
2193         struct dcb_output *dcbe;
2194         int crtcs, ret, i;
2195
2196         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2197         if (!disp)
2198                 return -ENOMEM;
2199
2200         mutex_init(&disp->mutex);
2201
2202         nouveau_display(dev)->priv = disp;
2203         nouveau_display(dev)->dtor = nv50_display_destroy;
2204         nouveau_display(dev)->init = nv50_display_init;
2205         nouveau_display(dev)->fini = nv50_display_fini;
2206         disp->disp = &nouveau_display(dev)->disp;
2207         dev->mode_config.funcs = &nv50_disp_func;
2208         dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP;
2209
2210         /* small shared memory area we use for notifiers and semaphores */
2211         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2212                              0, 0x0000, NULL, NULL, &disp->sync);
2213         if (!ret) {
2214                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2215                 if (!ret) {
2216                         ret = nouveau_bo_map(disp->sync);
2217                         if (ret)
2218                                 nouveau_bo_unpin(disp->sync);
2219                 }
2220                 if (ret)
2221                         nouveau_bo_ref(NULL, &disp->sync);
2222         }
2223
2224         if (ret)
2225                 goto out;
2226
2227         /* allocate master evo channel */
2228         ret = nv50_core_new(drm, &disp->core);
2229         if (ret)
2230                 goto out;
2231
2232         /* create crtc objects to represent the hw heads */
2233         if (disp->disp->object.oclass >= GV100_DISP)
2234                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2235         else
2236         if (disp->disp->object.oclass >= GF110_DISP)
2237                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2238         else
2239                 crtcs = 0x3;
2240
2241         for (i = 0; i < fls(crtcs); i++) {
2242                 if (!(crtcs & (1 << i)))
2243                         continue;
2244                 ret = nv50_head_create(dev, i);
2245                 if (ret)
2246                         goto out;
2247         }
2248
2249         /* create encoder/connector objects based on VBIOS DCB table */
2250         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2251                 connector = nouveau_connector_create(dev, dcbe->connector);
2252                 if (IS_ERR(connector))
2253                         continue;
2254
2255                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2256                         switch (dcbe->type) {
2257                         case DCB_OUTPUT_TMDS:
2258                         case DCB_OUTPUT_LVDS:
2259                         case DCB_OUTPUT_DP:
2260                                 ret = nv50_sor_create(connector, dcbe);
2261                                 break;
2262                         case DCB_OUTPUT_ANALOG:
2263                                 ret = nv50_dac_create(connector, dcbe);
2264                                 break;
2265                         default:
2266                                 ret = -ENODEV;
2267                                 break;
2268                         }
2269                 } else {
2270                         ret = nv50_pior_create(connector, dcbe);
2271                 }
2272
2273                 if (ret) {
2274                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2275                                      dcbe->location, dcbe->type,
2276                                      ffs(dcbe->or) - 1, ret);
2277                         ret = 0;
2278                 }
2279         }
2280
2281         /* cull any connectors we created that don't have an encoder */
2282         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2283                 if (connector->encoder_ids[0])
2284                         continue;
2285
2286                 NV_WARN(drm, "%s has no encoders, removing\n",
2287                         connector->name);
2288                 connector->funcs->destroy(connector);
2289         }
2290
2291         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2292         dev->vblank_disable_immediate = true;
2293
2294 out:
2295         if (ret)
2296                 nv50_display_destroy(dev);
2297         return ret;
2298 }