drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_dp_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_fb_helper.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <drm/drm_vblank.h>
  41
  42 #include <nvif/class.h>
  43 #include <nvif/cl0002.h>
  44 #include <nvif/cl5070.h>
  45 #include <nvif/cl507d.h>
  46 #include <nvif/event.h>
  47
  48 #include "nouveau_drv.h"
  49 #include "nouveau_dma.h"
  50 #include "nouveau_gem.h"
  51 #include "nouveau_connector.h"
  52 #include "nouveau_encoder.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55
  56 #include <subdev/bios/dp.h>
  57
  58 /******************************************************************************
  59  * Atomic state
  60  *****************************************************************************/
  61
  62 struct nv50_outp_atom {
  63         struct list_head head;
  64
  65         struct drm_encoder *encoder;
  66         bool flush_disable;
  67
  68         union nv50_outp_atom_mask {
  69                 struct {
  70                         bool ctrl:1;
  71                 };
  72                 u8 mask;
  73         } set, clr;
  74 };
  75
  76 /******************************************************************************
  77  * EVO channel
  78  *****************************************************************************/
  79
  80 static int
  81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  82                  const s32 *oclass, u8 head, void *data, u32 size,
  83                  struct nv50_chan *chan)
  84 {
  85         struct nvif_sclass *sclass;
  86         int ret, i, n;
  87
  88         chan->device = device;
  89
  90         ret = n = nvif_object_sclass_get(disp, &sclass);
  91         if (ret < 0)
  92                 return ret;
  93
  94         while (oclass[0]) {
  95                 for (i = 0; i < n; i++) {
  96                         if (sclass[i].oclass == oclass[0]) {
  97                                 ret = nvif_object_init(disp, 0, oclass[0],
  98                                                        data, size, &chan->user);
  99                                 if (ret == 0)
 100                                         nvif_object_map(&chan->user, NULL, 0);
 101                                 nvif_object_sclass_put(&sclass);
 102                                 return ret;
 103                         }
 104                 }
 105                 oclass++;
 106         }
 107
 108         nvif_object_sclass_put(&sclass);
 109         return -ENOSYS;
 110 }
 111
 112 static void
 113 nv50_chan_destroy(struct nv50_chan *chan)
 114 {
 115         nvif_object_fini(&chan->user);
 116 }
 117
 118 /******************************************************************************
 119  * DMA EVO channel
 120  *****************************************************************************/
 121
 122 void
 123 nv50_dmac_destroy(struct nv50_dmac *dmac)
 124 {
 125         nvif_object_fini(&dmac->vram);
 126         nvif_object_fini(&dmac->sync);
 127
 128         nv50_chan_destroy(&dmac->base);
 129
 130         nvif_mem_fini(&dmac->push);
 131 }
 132
 133 int
 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 135                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 136                  struct nv50_dmac *dmac)
 137 {
 138         struct nouveau_cli *cli = (void *)device->object.client;
 139         struct nv50_disp_core_channel_dma_v0 *args = data;
 140         u8 type = NVIF_MEM_COHERENT;
 141         int ret;
 142
 143         mutex_init(&dmac->lock);
 144
 145         /* Pascal added support for 47-bit physical addresses, but some
 146          * parts of EVO still only accept 40-bit PAs.
 147          *
 148          * To avoid issues on systems with large amounts of RAM, and on
 149          * systems where an IOMMU maps pages at a high address, we need
 150          * to allocate push buffers in VRAM instead.
 151          *
 152          * This appears to match NVIDIA's behaviour on Pascal.
 153          */
 154         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 155                 type |= NVIF_MEM_VRAM;
 156
 157         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 158         if (ret)
 159                 return ret;
 160
 161         dmac->ptr = dmac->push.object.map.ptr;
 162
 163         args->pushbuf = nvif_handle(&dmac->push.object);
 164
 165         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 166                                &dmac->base);
 167         if (ret)
 168                 return ret;
 169
 170         if (!syncbuf)
 171                 return 0;
 172
 173         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 174                                &(struct nv_dma_v0) {
 175                                         .target = NV_DMA_V0_TARGET_VRAM,
 176                                         .access = NV_DMA_V0_ACCESS_RDWR,
 177                                         .start = syncbuf + 0x0000,
 178                                         .limit = syncbuf + 0x0fff,
 179                                }, sizeof(struct nv_dma_v0),
 180                                &dmac->sync);
 181         if (ret)
 182                 return ret;
 183
 184         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 185                                &(struct nv_dma_v0) {
 186                                         .target = NV_DMA_V0_TARGET_VRAM,
 187                                         .access = NV_DMA_V0_ACCESS_RDWR,
 188                                         .start = 0,
 189                                         .limit = device->info.ram_user - 1,
 190                                }, sizeof(struct nv_dma_v0),
 191                                &dmac->vram);
 192         if (ret)
 193                 return ret;
 194
 195         return ret;
 196 }
 197
 198 /******************************************************************************
 199  * EVO channel helpers
 200  *****************************************************************************/
 201 static void
 202 evo_flush(struct nv50_dmac *dmac)
 203 {
 204         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 205          * writes have been flushed right through to VRAM before writing PUT.
 206          */
 207         if (dmac->push.type & NVIF_MEM_VRAM) {
 208                 struct nvif_device *device = dmac->base.device;
 209                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 210                 nvif_msec(device, 2000,
 211                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 212                                 break;
 213                 );
 214         }
 215 }
 216
 217 u32 *
 218 evo_wait(struct nv50_dmac *evoc, int nr)
 219 {
 220         struct nv50_dmac *dmac = evoc;
 221         struct nvif_device *device = dmac->base.device;
 222         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 223
 224         mutex_lock(&dmac->lock);
 225         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 226                 dmac->ptr[put] = 0x20000000;
 227                 evo_flush(dmac);
 228
 229                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 230                 if (nvif_msec(device, 2000,
 231                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 232                                 break;
 233                 ) < 0) {
 234                         mutex_unlock(&dmac->lock);
 235                         pr_err("nouveau: evo channel stalled\n");
 236                         return NULL;
 237                 }
 238
 239                 put = 0;
 240         }
 241
 242         return dmac->ptr + put;
 243 }
 244
 245 void
 246 evo_kick(u32 *push, struct nv50_dmac *evoc)
 247 {
 248         struct nv50_dmac *dmac = evoc;
 249
 250         evo_flush(dmac);
 251
 252         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 253         mutex_unlock(&dmac->lock);
 254 }
 255
 256 /******************************************************************************
 257  * Output path helpers
 258  *****************************************************************************/
 259 static void
 260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 261 {
 262         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 263         struct {
 264                 struct nv50_disp_mthd_v1 base;
 265         } args = {
 266                 .base.version = 1,
 267                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 268                 .base.hasht  = nv_encoder->dcb->hasht,
 269                 .base.hashm  = nv_encoder->dcb->hashm,
 270         };
 271
 272         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 273         nv_encoder->or = -1;
 274         nv_encoder->link = 0;
 275 }
 276
 277 static int
 278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 279 {
 280         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 281         struct nv50_disp *disp = nv50_disp(drm->dev);
 282         struct {
 283                 struct nv50_disp_mthd_v1 base;
 284                 struct nv50_disp_acquire_v0 info;
 285         } args = {
 286                 .base.version = 1,
 287                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 288                 .base.hasht  = nv_encoder->dcb->hasht,
 289                 .base.hashm  = nv_encoder->dcb->hashm,
 290         };
 291         int ret;
 292
 293         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 294         if (ret) {
 295                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 296                 return ret;
 297         }
 298
 299         nv_encoder->or = args.info.or;
 300         nv_encoder->link = args.info.link;
 301         return 0;
 302 }
 303
 304 static int
 305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 306                             struct drm_crtc_state *crtc_state,
 307                             struct drm_connector_state *conn_state,
 308                             struct drm_display_mode *native_mode)
 309 {
 310         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 311         struct drm_display_mode *mode = &crtc_state->mode;
 312         struct drm_connector *connector = conn_state->connector;
 313         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 314         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 315
 316         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 317         asyc->scaler.full = false;
 318         if (!native_mode)
 319                 return 0;
 320
 321         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 322                 switch (connector->connector_type) {
 323                 case DRM_MODE_CONNECTOR_LVDS:
 324                 case DRM_MODE_CONNECTOR_eDP:
 325                         /* Don't force scaler for EDID modes with
 326                          * same size as the native one (e.g. different
 327                          * refresh rate)
 328                          */
 329                         if (adjusted_mode->hdisplay == native_mode->hdisplay &&
 330                             adjusted_mode->vdisplay == native_mode->vdisplay &&
 331                             adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
 332                                 break;
 333                         mode = native_mode;
 334                         asyc->scaler.full = true;
 335                         break;
 336                 default:
 337                         break;
 338                 }
 339         } else {
 340                 mode = native_mode;
 341         }
 342
 343         if (!drm_mode_equal(adjusted_mode, mode)) {
 344                 drm_mode_copy(adjusted_mode, mode);
 345                 crtc_state->mode_changed = true;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int
 352 nv50_outp_atomic_check(struct drm_encoder *encoder,
 353                        struct drm_crtc_state *crtc_state,
 354                        struct drm_connector_state *conn_state)
 355 {
 356         struct nouveau_connector *nv_connector =
 357                 nouveau_connector(conn_state->connector);
 358         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 359                                            nv_connector->native_mode);
 360 }
 361
 362 /******************************************************************************
 363  * DAC
 364  *****************************************************************************/
 365 static void
 366 nv50_dac_disable(struct drm_encoder *encoder)
 367 {
 368         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 369         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 370         if (nv_encoder->crtc)
 371                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 372         nv_encoder->crtc = NULL;
 373         nv50_outp_release(nv_encoder);
 374 }
 375
 376 static void
 377 nv50_dac_enable(struct drm_encoder *encoder)
 378 {
 379         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 380         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 381         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 382         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 383
 384         nv50_outp_acquire(nv_encoder);
 385
 386         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 387         asyh->or.depth = 0;
 388
 389         nv_encoder->crtc = encoder->crtc;
 390 }
 391
 392 static enum drm_connector_status
 393 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 394 {
 395         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 396         struct nv50_disp *disp = nv50_disp(encoder->dev);
 397         struct {
 398                 struct nv50_disp_mthd_v1 base;
 399                 struct nv50_disp_dac_load_v0 load;
 400         } args = {
 401                 .base.version = 1,
 402                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 403                 .base.hasht  = nv_encoder->dcb->hasht,
 404                 .base.hashm  = nv_encoder->dcb->hashm,
 405         };
 406         int ret;
 407
 408         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 409         if (args.load.data == 0)
 410                 args.load.data = 340;
 411
 412         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 413         if (ret || !args.load.load)
 414                 return connector_status_disconnected;
 415
 416         return connector_status_connected;
 417 }
 418
 419 static const struct drm_encoder_helper_funcs
 420 nv50_dac_help = {
 421         .atomic_check = nv50_outp_atomic_check,
 422         .enable = nv50_dac_enable,
 423         .disable = nv50_dac_disable,
 424         .detect = nv50_dac_detect
 425 };
 426
 427 static void
 428 nv50_dac_destroy(struct drm_encoder *encoder)
 429 {
 430         drm_encoder_cleanup(encoder);
 431         kfree(encoder);
 432 }
 433
 434 static const struct drm_encoder_funcs
 435 nv50_dac_func = {
 436         .destroy = nv50_dac_destroy,
 437 };
 438
 439 static int
 440 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 441 {
 442         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 443         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 444         struct nvkm_i2c_bus *bus;
 445         struct nouveau_encoder *nv_encoder;
 446         struct drm_encoder *encoder;
 447         int type = DRM_MODE_ENCODER_DAC;
 448
 449         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 450         if (!nv_encoder)
 451                 return -ENOMEM;
 452         nv_encoder->dcb = dcbe;
 453
 454         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 455         if (bus)
 456                 nv_encoder->i2c = &bus->i2c;
 457
 458         encoder = to_drm_encoder(nv_encoder);
 459         encoder->possible_crtcs = dcbe->heads;
 460         encoder->possible_clones = 0;
 461         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 462                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 463         drm_encoder_helper_add(encoder, &nv50_dac_help);
 464
 465         drm_connector_attach_encoder(connector, encoder);
 466         return 0;
 467 }
 468
 469 /******************************************************************************
 470  * Audio
 471  *****************************************************************************/
 472 static void
 473 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 474 {
 475         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 476         struct nv50_disp *disp = nv50_disp(encoder->dev);
 477         struct {
 478                 struct nv50_disp_mthd_v1 base;
 479                 struct nv50_disp_sor_hda_eld_v0 eld;
 480         } args = {
 481                 .base.version = 1,
 482                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 483                 .base.hasht   = nv_encoder->dcb->hasht,
 484                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 485                                 (0x0100 << nv_crtc->index),
 486         };
 487
 488         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 489 }
 490
 491 static void
 492 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 493 {
 494         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 495         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 496         struct nouveau_connector *nv_connector;
 497         struct nv50_disp *disp = nv50_disp(encoder->dev);
 498         struct __packed {
 499                 struct {
 500                         struct nv50_disp_mthd_v1 mthd;
 501                         struct nv50_disp_sor_hda_eld_v0 eld;
 502                 } base;
 503                 u8 data[sizeof(nv_connector->base.eld)];
 504         } args = {
 505                 .base.mthd.version = 1,
 506                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 507                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 508                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 509                                      (0x0100 << nv_crtc->index),
 510         };
 511
 512         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 513         if (!drm_detect_monitor_audio(nv_connector->edid))
 514                 return;
 515
 516         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 517
 518         nvif_mthd(&disp->disp->object, 0, &args,
 519                   sizeof(args.base) + drm_eld_size(args.data));
 520 }
 521
 522 /******************************************************************************
 523  * HDMI
 524  *****************************************************************************/
 525 static void
 526 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 527 {
 528         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 529         struct nv50_disp *disp = nv50_disp(encoder->dev);
 530         struct {
 531                 struct nv50_disp_mthd_v1 base;
 532                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 533         } args = {
 534                 .base.version = 1,
 535                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 536                 .base.hasht  = nv_encoder->dcb->hasht,
 537                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 538                                (0x0100 << nv_crtc->index),
 539         };
 540
 541         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 542 }
 543
 544 static void
 545 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 546 {
 547         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 548         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 549         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 550         struct nv50_disp *disp = nv50_disp(encoder->dev);
 551         struct {
 552                 struct nv50_disp_mthd_v1 base;
 553                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 554                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 555         } args = {
 556                 .base.version = 1,
 557                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 558                 .base.hasht  = nv_encoder->dcb->hasht,
 559                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 560                                (0x0100 << nv_crtc->index),
 561                 .pwr.state = 1,
 562                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 563         };
 564         struct nouveau_connector *nv_connector;
 565         struct drm_hdmi_info *hdmi;
 566         u32 max_ac_packet;
 567         union hdmi_infoframe avi_frame;
 568         union hdmi_infoframe vendor_frame;
 569         bool high_tmds_clock_ratio = false, scrambling = false;
 570         u8 config;
 571         int ret;
 572         int size;
 573
 574         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 575         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 576                 return;
 577
 578         hdmi = &nv_connector->base.display_info.hdmi;
 579
 580         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 581                                                        &nv_connector->base, mode);
 582         if (!ret) {
 583                 /* We have an AVI InfoFrame, populate it to the display */
 584                 args.pwr.avi_infoframe_length
 585                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 586         }
 587
 588         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 589                                                           &nv_connector->base, mode);
 590         if (!ret) {
 591                 /* We have a Vendor InfoFrame, populate it to the display */
 592                 args.pwr.vendor_infoframe_length
 593                         = hdmi_infoframe_pack(&vendor_frame,
 594                                               args.infoframes
 595                                               + args.pwr.avi_infoframe_length,
 596                                               17);
 597         }
 598
 599         max_ac_packet  = mode->htotal - mode->hdisplay;
 600         max_ac_packet -= args.pwr.rekey;
 601         max_ac_packet -= 18; /* constant from tegra */
 602         args.pwr.max_ac_packet = max_ac_packet / 32;
 603
 604         if (hdmi->scdc.scrambling.supported) {
 605                 high_tmds_clock_ratio = mode->clock > 340000;
 606                 scrambling = high_tmds_clock_ratio ||
 607                         hdmi->scdc.scrambling.low_rates;
 608         }
 609
 610         args.pwr.scdc =
 611                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 612                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 613
 614         size = sizeof(args.base)
 615                 + sizeof(args.pwr)
 616                 + args.pwr.avi_infoframe_length
 617                 + args.pwr.vendor_infoframe_length;
 618         nvif_mthd(&disp->disp->object, 0, &args, size);
 619
 620         nv50_audio_enable(encoder, mode);
 621
 622         /* If SCDC is supported by the downstream monitor, update
 623          * divider / scrambling settings to what we programmed above.
 624          */
 625         if (!hdmi->scdc.scrambling.supported)
 626                 return;
 627
 628         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 629         if (ret < 0) {
 630                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 631                 return;
 632         }
 633         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 634         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 635         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 636         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 637         if (ret < 0)
 638                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 639                          config, ret);
 640 }
 641
 642 /******************************************************************************
 643  * MST
 644  *****************************************************************************/
 645 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 646 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 647 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 648
 649 struct nv50_mstm {
 650         struct nouveau_encoder *outp;
 651
 652         struct drm_dp_mst_topology_mgr mgr;
 653         struct nv50_msto *msto[4];
 654
 655         bool modified;
 656         bool disabled;
 657         int links;
 658 };
 659
 660 struct nv50_mstc {
 661         struct nv50_mstm *mstm;
 662         struct drm_dp_mst_port *port;
 663         struct drm_connector connector;
 664
 665         struct drm_display_mode *native;
 666         struct edid *edid;
 667 };
 668
 669 struct nv50_msto {
 670         struct drm_encoder encoder;
 671
 672         struct nv50_head *head;
 673         struct nv50_mstc *mstc;
 674         bool disabled;
 675 };
 676
 677 static struct drm_dp_payload *
 678 nv50_msto_payload(struct nv50_msto *msto)
 679 {
 680         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 681         struct nv50_mstc *mstc = msto->mstc;
 682         struct nv50_mstm *mstm = mstc->mstm;
 683         int vcpi = mstc->port->vcpi.vcpi, i;
 684
 685         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 686
 687         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 688         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 689                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 690                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 691                           mstm->outp->base.base.name, i, payload->vcpi,
 692                           payload->start_slot, payload->num_slots);
 693         }
 694
 695         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 696                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 697                 if (payload->vcpi == vcpi)
 698                         return payload;
 699         }
 700
 701         return NULL;
 702 }
 703
 704 static void
 705 nv50_msto_cleanup(struct nv50_msto *msto)
 706 {
 707         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 708         struct nv50_mstc *mstc = msto->mstc;
 709         struct nv50_mstm *mstm = mstc->mstm;
 710
 711         if (!msto->disabled)
 712                 return;
 713
 714         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 715
 716         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 717
 718         msto->mstc = NULL;
 719         msto->head = NULL;
 720         msto->disabled = false;
 721 }
 722
 723 static void
 724 nv50_msto_prepare(struct nv50_msto *msto)
 725 {
 726         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 727         struct nv50_mstc *mstc = msto->mstc;
 728         struct nv50_mstm *mstm = mstc->mstm;
 729         struct {
 730                 struct nv50_disp_mthd_v1 base;
 731                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 732         } args = {
 733                 .base.version = 1,
 734                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 735                 .base.hasht  = mstm->outp->dcb->hasht,
 736                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 737                                (0x0100 << msto->head->base.index),
 738         };
 739
 740         mutex_lock(&mstm->mgr.payload_lock);
 741
 742         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 743         if (mstc->port->vcpi.vcpi > 0) {
 744                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 745                 if (payload) {
 746                         args.vcpi.start_slot = payload->start_slot;
 747                         args.vcpi.num_slots = payload->num_slots;
 748                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 749                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 750                 }
 751         }
 752
 753         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 754                   msto->encoder.name, msto->head->base.base.name,
 755                   args.vcpi.start_slot, args.vcpi.num_slots,
 756                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 757
 758         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 759         mutex_unlock(&mstm->mgr.payload_lock);
 760 }
 761
 762 static int
 763 nv50_msto_atomic_check(struct drm_encoder *encoder,
 764                        struct drm_crtc_state *crtc_state,
 765                        struct drm_connector_state *conn_state)
 766 {
 767         struct drm_atomic_state *state = crtc_state->state;
 768         struct drm_connector *connector = conn_state->connector;
 769         struct nv50_mstc *mstc = nv50_mstc(connector);
 770         struct nv50_mstm *mstm = mstc->mstm;
 771         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 772         int slots;
 773         int ret;
 774
 775         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 776                                           mstc->native);
 777         if (ret)
 778                 return ret;
 779
 780         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
 781                 return 0;
 782
 783         /*
 784          * When restoring duplicated states, we need to make sure that the bw
 785          * remains the same and avoid recalculating it, as the connector's bpc
 786          * may have changed after the state was duplicated
 787          */
 788         if (!state->duplicated) {
 789                 const int bpp = connector->display_info.bpc * 3;
 790                 const int clock = crtc_state->adjusted_mode.clock;
 791
 792                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp);
 793         }
 794
 795         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
 796                                               asyh->dp.pbn);
 797         if (slots < 0)
 798                 return slots;
 799
 800         asyh->dp.tu = slots;
 801
 802         return 0;
 803 }
 804
 805 static void
 806 nv50_msto_enable(struct drm_encoder *encoder)
 807 {
 808         struct nv50_head *head = nv50_head(encoder->crtc);
 809         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
 810         struct nv50_msto *msto = nv50_msto(encoder);
 811         struct nv50_mstc *mstc = NULL;
 812         struct nv50_mstm *mstm = NULL;
 813         struct drm_connector *connector;
 814         struct drm_connector_list_iter conn_iter;
 815         u8 proto, depth;
 816         bool r;
 817
 818         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 819         drm_for_each_connector_iter(connector, &conn_iter) {
 820                 if (connector->state->best_encoder == &msto->encoder) {
 821                         mstc = nv50_mstc(connector);
 822                         mstm = mstc->mstm;
 823                         break;
 824                 }
 825         }
 826         drm_connector_list_iter_end(&conn_iter);
 827
 828         if (WARN_ON(!mstc))
 829                 return;
 830
 831         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
 832                                      armh->dp.tu);
 833         if (!r)
 834                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
 835
 836         if (!mstm->links++)
 837                 nv50_outp_acquire(mstm->outp);
 838
 839         if (mstm->outp->link & 1)
 840                 proto = 0x8;
 841         else
 842                 proto = 0x9;
 843
 844         switch (mstc->connector.display_info.bpc) {
 845         case  6: depth = 0x2; break;
 846         case  8: depth = 0x5; break;
 847         case 10:
 848         default: depth = 0x6; break;
 849         }
 850
 851         mstm->outp->update(mstm->outp, head->base.index, armh, proto, depth);
 852
 853         msto->head = head;
 854         msto->mstc = mstc;
 855         mstm->modified = true;
 856 }
 857
 858 static void
 859 nv50_msto_disable(struct drm_encoder *encoder)
 860 {
 861         struct nv50_msto *msto = nv50_msto(encoder);
 862         struct nv50_mstc *mstc = msto->mstc;
 863         struct nv50_mstm *mstm = mstc->mstm;
 864
 865         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 866
 867         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 868         mstm->modified = true;
 869         if (!--mstm->links)
 870                 mstm->disabled = true;
 871         msto->disabled = true;
 872 }
 873
 874 static const struct drm_encoder_helper_funcs
 875 nv50_msto_help = {
 876         .disable = nv50_msto_disable,
 877         .enable = nv50_msto_enable,
 878         .atomic_check = nv50_msto_atomic_check,
 879 };
 880
 881 static void
 882 nv50_msto_destroy(struct drm_encoder *encoder)
 883 {
 884         struct nv50_msto *msto = nv50_msto(encoder);
 885         drm_encoder_cleanup(&msto->encoder);
 886         kfree(msto);
 887 }
 888
 889 static const struct drm_encoder_funcs
 890 nv50_msto = {
 891         .destroy = nv50_msto_destroy,
 892 };
 893
 894 static int
 895 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 896               struct nv50_msto **pmsto)
 897 {
 898         struct nv50_msto *msto;
 899         int ret;
 900
 901         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 902                 return -ENOMEM;
 903
 904         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 905                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 906         if (ret) {
 907                 kfree(*pmsto);
 908                 *pmsto = NULL;
 909                 return ret;
 910         }
 911
 912         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 913         msto->encoder.possible_crtcs = heads;
 914         return 0;
 915 }
 916
 917 static struct drm_encoder *
 918 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 919                               struct drm_connector_state *connector_state)
 920 {
 921         struct nv50_head *head = nv50_head(connector_state->crtc);
 922         struct nv50_mstc *mstc = nv50_mstc(connector);
 923
 924         return &mstc->mstm->msto[head->base.index]->encoder;
 925 }
 926
 927 static struct drm_encoder *
 928 nv50_mstc_best_encoder(struct drm_connector *connector)
 929 {
 930         struct nv50_mstc *mstc = nv50_mstc(connector);
 931
 932         return &mstc->mstm->msto[0]->encoder;
 933 }
 934
 935 static enum drm_mode_status
 936 nv50_mstc_mode_valid(struct drm_connector *connector,
 937                      struct drm_display_mode *mode)
 938 {
 939         return MODE_OK;
 940 }
 941
 942 static int
 943 nv50_mstc_get_modes(struct drm_connector *connector)
 944 {
 945         struct nv50_mstc *mstc = nv50_mstc(connector);
 946         int ret = 0;
 947
 948         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 949         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 950         if (mstc->edid)
 951                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 952
 953         if (!mstc->connector.display_info.bpc)
 954                 mstc->connector.display_info.bpc = 8;
 955
 956         if (mstc->native)
 957                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 958         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 959         return ret;
 960 }
 961
 962 static int
 963 nv50_mstc_atomic_check(struct drm_connector *connector,
 964                        struct drm_atomic_state *state)
 965 {
 966         struct nv50_mstc *mstc = nv50_mstc(connector);
 967         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
 968         struct drm_connector_state *new_conn_state =
 969                 drm_atomic_get_new_connector_state(state, connector);
 970         struct drm_connector_state *old_conn_state =
 971                 drm_atomic_get_old_connector_state(state, connector);
 972         struct drm_crtc_state *crtc_state;
 973         struct drm_crtc *new_crtc = new_conn_state->crtc;
 974
 975         if (!old_conn_state->crtc)
 976                 return 0;
 977
 978         /* We only want to free VCPI if this state disables the CRTC on this
 979          * connector
 980          */
 981         if (new_crtc) {
 982                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
 983
 984                 if (!crtc_state ||
 985                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
 986                     crtc_state->enable)
 987                         return 0;
 988         }
 989
 990         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
 991 }
 992
 993 static int
 994 nv50_mstc_detect(struct drm_connector *connector,
 995                  struct drm_modeset_acquire_ctx *ctx, bool force)
 996 {
 997         struct nv50_mstc *mstc = nv50_mstc(connector);
 998         int ret;
 999
1000         if (drm_connector_is_unregistered(connector))
1001                 return connector_status_disconnected;
1002
1003         ret = pm_runtime_get_sync(connector->dev->dev);
1004         if (ret < 0 && ret != -EACCES)
1005                 return connector_status_disconnected;
1006
1007         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1008                                      mstc->port);
1009
1010         pm_runtime_mark_last_busy(connector->dev->dev);
1011         pm_runtime_put_autosuspend(connector->dev->dev);
1012         return ret;
1013 }
1014
1015 static const struct drm_connector_helper_funcs
1016 nv50_mstc_help = {
1017         .get_modes = nv50_mstc_get_modes,
1018         .mode_valid = nv50_mstc_mode_valid,
1019         .best_encoder = nv50_mstc_best_encoder,
1020         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1021         .atomic_check = nv50_mstc_atomic_check,
1022         .detect_ctx = nv50_mstc_detect,
1023 };
1024
1025 static void
1026 nv50_mstc_destroy(struct drm_connector *connector)
1027 {
1028         struct nv50_mstc *mstc = nv50_mstc(connector);
1029
1030         drm_connector_cleanup(&mstc->connector);
1031         drm_dp_mst_put_port_malloc(mstc->port);
1032
1033         kfree(mstc);
1034 }
1035
1036 static const struct drm_connector_funcs
1037 nv50_mstc = {
1038         .reset = nouveau_conn_reset,
1039         .fill_modes = drm_helper_probe_single_connector_modes,
1040         .destroy = nv50_mstc_destroy,
1041         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1042         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1043         .atomic_set_property = nouveau_conn_atomic_set_property,
1044         .atomic_get_property = nouveau_conn_atomic_get_property,
1045 };
1046
1047 static int
1048 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1049               const char *path, struct nv50_mstc **pmstc)
1050 {
1051         struct drm_device *dev = mstm->outp->base.base.dev;
1052         struct nv50_mstc *mstc;
1053         int ret, i;
1054
1055         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1056                 return -ENOMEM;
1057         mstc->mstm = mstm;
1058         mstc->port = port;
1059
1060         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1061                                  DRM_MODE_CONNECTOR_DisplayPort);
1062         if (ret) {
1063                 kfree(*pmstc);
1064                 *pmstc = NULL;
1065                 return ret;
1066         }
1067
1068         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1069
1070         mstc->connector.funcs->reset(&mstc->connector);
1071         nouveau_conn_attach_properties(&mstc->connector);
1072
1073         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
1074                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1075
1076         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1077         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1078         drm_connector_set_path_property(&mstc->connector, path);
1079         drm_dp_mst_get_port_malloc(port);
1080         return 0;
1081 }
1082
1083 static void
1084 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1085 {
1086         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1087         struct drm_encoder *encoder;
1088         int ret;
1089
1090         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1091         ret = drm_dp_check_act_status(&mstm->mgr);
1092
1093         ret = drm_dp_update_payload_part2(&mstm->mgr);
1094
1095         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1096                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1097                         struct nv50_msto *msto = nv50_msto(encoder);
1098                         struct nv50_mstc *mstc = msto->mstc;
1099                         if (mstc && mstc->mstm == mstm)
1100                                 nv50_msto_cleanup(msto);
1101                 }
1102         }
1103
1104         mstm->modified = false;
1105 }
1106
1107 static void
1108 nv50_mstm_prepare(struct nv50_mstm *mstm)
1109 {
1110         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1111         struct drm_encoder *encoder;
1112         int ret;
1113
1114         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1115         ret = drm_dp_update_payload_part1(&mstm->mgr);
1116
1117         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1118                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1119                         struct nv50_msto *msto = nv50_msto(encoder);
1120                         struct nv50_mstc *mstc = msto->mstc;
1121                         if (mstc && mstc->mstm == mstm)
1122                                 nv50_msto_prepare(msto);
1123                 }
1124         }
1125
1126         if (mstm->disabled) {
1127                 if (!mstm->links)
1128                         nv50_outp_release(mstm->outp);
1129                 mstm->disabled = false;
1130         }
1131 }
1132
1133 static void
1134 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1135                             struct drm_connector *connector)
1136 {
1137         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1138         struct nv50_mstc *mstc = nv50_mstc(connector);
1139
1140         drm_connector_unregister(&mstc->connector);
1141
1142         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1143
1144         drm_connector_put(&mstc->connector);
1145 }
1146
1147 static void
1148 nv50_mstm_register_connector(struct drm_connector *connector)
1149 {
1150         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1151
1152         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1153
1154         drm_connector_register(connector);
1155 }
1156
1157 static struct drm_connector *
1158 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1159                         struct drm_dp_mst_port *port, const char *path)
1160 {
1161         struct nv50_mstm *mstm = nv50_mstm(mgr);
1162         struct nv50_mstc *mstc;
1163         int ret;
1164
1165         ret = nv50_mstc_new(mstm, port, path, &mstc);
1166         if (ret)
1167                 return NULL;
1168
1169         return &mstc->connector;
1170 }
1171
1172 static const struct drm_dp_mst_topology_cbs
1173 nv50_mstm = {
1174         .add_connector = nv50_mstm_add_connector,
1175         .register_connector = nv50_mstm_register_connector,
1176         .destroy_connector = nv50_mstm_destroy_connector,
1177 };
1178
1179 void
1180 nv50_mstm_service(struct nv50_mstm *mstm)
1181 {
1182         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1183         bool handled = true;
1184         int ret;
1185         u8 esi[8] = {};
1186
1187         if (!aux)
1188                 return;
1189
1190         while (handled) {
1191                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1192                 if (ret != 8) {
1193                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1194                         return;
1195                 }
1196
1197                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1198                 if (!handled)
1199                         break;
1200
1201                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1202         }
1203 }
1204
1205 void
1206 nv50_mstm_remove(struct nv50_mstm *mstm)
1207 {
1208         if (mstm)
1209                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1210 }
1211
1212 static int
1213 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1214 {
1215         struct nouveau_encoder *outp = mstm->outp;
1216         struct {
1217                 struct nv50_disp_mthd_v1 base;
1218                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1219         } args = {
1220                 .base.version = 1,
1221                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1222                 .base.hasht = outp->dcb->hasht,
1223                 .base.hashm = outp->dcb->hashm,
1224                 .mst.state = state,
1225         };
1226         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1227         struct nvif_object *disp = &drm->display->disp.object;
1228         int ret;
1229
1230         if (dpcd >= 0x12) {
1231                 /* Even if we're enabling MST, start with disabling the
1232                  * branching unit to clear any sink-side MST topology state
1233                  * that wasn't set by us
1234                  */
1235                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1236                 if (ret < 0)
1237                         return ret;
1238
1239                 if (state) {
1240                         /* Now, start initializing */
1241                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1242                                                  DP_MST_EN);
1243                         if (ret < 0)
1244                                 return ret;
1245                 }
1246         }
1247
1248         return nvif_mthd(disp, 0, &args, sizeof(args));
1249 }
1250
1251 int
1252 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1253 {
1254         struct drm_dp_aux *aux;
1255         int ret;
1256         bool old_state, new_state;
1257         u8 mstm_ctrl;
1258
1259         if (!mstm)
1260                 return 0;
1261
1262         mutex_lock(&mstm->mgr.lock);
1263
1264         old_state = mstm->mgr.mst_state;
1265         new_state = old_state;
1266         aux = mstm->mgr.aux;
1267
1268         if (old_state) {
1269                 /* Just check that the MST hub is still as we expect it */
1270                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1271                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1272                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1273                         new_state = false;
1274                 }
1275         } else if (dpcd[0] >= 0x12) {
1276                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1277                 if (ret < 0)
1278                         goto probe_error;
1279
1280                 if (!(dpcd[1] & DP_MST_CAP))
1281                         dpcd[0] = 0x11;
1282                 else
1283                         new_state = allow;
1284         }
1285
1286         if (new_state == old_state) {
1287                 mutex_unlock(&mstm->mgr.lock);
1288                 return new_state;
1289         }
1290
1291         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1292         if (ret)
1293                 goto probe_error;
1294
1295         mutex_unlock(&mstm->mgr.lock);
1296
1297         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1298         if (ret)
1299                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1300
1301         return new_state;
1302
1303 probe_error:
1304         mutex_unlock(&mstm->mgr.lock);
1305         return ret;
1306 }
1307
1308 static void
1309 nv50_mstm_fini(struct nv50_mstm *mstm)
1310 {
1311         if (mstm && mstm->mgr.mst_state)
1312                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1313 }
1314
1315 static void
1316 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1317 {
1318         int ret;
1319
1320         if (!mstm || !mstm->mgr.mst_state)
1321                 return;
1322
1323         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1324         if (ret == -1) {
1325                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1326                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1327         }
1328 }
1329
1330 static void
1331 nv50_mstm_del(struct nv50_mstm **pmstm)
1332 {
1333         struct nv50_mstm *mstm = *pmstm;
1334         if (mstm) {
1335                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1336                 kfree(*pmstm);
1337                 *pmstm = NULL;
1338         }
1339 }
1340
1341 static int
1342 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1343               int conn_base_id, struct nv50_mstm **pmstm)
1344 {
1345         const int max_payloads = hweight8(outp->dcb->heads);
1346         struct drm_device *dev = outp->base.base.dev;
1347         struct nv50_mstm *mstm;
1348         int ret, i;
1349         u8 dpcd;
1350
1351         /* This is a workaround for some monitors not functioning
1352          * correctly in MST mode on initial module load.  I think
1353          * some bad interaction with the VBIOS may be responsible.
1354          *
1355          * A good ol' off and on again seems to work here ;)
1356          */
1357         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1358         if (ret >= 0 && dpcd >= 0x12)
1359                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1360
1361         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1362                 return -ENOMEM;
1363         mstm->outp = outp;
1364         mstm->mgr.cbs = &nv50_mstm;
1365
1366         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1367                                            max_payloads, conn_base_id);
1368         if (ret)
1369                 return ret;
1370
1371         for (i = 0; i < max_payloads; i++) {
1372                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1373                                     i, &mstm->msto[i]);
1374                 if (ret)
1375                         return ret;
1376         }
1377
1378         return 0;
1379 }
1380
1381 /******************************************************************************
1382  * SOR
1383  *****************************************************************************/
1384 static void
1385 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1386                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1387 {
1388         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1389         struct nv50_core *core = disp->core;
1390
1391         if (!asyh) {
1392                 nv_encoder->ctrl &= ~BIT(head);
1393                 if (!(nv_encoder->ctrl & 0x0000000f))
1394                         nv_encoder->ctrl = 0;
1395         } else {
1396                 nv_encoder->ctrl |= proto << 8;
1397                 nv_encoder->ctrl |= BIT(head);
1398                 asyh->or.depth = depth;
1399         }
1400
1401         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1402 }
1403
1404 static void
1405 nv50_sor_disable(struct drm_encoder *encoder)
1406 {
1407         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1408         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1409
1410         nv_encoder->crtc = NULL;
1411
1412         if (nv_crtc) {
1413                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1414                 u8 pwr;
1415
1416                 if (aux) {
1417                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1418                         if (ret == 0) {
1419                                 pwr &= ~DP_SET_POWER_MASK;
1420                                 pwr |=  DP_SET_POWER_D3;
1421                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1422                         }
1423                 }
1424
1425                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1426                 nv50_audio_disable(encoder, nv_crtc);
1427                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1428                 nv50_outp_release(nv_encoder);
1429         }
1430 }
1431
1432 static void
1433 nv50_sor_enable(struct drm_encoder *encoder)
1434 {
1435         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1436         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1437         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1438         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1439         struct {
1440                 struct nv50_disp_mthd_v1 base;
1441                 struct nv50_disp_sor_lvds_script_v0 lvds;
1442         } lvds = {
1443                 .base.version = 1,
1444                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1445                 .base.hasht   = nv_encoder->dcb->hasht,
1446                 .base.hashm   = nv_encoder->dcb->hashm,
1447         };
1448         struct nv50_disp *disp = nv50_disp(encoder->dev);
1449         struct drm_device *dev = encoder->dev;
1450         struct nouveau_drm *drm = nouveau_drm(dev);
1451         struct nouveau_connector *nv_connector;
1452         struct nvbios *bios = &drm->vbios;
1453         u8 proto = 0xf;
1454         u8 depth = 0x0;
1455
1456         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1457         nv_encoder->crtc = encoder->crtc;
1458         nv50_outp_acquire(nv_encoder);
1459
1460         switch (nv_encoder->dcb->type) {
1461         case DCB_OUTPUT_TMDS:
1462                 if (nv_encoder->link & 1) {
1463                         proto = 0x1;
1464                         /* Only enable dual-link if:
1465                          *  - Need to (i.e. rate > 165MHz)
1466                          *  - DCB says we can
1467                          *  - Not an HDMI monitor, since there's no dual-link
1468                          *    on HDMI.
1469                          */
1470                         if (mode->clock >= 165000 &&
1471                             nv_encoder->dcb->duallink_possible &&
1472                             !drm_detect_hdmi_monitor(nv_connector->edid))
1473                                 proto |= 0x4;
1474                 } else {
1475                         proto = 0x2;
1476                 }
1477
1478                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1479                 break;
1480         case DCB_OUTPUT_LVDS:
1481                 proto = 0x0;
1482
1483                 if (bios->fp_no_ddc) {
1484                         if (bios->fp.dual_link)
1485                                 lvds.lvds.script |= 0x0100;
1486                         if (bios->fp.if_is_24bit)
1487                                 lvds.lvds.script |= 0x0200;
1488                 } else {
1489                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1490                                 if (((u8 *)nv_connector->edid)[121] == 2)
1491                                         lvds.lvds.script |= 0x0100;
1492                         } else
1493                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1494                                 lvds.lvds.script |= 0x0100;
1495                         }
1496
1497                         if (lvds.lvds.script & 0x0100) {
1498                                 if (bios->fp.strapless_is_24bit & 2)
1499                                         lvds.lvds.script |= 0x0200;
1500                         } else {
1501                                 if (bios->fp.strapless_is_24bit & 1)
1502                                         lvds.lvds.script |= 0x0200;
1503                         }
1504
1505                         if (nv_connector->base.display_info.bpc == 8)
1506                                 lvds.lvds.script |= 0x0200;
1507                 }
1508
1509                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1510                 break;
1511         case DCB_OUTPUT_DP:
1512                 if (nv_connector->base.display_info.bpc == 6)
1513                         depth = 0x2;
1514                 else
1515                 if (nv_connector->base.display_info.bpc == 8)
1516                         depth = 0x5;
1517                 else
1518                         depth = 0x6;
1519
1520                 if (nv_encoder->link & 1)
1521                         proto = 0x8;
1522                 else
1523                         proto = 0x9;
1524
1525                 nv50_audio_enable(encoder, mode);
1526                 break;
1527         default:
1528                 BUG();
1529                 break;
1530         }
1531
1532         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1533 }
1534
1535 static const struct drm_encoder_helper_funcs
1536 nv50_sor_help = {
1537         .atomic_check = nv50_outp_atomic_check,
1538         .enable = nv50_sor_enable,
1539         .disable = nv50_sor_disable,
1540 };
1541
1542 static void
1543 nv50_sor_destroy(struct drm_encoder *encoder)
1544 {
1545         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1546         nv50_mstm_del(&nv_encoder->dp.mstm);
1547         drm_encoder_cleanup(encoder);
1548         kfree(encoder);
1549 }
1550
1551 static const struct drm_encoder_funcs
1552 nv50_sor_func = {
1553         .destroy = nv50_sor_destroy,
1554 };
1555
1556 static int
1557 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1558 {
1559         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1560         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1561         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1562         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1563         struct nouveau_encoder *nv_encoder;
1564         struct drm_encoder *encoder;
1565         u8 ver, hdr, cnt, len;
1566         u32 data;
1567         int type, ret;
1568
1569         switch (dcbe->type) {
1570         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1571         case DCB_OUTPUT_TMDS:
1572         case DCB_OUTPUT_DP:
1573         default:
1574                 type = DRM_MODE_ENCODER_TMDS;
1575                 break;
1576         }
1577
1578         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1579         if (!nv_encoder)
1580                 return -ENOMEM;
1581         nv_encoder->dcb = dcbe;
1582         nv_encoder->update = nv50_sor_update;
1583
1584         encoder = to_drm_encoder(nv_encoder);
1585         encoder->possible_crtcs = dcbe->heads;
1586         encoder->possible_clones = 0;
1587         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1588                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1589         drm_encoder_helper_add(encoder, &nv50_sor_help);
1590
1591         drm_connector_attach_encoder(connector, encoder);
1592
1593         if (dcbe->type == DCB_OUTPUT_DP) {
1594                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1595                 struct nvkm_i2c_aux *aux =
1596                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1597                 if (aux) {
1598                         if (disp->disp->object.oclass < GF110_DISP) {
1599                                 /* HW has no support for address-only
1600                                  * transactions, so we're required to
1601                                  * use custom I2C-over-AUX code.
1602                                  */
1603                                 nv_encoder->i2c = &aux->i2c;
1604                         } else {
1605                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1606                         }
1607                         nv_encoder->aux = aux;
1608                 }
1609
1610                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1611                     (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1612                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1613                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1614                                             nv_connector->base.base.id,
1615                                             &nv_encoder->dp.mstm);
1616                         if (ret)
1617                                 return ret;
1618                 }
1619         } else {
1620                 struct nvkm_i2c_bus *bus =
1621                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1622                 if (bus)
1623                         nv_encoder->i2c = &bus->i2c;
1624         }
1625
1626         return 0;
1627 }
1628
1629 /******************************************************************************
1630  * PIOR
1631  *****************************************************************************/
1632 static int
1633 nv50_pior_atomic_check(struct drm_encoder *encoder,
1634                        struct drm_crtc_state *crtc_state,
1635                        struct drm_connector_state *conn_state)
1636 {
1637         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1638         if (ret)
1639                 return ret;
1640         crtc_state->adjusted_mode.clock *= 2;
1641         return 0;
1642 }
1643
1644 static void
1645 nv50_pior_disable(struct drm_encoder *encoder)
1646 {
1647         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1648         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1649         if (nv_encoder->crtc)
1650                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1651         nv_encoder->crtc = NULL;
1652         nv50_outp_release(nv_encoder);
1653 }
1654
1655 static void
1656 nv50_pior_enable(struct drm_encoder *encoder)
1657 {
1658         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1659         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1660         struct nouveau_connector *nv_connector;
1661         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1662         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1663         u8 owner = 1 << nv_crtc->index;
1664         u8 proto;
1665
1666         nv50_outp_acquire(nv_encoder);
1667
1668         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1669         switch (nv_connector->base.display_info.bpc) {
1670         case 10: asyh->or.depth = 0x6; break;
1671         case  8: asyh->or.depth = 0x5; break;
1672         case  6: asyh->or.depth = 0x2; break;
1673         default: asyh->or.depth = 0x0; break;
1674         }
1675
1676         switch (nv_encoder->dcb->type) {
1677         case DCB_OUTPUT_TMDS:
1678         case DCB_OUTPUT_DP:
1679                 proto = 0x0;
1680                 break;
1681         default:
1682                 BUG();
1683                 break;
1684         }
1685
1686         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1687         nv_encoder->crtc = encoder->crtc;
1688 }
1689
1690 static const struct drm_encoder_helper_funcs
1691 nv50_pior_help = {
1692         .atomic_check = nv50_pior_atomic_check,
1693         .enable = nv50_pior_enable,
1694         .disable = nv50_pior_disable,
1695 };
1696
1697 static void
1698 nv50_pior_destroy(struct drm_encoder *encoder)
1699 {
1700         drm_encoder_cleanup(encoder);
1701         kfree(encoder);
1702 }
1703
1704 static const struct drm_encoder_funcs
1705 nv50_pior_func = {
1706         .destroy = nv50_pior_destroy,
1707 };
1708
1709 static int
1710 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1711 {
1712         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1713         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1714         struct nvkm_i2c_bus *bus = NULL;
1715         struct nvkm_i2c_aux *aux = NULL;
1716         struct i2c_adapter *ddc;
1717         struct nouveau_encoder *nv_encoder;
1718         struct drm_encoder *encoder;
1719         int type;
1720
1721         switch (dcbe->type) {
1722         case DCB_OUTPUT_TMDS:
1723                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1724                 ddc  = bus ? &bus->i2c : NULL;
1725                 type = DRM_MODE_ENCODER_TMDS;
1726                 break;
1727         case DCB_OUTPUT_DP:
1728                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1729                 ddc  = aux ? &aux->i2c : NULL;
1730                 type = DRM_MODE_ENCODER_TMDS;
1731                 break;
1732         default:
1733                 return -ENODEV;
1734         }
1735
1736         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1737         if (!nv_encoder)
1738                 return -ENOMEM;
1739         nv_encoder->dcb = dcbe;
1740         nv_encoder->i2c = ddc;
1741         nv_encoder->aux = aux;
1742
1743         encoder = to_drm_encoder(nv_encoder);
1744         encoder->possible_crtcs = dcbe->heads;
1745         encoder->possible_clones = 0;
1746         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1747                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1748         drm_encoder_helper_add(encoder, &nv50_pior_help);
1749
1750         drm_connector_attach_encoder(connector, encoder);
1751         return 0;
1752 }
1753
1754 /******************************************************************************
1755  * Atomic
1756  *****************************************************************************/
1757
1758 static void
1759 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1760 {
1761         struct nouveau_drm *drm = nouveau_drm(state->dev);
1762         struct nv50_disp *disp = nv50_disp(drm->dev);
1763         struct nv50_core *core = disp->core;
1764         struct nv50_mstm *mstm;
1765         struct drm_encoder *encoder;
1766
1767         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1768
1769         drm_for_each_encoder(encoder, drm->dev) {
1770                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1771                         mstm = nouveau_encoder(encoder)->dp.mstm;
1772                         if (mstm && mstm->modified)
1773                                 nv50_mstm_prepare(mstm);
1774                 }
1775         }
1776
1777         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1778         core->func->update(core, interlock, true);
1779         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1780                                        disp->core->chan.base.device))
1781                 NV_ERROR(drm, "core notifier timeout\n");
1782
1783         drm_for_each_encoder(encoder, drm->dev) {
1784                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1785                         mstm = nouveau_encoder(encoder)->dp.mstm;
1786                         if (mstm && mstm->modified)
1787                                 nv50_mstm_cleanup(mstm);
1788                 }
1789         }
1790 }
1791
1792 static void
1793 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1794 {
1795         struct drm_plane_state *new_plane_state;
1796         struct drm_plane *plane;
1797         int i;
1798
1799         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1800                 struct nv50_wndw *wndw = nv50_wndw(plane);
1801                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1802                         if (wndw->func->update)
1803                                 wndw->func->update(wndw, interlock);
1804                 }
1805         }
1806 }
1807
1808 static void
1809 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1810 {
1811         struct drm_device *dev = state->dev;
1812         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1813         struct drm_crtc *crtc;
1814         struct drm_plane_state *new_plane_state;
1815         struct drm_plane *plane;
1816         struct nouveau_drm *drm = nouveau_drm(dev);
1817         struct nv50_disp *disp = nv50_disp(dev);
1818         struct nv50_atom *atom = nv50_atom(state);
1819         struct nv50_outp_atom *outp, *outt;
1820         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1821         int i;
1822
1823         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1824         drm_atomic_helper_wait_for_fences(dev, state, false);
1825         drm_atomic_helper_wait_for_dependencies(state);
1826         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1827
1828         if (atom->lock_core)
1829                 mutex_lock(&disp->mutex);
1830
1831         /* Disable head(s). */
1832         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1833                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1834                 struct nv50_head *head = nv50_head(crtc);
1835
1836                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1837                           asyh->clr.mask, asyh->set.mask);
1838
1839                 if (old_crtc_state->active && !new_crtc_state->active) {
1840                         pm_runtime_put_noidle(dev->dev);
1841                         drm_crtc_vblank_off(crtc);
1842                 }
1843
1844                 if (asyh->clr.mask) {
1845                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1846                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1847                 }
1848         }
1849
1850         /* Disable plane(s). */
1851         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1852                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1853                 struct nv50_wndw *wndw = nv50_wndw(plane);
1854
1855                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1856                           asyw->clr.mask, asyw->set.mask);
1857                 if (!asyw->clr.mask)
1858                         continue;
1859
1860                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1861         }
1862
1863         /* Disable output path(s). */
1864         list_for_each_entry(outp, &atom->outp, head) {
1865                 const struct drm_encoder_helper_funcs *help;
1866                 struct drm_encoder *encoder;
1867
1868                 encoder = outp->encoder;
1869                 help = encoder->helper_private;
1870
1871                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1872                           outp->clr.mask, outp->set.mask);
1873
1874                 if (outp->clr.mask) {
1875                         help->disable(encoder);
1876                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1877                         if (outp->flush_disable) {
1878                                 nv50_disp_atomic_commit_wndw(state, interlock);
1879                                 nv50_disp_atomic_commit_core(state, interlock);
1880                                 memset(interlock, 0x00, sizeof(interlock));
1881                         }
1882                 }
1883         }
1884
1885         /* Flush disable. */
1886         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1887                 if (atom->flush_disable) {
1888                         nv50_disp_atomic_commit_wndw(state, interlock);
1889                         nv50_disp_atomic_commit_core(state, interlock);
1890                         memset(interlock, 0x00, sizeof(interlock));
1891                 }
1892         }
1893
1894         /* Update output path(s). */
1895         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1896                 const struct drm_encoder_helper_funcs *help;
1897                 struct drm_encoder *encoder;
1898
1899                 encoder = outp->encoder;
1900                 help = encoder->helper_private;
1901
1902                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1903                           outp->set.mask, outp->clr.mask);
1904
1905                 if (outp->set.mask) {
1906                         help->enable(encoder);
1907                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1908                 }
1909
1910                 list_del(&outp->head);
1911                 kfree(outp);
1912         }
1913
1914         /* Update head(s). */
1915         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1916                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1917                 struct nv50_head *head = nv50_head(crtc);
1918
1919                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1920                           asyh->set.mask, asyh->clr.mask);
1921
1922                 if (asyh->set.mask) {
1923                         nv50_head_flush_set(head, asyh);
1924                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1925                 }
1926
1927                 if (new_crtc_state->active) {
1928                         if (!old_crtc_state->active) {
1929                                 drm_crtc_vblank_on(crtc);
1930                                 pm_runtime_get_noresume(dev->dev);
1931                         }
1932                         if (new_crtc_state->event)
1933                                 drm_crtc_vblank_get(crtc);
1934                 }
1935         }
1936
1937         /* Update plane(s). */
1938         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1939                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1940                 struct nv50_wndw *wndw = nv50_wndw(plane);
1941
1942                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1943                           asyw->set.mask, asyw->clr.mask);
1944                 if ( !asyw->set.mask &&
1945                     (!asyw->clr.mask || atom->flush_disable))
1946                         continue;
1947
1948                 nv50_wndw_flush_set(wndw, interlock, asyw);
1949         }
1950
1951         /* Flush update. */
1952         nv50_disp_atomic_commit_wndw(state, interlock);
1953
1954         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1955                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1956                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1957                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1958                     !atom->state.legacy_cursor_update)
1959                         nv50_disp_atomic_commit_core(state, interlock);
1960                 else
1961                         disp->core->func->update(disp->core, interlock, false);
1962         }
1963
1964         if (atom->lock_core)
1965                 mutex_unlock(&disp->mutex);
1966
1967         /* Wait for HW to signal completion. */
1968         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1969                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1970                 struct nv50_wndw *wndw = nv50_wndw(plane);
1971                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1972                 if (ret)
1973                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1974         }
1975
1976         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1977                 if (new_crtc_state->event) {
1978                         unsigned long flags;
1979                         /* Get correct count/ts if racing with vblank irq */
1980                         if (new_crtc_state->active)
1981                                 drm_crtc_accurate_vblank_count(crtc);
1982                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1983                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1984                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1985
1986                         new_crtc_state->event = NULL;
1987                         if (new_crtc_state->active)
1988                                 drm_crtc_vblank_put(crtc);
1989                 }
1990         }
1991
1992         drm_atomic_helper_commit_hw_done(state);
1993         drm_atomic_helper_cleanup_planes(dev, state);
1994         drm_atomic_helper_commit_cleanup_done(state);
1995         drm_atomic_state_put(state);
1996
1997         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
1998         pm_runtime_mark_last_busy(dev->dev);
1999         pm_runtime_put_autosuspend(dev->dev);
2000 }
2001
2002 static void
2003 nv50_disp_atomic_commit_work(struct work_struct *work)
2004 {
2005         struct drm_atomic_state *state =
2006                 container_of(work, typeof(*state), commit_work);
2007         nv50_disp_atomic_commit_tail(state);
2008 }
2009
2010 static int
2011 nv50_disp_atomic_commit(struct drm_device *dev,
2012                         struct drm_atomic_state *state, bool nonblock)
2013 {
2014         struct drm_plane_state *new_plane_state;
2015         struct drm_plane *plane;
2016         int ret, i;
2017
2018         ret = pm_runtime_get_sync(dev->dev);
2019         if (ret < 0 && ret != -EACCES)
2020                 return ret;
2021
2022         ret = drm_atomic_helper_setup_commit(state, nonblock);
2023         if (ret)
2024                 goto done;
2025
2026         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2027
2028         ret = drm_atomic_helper_prepare_planes(dev, state);
2029         if (ret)
2030                 goto done;
2031
2032         if (!nonblock) {
2033                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2034                 if (ret)
2035                         goto err_cleanup;
2036         }
2037
2038         ret = drm_atomic_helper_swap_state(state, true);
2039         if (ret)
2040                 goto err_cleanup;
2041
2042         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2043                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2044                 struct nv50_wndw *wndw = nv50_wndw(plane);
2045
2046                 if (asyw->set.image)
2047                         nv50_wndw_ntfy_enable(wndw, asyw);
2048         }
2049
2050         drm_atomic_state_get(state);
2051
2052         /*
2053          * Grab another RPM ref for the commit tail, which will release the
2054          * ref when it's finished
2055          */
2056         pm_runtime_get_noresume(dev->dev);
2057
2058         if (nonblock)
2059                 queue_work(system_unbound_wq, &state->commit_work);
2060         else
2061                 nv50_disp_atomic_commit_tail(state);
2062
2063 err_cleanup:
2064         if (ret)
2065                 drm_atomic_helper_cleanup_planes(dev, state);
2066 done:
2067         pm_runtime_put_autosuspend(dev->dev);
2068         return ret;
2069 }
2070
2071 static struct nv50_outp_atom *
2072 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2073 {
2074         struct nv50_outp_atom *outp;
2075
2076         list_for_each_entry(outp, &atom->outp, head) {
2077                 if (outp->encoder == encoder)
2078                         return outp;
2079         }
2080
2081         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2082         if (!outp)
2083                 return ERR_PTR(-ENOMEM);
2084
2085         list_add(&outp->head, &atom->outp);
2086         outp->encoder = encoder;
2087         return outp;
2088 }
2089
2090 static int
2091 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2092                                 struct drm_connector_state *old_connector_state)
2093 {
2094         struct drm_encoder *encoder = old_connector_state->best_encoder;
2095         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2096         struct drm_crtc *crtc;
2097         struct nv50_outp_atom *outp;
2098
2099         if (!(crtc = old_connector_state->crtc))
2100                 return 0;
2101
2102         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2103         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2104         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2105                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2106                 if (IS_ERR(outp))
2107                         return PTR_ERR(outp);
2108
2109                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2110                         outp->flush_disable = true;
2111                         atom->flush_disable = true;
2112                 }
2113                 outp->clr.ctrl = true;
2114                 atom->lock_core = true;
2115         }
2116
2117         return 0;
2118 }
2119
2120 static int
2121 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2122                                 struct drm_connector_state *connector_state)
2123 {
2124         struct drm_encoder *encoder = connector_state->best_encoder;
2125         struct drm_crtc_state *new_crtc_state;
2126         struct drm_crtc *crtc;
2127         struct nv50_outp_atom *outp;
2128
2129         if (!(crtc = connector_state->crtc))
2130                 return 0;
2131
2132         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2133         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2134                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2135                 if (IS_ERR(outp))
2136                         return PTR_ERR(outp);
2137
2138                 outp->set.ctrl = true;
2139                 atom->lock_core = true;
2140         }
2141
2142         return 0;
2143 }
2144
2145 static int
2146 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2147 {
2148         struct nv50_atom *atom = nv50_atom(state);
2149         struct drm_connector_state *old_connector_state, *new_connector_state;
2150         struct drm_connector *connector;
2151         struct drm_crtc_state *new_crtc_state;
2152         struct drm_crtc *crtc;
2153         int ret, i;
2154
2155         /* We need to handle colour management on a per-plane basis. */
2156         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2157                 if (new_crtc_state->color_mgmt_changed) {
2158                         ret = drm_atomic_add_affected_planes(state, crtc);
2159                         if (ret)
2160                                 return ret;
2161                 }
2162         }
2163
2164         ret = drm_atomic_helper_check(dev, state);
2165         if (ret)
2166                 return ret;
2167
2168         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2169                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2170                 if (ret)
2171                         return ret;
2172
2173                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2174                 if (ret)
2175                         return ret;
2176         }
2177
2178         ret = drm_dp_mst_atomic_check(state);
2179         if (ret)
2180                 return ret;
2181
2182         return 0;
2183 }
2184
2185 static void
2186 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2187 {
2188         struct nv50_atom *atom = nv50_atom(state);
2189         struct nv50_outp_atom *outp, *outt;
2190
2191         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2192                 list_del(&outp->head);
2193                 kfree(outp);
2194         }
2195
2196         drm_atomic_state_default_clear(state);
2197 }
2198
2199 static void
2200 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2201 {
2202         struct nv50_atom *atom = nv50_atom(state);
2203         drm_atomic_state_default_release(&atom->state);
2204         kfree(atom);
2205 }
2206
2207 static struct drm_atomic_state *
2208 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2209 {
2210         struct nv50_atom *atom;
2211         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2212             drm_atomic_state_init(dev, &atom->state) < 0) {
2213                 kfree(atom);
2214                 return NULL;
2215         }
2216         INIT_LIST_HEAD(&atom->outp);
2217         return &atom->state;
2218 }
2219
2220 static const struct drm_mode_config_funcs
2221 nv50_disp_func = {
2222         .fb_create = nouveau_user_framebuffer_create,
2223         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2224         .atomic_check = nv50_disp_atomic_check,
2225         .atomic_commit = nv50_disp_atomic_commit,
2226         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2227         .atomic_state_clear = nv50_disp_atomic_state_clear,
2228         .atomic_state_free = nv50_disp_atomic_state_free,
2229 };
2230
2231 /******************************************************************************
2232  * Init
2233  *****************************************************************************/
2234
2235 static void
2236 nv50_display_fini(struct drm_device *dev, bool suspend)
2237 {
2238         struct nouveau_encoder *nv_encoder;
2239         struct drm_encoder *encoder;
2240         struct drm_plane *plane;
2241
2242         drm_for_each_plane(plane, dev) {
2243                 struct nv50_wndw *wndw = nv50_wndw(plane);
2244                 if (plane->funcs != &nv50_wndw)
2245                         continue;
2246                 nv50_wndw_fini(wndw);
2247         }
2248
2249         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2250                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2251                         nv_encoder = nouveau_encoder(encoder);
2252                         nv50_mstm_fini(nv_encoder->dp.mstm);
2253                 }
2254         }
2255 }
2256
2257 static int
2258 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2259 {
2260         struct nv50_core *core = nv50_disp(dev)->core;
2261         struct drm_encoder *encoder;
2262         struct drm_plane *plane;
2263
2264         core->func->init(core);
2265
2266         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2267                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2268                         struct nouveau_encoder *nv_encoder =
2269                                 nouveau_encoder(encoder);
2270                         nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2271                 }
2272         }
2273
2274         drm_for_each_plane(plane, dev) {
2275                 struct nv50_wndw *wndw = nv50_wndw(plane);
2276                 if (plane->funcs != &nv50_wndw)
2277                         continue;
2278                 nv50_wndw_init(wndw);
2279         }
2280
2281         return 0;
2282 }
2283
2284 static void
2285 nv50_display_destroy(struct drm_device *dev)
2286 {
2287         struct nv50_disp *disp = nv50_disp(dev);
2288
2289         nv50_core_del(&disp->core);
2290
2291         nouveau_bo_unmap(disp->sync);
2292         if (disp->sync)
2293                 nouveau_bo_unpin(disp->sync);
2294         nouveau_bo_ref(NULL, &disp->sync);
2295
2296         nouveau_display(dev)->priv = NULL;
2297         kfree(disp);
2298 }
2299
2300 int
2301 nv50_display_create(struct drm_device *dev)
2302 {
2303         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2304         struct nouveau_drm *drm = nouveau_drm(dev);
2305         struct dcb_table *dcb = &drm->vbios.dcb;
2306         struct drm_connector *connector, *tmp;
2307         struct nv50_disp *disp;
2308         struct dcb_output *dcbe;
2309         int crtcs, ret, i;
2310
2311         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2312         if (!disp)
2313                 return -ENOMEM;
2314
2315         mutex_init(&disp->mutex);
2316
2317         nouveau_display(dev)->priv = disp;
2318         nouveau_display(dev)->dtor = nv50_display_destroy;
2319         nouveau_display(dev)->init = nv50_display_init;
2320         nouveau_display(dev)->fini = nv50_display_fini;
2321         disp->disp = &nouveau_display(dev)->disp;
2322         dev->mode_config.funcs = &nv50_disp_func;
2323         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2324         dev->mode_config.normalize_zpos = true;
2325
2326         /* small shared memory area we use for notifiers and semaphores */
2327         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2328                              0, 0x0000, NULL, NULL, &disp->sync);
2329         if (!ret) {
2330                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2331                 if (!ret) {
2332                         ret = nouveau_bo_map(disp->sync);
2333                         if (ret)
2334                                 nouveau_bo_unpin(disp->sync);
2335                 }
2336                 if (ret)
2337                         nouveau_bo_ref(NULL, &disp->sync);
2338         }
2339
2340         if (ret)
2341                 goto out;
2342
2343         /* allocate master evo channel */
2344         ret = nv50_core_new(drm, &disp->core);
2345         if (ret)
2346                 goto out;
2347
2348         /* create crtc objects to represent the hw heads */
2349         if (disp->disp->object.oclass >= GV100_DISP)
2350                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2351         else
2352         if (disp->disp->object.oclass >= GF110_DISP)
2353                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2354         else
2355                 crtcs = 0x3;
2356
2357         for (i = 0; i < fls(crtcs); i++) {
2358                 if (!(crtcs & (1 << i)))
2359                         continue;
2360                 ret = nv50_head_create(dev, i);
2361                 if (ret)
2362                         goto out;
2363         }
2364
2365         /* create encoder/connector objects based on VBIOS DCB table */
2366         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2367                 connector = nouveau_connector_create(dev, dcbe);
2368                 if (IS_ERR(connector))
2369                         continue;
2370
2371                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2372                         switch (dcbe->type) {
2373                         case DCB_OUTPUT_TMDS:
2374                         case DCB_OUTPUT_LVDS:
2375                         case DCB_OUTPUT_DP:
2376                                 ret = nv50_sor_create(connector, dcbe);
2377                                 break;
2378                         case DCB_OUTPUT_ANALOG:
2379                                 ret = nv50_dac_create(connector, dcbe);
2380                                 break;
2381                         default:
2382                                 ret = -ENODEV;
2383                                 break;
2384                         }
2385                 } else {
2386                         ret = nv50_pior_create(connector, dcbe);
2387                 }
2388
2389                 if (ret) {
2390                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2391                                      dcbe->location, dcbe->type,
2392                                      ffs(dcbe->or) - 1, ret);
2393                         ret = 0;
2394                 }
2395         }
2396
2397         /* cull any connectors we created that don't have an encoder */
2398         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2399                 if (connector->possible_encoders)
2400                         continue;
2401
2402                 NV_WARN(drm, "%s has no encoders, removing\n",
2403                         connector->name);
2404                 connector->funcs->destroy(connector);
2405         }
2406
2407         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2408         dev->vblank_disable_immediate = true;
2409
2410 out:
2411         if (ret)
2412                 nv50_display_destroy(dev);
2413         return ret;
2414 }