drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_dp_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_fb_helper.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <drm/drm_vblank.h>
  41
  42 #include <nvif/class.h>
  43 #include <nvif/cl0002.h>
  44 #include <nvif/cl5070.h>
  45 #include <nvif/cl507d.h>
  46 #include <nvif/event.h>
  47
  48 #include "nouveau_drv.h"
  49 #include "nouveau_dma.h"
  50 #include "nouveau_gem.h"
  51 #include "nouveau_connector.h"
  52 #include "nouveau_encoder.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55
  56 #include <subdev/bios/dp.h>
  57
  58 /******************************************************************************
  59  * Atomic state
  60  *****************************************************************************/
  61
  62 struct nv50_outp_atom {
  63         struct list_head head;
  64
  65         struct drm_encoder *encoder;
  66         bool flush_disable;
  67
  68         union nv50_outp_atom_mask {
  69                 struct {
  70                         bool ctrl:1;
  71                 };
  72                 u8 mask;
  73         } set, clr;
  74 };
  75
  76 /******************************************************************************
  77  * EVO channel
  78  *****************************************************************************/
  79
  80 static int
  81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  82                  const s32 *oclass, u8 head, void *data, u32 size,
  83                  struct nv50_chan *chan)
  84 {
  85         struct nvif_sclass *sclass;
  86         int ret, i, n;
  87
  88         chan->device = device;
  89
  90         ret = n = nvif_object_sclass_get(disp, &sclass);
  91         if (ret < 0)
  92                 return ret;
  93
  94         while (oclass[0]) {
  95                 for (i = 0; i < n; i++) {
  96                         if (sclass[i].oclass == oclass[0]) {
  97                                 ret = nvif_object_init(disp, 0, oclass[0],
  98                                                        data, size, &chan->user);
  99                                 if (ret == 0)
 100                                         nvif_object_map(&chan->user, NULL, 0);
 101                                 nvif_object_sclass_put(&sclass);
 102                                 return ret;
 103                         }
 104                 }
 105                 oclass++;
 106         }
 107
 108         nvif_object_sclass_put(&sclass);
 109         return -ENOSYS;
 110 }
 111
 112 static void
 113 nv50_chan_destroy(struct nv50_chan *chan)
 114 {
 115         nvif_object_fini(&chan->user);
 116 }
 117
 118 /******************************************************************************
 119  * DMA EVO channel
 120  *****************************************************************************/
 121
 122 void
 123 nv50_dmac_destroy(struct nv50_dmac *dmac)
 124 {
 125         nvif_object_fini(&dmac->vram);
 126         nvif_object_fini(&dmac->sync);
 127
 128         nv50_chan_destroy(&dmac->base);
 129
 130         nvif_mem_fini(&dmac->push);
 131 }
 132
 133 int
 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 135                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 136                  struct nv50_dmac *dmac)
 137 {
 138         struct nouveau_cli *cli = (void *)device->object.client;
 139         struct nv50_disp_core_channel_dma_v0 *args = data;
 140         u8 type = NVIF_MEM_COHERENT;
 141         int ret;
 142
 143         mutex_init(&dmac->lock);
 144
 145         /* Pascal added support for 47-bit physical addresses, but some
 146          * parts of EVO still only accept 40-bit PAs.
 147          *
 148          * To avoid issues on systems with large amounts of RAM, and on
 149          * systems where an IOMMU maps pages at a high address, we need
 150          * to allocate push buffers in VRAM instead.
 151          *
 152          * This appears to match NVIDIA's behaviour on Pascal.
 153          */
 154         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 155                 type |= NVIF_MEM_VRAM;
 156
 157         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 158         if (ret)
 159                 return ret;
 160
 161         dmac->ptr = dmac->push.object.map.ptr;
 162
 163         args->pushbuf = nvif_handle(&dmac->push.object);
 164
 165         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 166                                &dmac->base);
 167         if (ret)
 168                 return ret;
 169
 170         if (!syncbuf)
 171                 return 0;
 172
 173         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 174                                &(struct nv_dma_v0) {
 175                                         .target = NV_DMA_V0_TARGET_VRAM,
 176                                         .access = NV_DMA_V0_ACCESS_RDWR,
 177                                         .start = syncbuf + 0x0000,
 178                                         .limit = syncbuf + 0x0fff,
 179                                }, sizeof(struct nv_dma_v0),
 180                                &dmac->sync);
 181         if (ret)
 182                 return ret;
 183
 184         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 185                                &(struct nv_dma_v0) {
 186                                         .target = NV_DMA_V0_TARGET_VRAM,
 187                                         .access = NV_DMA_V0_ACCESS_RDWR,
 188                                         .start = 0,
 189                                         .limit = device->info.ram_user - 1,
 190                                }, sizeof(struct nv_dma_v0),
 191                                &dmac->vram);
 192         if (ret)
 193                 return ret;
 194
 195         return ret;
 196 }
 197
 198 /******************************************************************************
 199  * EVO channel helpers
 200  *****************************************************************************/
 201 static void
 202 evo_flush(struct nv50_dmac *dmac)
 203 {
 204         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 205          * writes have been flushed right through to VRAM before writing PUT.
 206          */
 207         if (dmac->push.type & NVIF_MEM_VRAM) {
 208                 struct nvif_device *device = dmac->base.device;
 209                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 210                 nvif_msec(device, 2000,
 211                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 212                                 break;
 213                 );
 214         }
 215 }
 216
 217 u32 *
 218 evo_wait(struct nv50_dmac *evoc, int nr)
 219 {
 220         struct nv50_dmac *dmac = evoc;
 221         struct nvif_device *device = dmac->base.device;
 222         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 223
 224         mutex_lock(&dmac->lock);
 225         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 226                 dmac->ptr[put] = 0x20000000;
 227                 evo_flush(dmac);
 228
 229                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 230                 if (nvif_msec(device, 2000,
 231                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 232                                 break;
 233                 ) < 0) {
 234                         mutex_unlock(&dmac->lock);
 235                         pr_err("nouveau: evo channel stalled\n");
 236                         return NULL;
 237                 }
 238
 239                 put = 0;
 240         }
 241
 242         return dmac->ptr + put;
 243 }
 244
 245 void
 246 evo_kick(u32 *push, struct nv50_dmac *evoc)
 247 {
 248         struct nv50_dmac *dmac = evoc;
 249
 250         evo_flush(dmac);
 251
 252         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 253         mutex_unlock(&dmac->lock);
 254 }
 255
 256 /******************************************************************************
 257  * Output path helpers
 258  *****************************************************************************/
 259 static void
 260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 261 {
 262         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 263         struct {
 264                 struct nv50_disp_mthd_v1 base;
 265         } args = {
 266                 .base.version = 1,
 267                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 268                 .base.hasht  = nv_encoder->dcb->hasht,
 269                 .base.hashm  = nv_encoder->dcb->hashm,
 270         };
 271
 272         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 273         nv_encoder->or = -1;
 274         nv_encoder->link = 0;
 275 }
 276
 277 static int
 278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 279 {
 280         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 281         struct nv50_disp *disp = nv50_disp(drm->dev);
 282         struct {
 283                 struct nv50_disp_mthd_v1 base;
 284                 struct nv50_disp_acquire_v0 info;
 285         } args = {
 286                 .base.version = 1,
 287                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 288                 .base.hasht  = nv_encoder->dcb->hasht,
 289                 .base.hashm  = nv_encoder->dcb->hashm,
 290         };
 291         int ret;
 292
 293         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 294         if (ret) {
 295                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 296                 return ret;
 297         }
 298
 299         nv_encoder->or = args.info.or;
 300         nv_encoder->link = args.info.link;
 301         return 0;
 302 }
 303
 304 static int
 305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 306                             struct drm_crtc_state *crtc_state,
 307                             struct drm_connector_state *conn_state,
 308                             struct drm_display_mode *native_mode)
 309 {
 310         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 311         struct drm_display_mode *mode = &crtc_state->mode;
 312         struct drm_connector *connector = conn_state->connector;
 313         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 314         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 315
 316         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 317         asyc->scaler.full = false;
 318         if (!native_mode)
 319                 return 0;
 320
 321         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 322                 switch (connector->connector_type) {
 323                 case DRM_MODE_CONNECTOR_LVDS:
 324                 case DRM_MODE_CONNECTOR_eDP:
 325                         /* Don't force scaler for EDID modes with
 326                          * same size as the native one (e.g. different
 327                          * refresh rate)
 328                          */
 329                         if (adjusted_mode->hdisplay == native_mode->hdisplay &&
 330                             adjusted_mode->vdisplay == native_mode->vdisplay &&
 331                             adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
 332                                 break;
 333                         mode = native_mode;
 334                         asyc->scaler.full = true;
 335                         break;
 336                 default:
 337                         break;
 338                 }
 339         } else {
 340                 mode = native_mode;
 341         }
 342
 343         if (!drm_mode_equal(adjusted_mode, mode)) {
 344                 drm_mode_copy(adjusted_mode, mode);
 345                 crtc_state->mode_changed = true;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int
 352 nv50_outp_atomic_check(struct drm_encoder *encoder,
 353                        struct drm_crtc_state *crtc_state,
 354                        struct drm_connector_state *conn_state)
 355 {
 356         struct drm_connector *connector = conn_state->connector;
 357         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 358         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 359         int ret;
 360
 361         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 362                                           nv_connector->native_mode);
 363         if (ret)
 364                 return ret;
 365
 366         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 367                 asyh->or.bpc = connector->display_info.bpc;
 368
 369         return 0;
 370 }
 371
 372 /******************************************************************************
 373  * DAC
 374  *****************************************************************************/
 375 static void
 376 nv50_dac_disable(struct drm_encoder *encoder)
 377 {
 378         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 379         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 380         if (nv_encoder->crtc)
 381                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 382         nv_encoder->crtc = NULL;
 383         nv50_outp_release(nv_encoder);
 384 }
 385
 386 static void
 387 nv50_dac_enable(struct drm_encoder *encoder)
 388 {
 389         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 390         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 391         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 392         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 393
 394         nv50_outp_acquire(nv_encoder);
 395
 396         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 397         asyh->or.depth = 0;
 398
 399         nv_encoder->crtc = encoder->crtc;
 400 }
 401
 402 static enum drm_connector_status
 403 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 404 {
 405         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 406         struct nv50_disp *disp = nv50_disp(encoder->dev);
 407         struct {
 408                 struct nv50_disp_mthd_v1 base;
 409                 struct nv50_disp_dac_load_v0 load;
 410         } args = {
 411                 .base.version = 1,
 412                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 413                 .base.hasht  = nv_encoder->dcb->hasht,
 414                 .base.hashm  = nv_encoder->dcb->hashm,
 415         };
 416         int ret;
 417
 418         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 419         if (args.load.data == 0)
 420                 args.load.data = 340;
 421
 422         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 423         if (ret || !args.load.load)
 424                 return connector_status_disconnected;
 425
 426         return connector_status_connected;
 427 }
 428
 429 static const struct drm_encoder_helper_funcs
 430 nv50_dac_help = {
 431         .atomic_check = nv50_outp_atomic_check,
 432         .enable = nv50_dac_enable,
 433         .disable = nv50_dac_disable,
 434         .detect = nv50_dac_detect
 435 };
 436
 437 static void
 438 nv50_dac_destroy(struct drm_encoder *encoder)
 439 {
 440         drm_encoder_cleanup(encoder);
 441         kfree(encoder);
 442 }
 443
 444 static const struct drm_encoder_funcs
 445 nv50_dac_func = {
 446         .destroy = nv50_dac_destroy,
 447 };
 448
 449 static int
 450 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 451 {
 452         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 453         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 454         struct nvkm_i2c_bus *bus;
 455         struct nouveau_encoder *nv_encoder;
 456         struct drm_encoder *encoder;
 457         int type = DRM_MODE_ENCODER_DAC;
 458
 459         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 460         if (!nv_encoder)
 461                 return -ENOMEM;
 462         nv_encoder->dcb = dcbe;
 463
 464         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 465         if (bus)
 466                 nv_encoder->i2c = &bus->i2c;
 467
 468         encoder = to_drm_encoder(nv_encoder);
 469         encoder->possible_crtcs = dcbe->heads;
 470         encoder->possible_clones = 0;
 471         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 472                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 473         drm_encoder_helper_add(encoder, &nv50_dac_help);
 474
 475         drm_connector_attach_encoder(connector, encoder);
 476         return 0;
 477 }
 478
 479 /******************************************************************************
 480  * Audio
 481  *****************************************************************************/
 482 static void
 483 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 484 {
 485         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 486         struct nv50_disp *disp = nv50_disp(encoder->dev);
 487         struct {
 488                 struct nv50_disp_mthd_v1 base;
 489                 struct nv50_disp_sor_hda_eld_v0 eld;
 490         } args = {
 491                 .base.version = 1,
 492                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 493                 .base.hasht   = nv_encoder->dcb->hasht,
 494                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 495                                 (0x0100 << nv_crtc->index),
 496         };
 497
 498         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 499 }
 500
 501 static void
 502 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 503 {
 504         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 505         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 506         struct nouveau_connector *nv_connector;
 507         struct nv50_disp *disp = nv50_disp(encoder->dev);
 508         struct __packed {
 509                 struct {
 510                         struct nv50_disp_mthd_v1 mthd;
 511                         struct nv50_disp_sor_hda_eld_v0 eld;
 512                 } base;
 513                 u8 data[sizeof(nv_connector->base.eld)];
 514         } args = {
 515                 .base.mthd.version = 1,
 516                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 517                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 518                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 519                                      (0x0100 << nv_crtc->index),
 520         };
 521
 522         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 523         if (!drm_detect_monitor_audio(nv_connector->edid))
 524                 return;
 525
 526         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 527
 528         nvif_mthd(&disp->disp->object, 0, &args,
 529                   sizeof(args.base) + drm_eld_size(args.data));
 530 }
 531
 532 /******************************************************************************
 533  * HDMI
 534  *****************************************************************************/
 535 static void
 536 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 537 {
 538         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 539         struct nv50_disp *disp = nv50_disp(encoder->dev);
 540         struct {
 541                 struct nv50_disp_mthd_v1 base;
 542                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 543         } args = {
 544                 .base.version = 1,
 545                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 546                 .base.hasht  = nv_encoder->dcb->hasht,
 547                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 548                                (0x0100 << nv_crtc->index),
 549         };
 550
 551         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 552 }
 553
 554 static void
 555 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 556 {
 557         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 558         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 559         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 560         struct nv50_disp *disp = nv50_disp(encoder->dev);
 561         struct {
 562                 struct nv50_disp_mthd_v1 base;
 563                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 564                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 565         } args = {
 566                 .base.version = 1,
 567                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 568                 .base.hasht  = nv_encoder->dcb->hasht,
 569                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 570                                (0x0100 << nv_crtc->index),
 571                 .pwr.state = 1,
 572                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 573         };
 574         struct nouveau_connector *nv_connector;
 575         struct drm_hdmi_info *hdmi;
 576         u32 max_ac_packet;
 577         union hdmi_infoframe avi_frame;
 578         union hdmi_infoframe vendor_frame;
 579         bool high_tmds_clock_ratio = false, scrambling = false;
 580         u8 config;
 581         int ret;
 582         int size;
 583
 584         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 585         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 586                 return;
 587
 588         hdmi = &nv_connector->base.display_info.hdmi;
 589
 590         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 591                                                        &nv_connector->base, mode);
 592         if (!ret) {
 593                 /* We have an AVI InfoFrame, populate it to the display */
 594                 args.pwr.avi_infoframe_length
 595                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 596         }
 597
 598         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 599                                                           &nv_connector->base, mode);
 600         if (!ret) {
 601                 /* We have a Vendor InfoFrame, populate it to the display */
 602                 args.pwr.vendor_infoframe_length
 603                         = hdmi_infoframe_pack(&vendor_frame,
 604                                               args.infoframes
 605                                               + args.pwr.avi_infoframe_length,
 606                                               17);
 607         }
 608
 609         max_ac_packet  = mode->htotal - mode->hdisplay;
 610         max_ac_packet -= args.pwr.rekey;
 611         max_ac_packet -= 18; /* constant from tegra */
 612         args.pwr.max_ac_packet = max_ac_packet / 32;
 613
 614         if (hdmi->scdc.scrambling.supported) {
 615                 high_tmds_clock_ratio = mode->clock > 340000;
 616                 scrambling = high_tmds_clock_ratio ||
 617                         hdmi->scdc.scrambling.low_rates;
 618         }
 619
 620         args.pwr.scdc =
 621                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 622                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 623
 624         size = sizeof(args.base)
 625                 + sizeof(args.pwr)
 626                 + args.pwr.avi_infoframe_length
 627                 + args.pwr.vendor_infoframe_length;
 628         nvif_mthd(&disp->disp->object, 0, &args, size);
 629
 630         nv50_audio_enable(encoder, mode);
 631
 632         /* If SCDC is supported by the downstream monitor, update
 633          * divider / scrambling settings to what we programmed above.
 634          */
 635         if (!hdmi->scdc.scrambling.supported)
 636                 return;
 637
 638         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 639         if (ret < 0) {
 640                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 641                 return;
 642         }
 643         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 644         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 645         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 646         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 647         if (ret < 0)
 648                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 649                          config, ret);
 650 }
 651
 652 /******************************************************************************
 653  * MST
 654  *****************************************************************************/
 655 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 656 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 657 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 658
 659 struct nv50_mstm {
 660         struct nouveau_encoder *outp;
 661
 662         struct drm_dp_mst_topology_mgr mgr;
 663         struct nv50_msto *msto[4];
 664
 665         bool modified;
 666         bool disabled;
 667         int links;
 668 };
 669
 670 struct nv50_mstc {
 671         struct nv50_mstm *mstm;
 672         struct drm_dp_mst_port *port;
 673         struct drm_connector connector;
 674
 675         struct drm_display_mode *native;
 676         struct edid *edid;
 677 };
 678
 679 struct nv50_msto {
 680         struct drm_encoder encoder;
 681
 682         struct nv50_head *head;
 683         struct nv50_mstc *mstc;
 684         bool disabled;
 685 };
 686
 687 static struct drm_dp_payload *
 688 nv50_msto_payload(struct nv50_msto *msto)
 689 {
 690         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 691         struct nv50_mstc *mstc = msto->mstc;
 692         struct nv50_mstm *mstm = mstc->mstm;
 693         int vcpi = mstc->port->vcpi.vcpi, i;
 694
 695         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 696
 697         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 698         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 699                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 700                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 701                           mstm->outp->base.base.name, i, payload->vcpi,
 702                           payload->start_slot, payload->num_slots);
 703         }
 704
 705         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 706                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 707                 if (payload->vcpi == vcpi)
 708                         return payload;
 709         }
 710
 711         return NULL;
 712 }
 713
 714 static void
 715 nv50_msto_cleanup(struct nv50_msto *msto)
 716 {
 717         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 718         struct nv50_mstc *mstc = msto->mstc;
 719         struct nv50_mstm *mstm = mstc->mstm;
 720
 721         if (!msto->disabled)
 722                 return;
 723
 724         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 725
 726         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 727
 728         msto->mstc = NULL;
 729         msto->head = NULL;
 730         msto->disabled = false;
 731 }
 732
 733 static void
 734 nv50_msto_prepare(struct nv50_msto *msto)
 735 {
 736         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 737         struct nv50_mstc *mstc = msto->mstc;
 738         struct nv50_mstm *mstm = mstc->mstm;
 739         struct {
 740                 struct nv50_disp_mthd_v1 base;
 741                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 742         } args = {
 743                 .base.version = 1,
 744                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 745                 .base.hasht  = mstm->outp->dcb->hasht,
 746                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 747                                (0x0100 << msto->head->base.index),
 748         };
 749
 750         mutex_lock(&mstm->mgr.payload_lock);
 751
 752         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 753         if (mstc->port->vcpi.vcpi > 0) {
 754                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 755                 if (payload) {
 756                         args.vcpi.start_slot = payload->start_slot;
 757                         args.vcpi.num_slots = payload->num_slots;
 758                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 759                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 760                 }
 761         }
 762
 763         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 764                   msto->encoder.name, msto->head->base.base.name,
 765                   args.vcpi.start_slot, args.vcpi.num_slots,
 766                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 767
 768         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 769         mutex_unlock(&mstm->mgr.payload_lock);
 770 }
 771
 772 static int
 773 nv50_msto_atomic_check(struct drm_encoder *encoder,
 774                        struct drm_crtc_state *crtc_state,
 775                        struct drm_connector_state *conn_state)
 776 {
 777         struct drm_atomic_state *state = crtc_state->state;
 778         struct drm_connector *connector = conn_state->connector;
 779         struct nv50_mstc *mstc = nv50_mstc(connector);
 780         struct nv50_mstm *mstm = mstc->mstm;
 781         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 782         int slots;
 783         int ret;
 784
 785         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 786                                           mstc->native);
 787         if (ret)
 788                 return ret;
 789
 790         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
 791                 return 0;
 792
 793         /*
 794          * When restoring duplicated states, we need to make sure that the bw
 795          * remains the same and avoid recalculating it, as the connector's bpc
 796          * may have changed after the state was duplicated
 797          */
 798         if (!state->duplicated) {
 799                 const int clock = crtc_state->adjusted_mode.clock;
 800
 801                 asyh->or.bpc = connector->display_info.bpc;
 802                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3);
 803         }
 804
 805         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
 806                                               asyh->dp.pbn);
 807         if (slots < 0)
 808                 return slots;
 809
 810         asyh->dp.tu = slots;
 811
 812         return 0;
 813 }
 814
 815 static u8
 816 nv50_dp_bpc_to_depth(unsigned int bpc)
 817 {
 818         switch (bpc) {
 819         case  6: return 0x2;
 820         case  8: return 0x5;
 821         case 10: /* fall-through */
 822         default: return 0x6;
 823         }
 824 }
 825
 826 static void
 827 nv50_msto_enable(struct drm_encoder *encoder)
 828 {
 829         struct nv50_head *head = nv50_head(encoder->crtc);
 830         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
 831         struct nv50_msto *msto = nv50_msto(encoder);
 832         struct nv50_mstc *mstc = NULL;
 833         struct nv50_mstm *mstm = NULL;
 834         struct drm_connector *connector;
 835         struct drm_connector_list_iter conn_iter;
 836         u8 proto;
 837         bool r;
 838
 839         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 840         drm_for_each_connector_iter(connector, &conn_iter) {
 841                 if (connector->state->best_encoder == &msto->encoder) {
 842                         mstc = nv50_mstc(connector);
 843                         mstm = mstc->mstm;
 844                         break;
 845                 }
 846         }
 847         drm_connector_list_iter_end(&conn_iter);
 848
 849         if (WARN_ON(!mstc))
 850                 return;
 851
 852         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
 853                                      armh->dp.tu);
 854         if (!r)
 855                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
 856
 857         if (!mstm->links++)
 858                 nv50_outp_acquire(mstm->outp);
 859
 860         if (mstm->outp->link & 1)
 861                 proto = 0x8;
 862         else
 863                 proto = 0x9;
 864
 865         mstm->outp->update(mstm->outp, head->base.index, armh, proto,
 866                            nv50_dp_bpc_to_depth(armh->or.bpc));
 867
 868         msto->head = head;
 869         msto->mstc = mstc;
 870         mstm->modified = true;
 871 }
 872
 873 static void
 874 nv50_msto_disable(struct drm_encoder *encoder)
 875 {
 876         struct nv50_msto *msto = nv50_msto(encoder);
 877         struct nv50_mstc *mstc = msto->mstc;
 878         struct nv50_mstm *mstm = mstc->mstm;
 879
 880         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 881
 882         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 883         mstm->modified = true;
 884         if (!--mstm->links)
 885                 mstm->disabled = true;
 886         msto->disabled = true;
 887 }
 888
 889 static const struct drm_encoder_helper_funcs
 890 nv50_msto_help = {
 891         .disable = nv50_msto_disable,
 892         .enable = nv50_msto_enable,
 893         .atomic_check = nv50_msto_atomic_check,
 894 };
 895
 896 static void
 897 nv50_msto_destroy(struct drm_encoder *encoder)
 898 {
 899         struct nv50_msto *msto = nv50_msto(encoder);
 900         drm_encoder_cleanup(&msto->encoder);
 901         kfree(msto);
 902 }
 903
 904 static const struct drm_encoder_funcs
 905 nv50_msto = {
 906         .destroy = nv50_msto_destroy,
 907 };
 908
 909 static int
 910 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 911               struct nv50_msto **pmsto)
 912 {
 913         struct nv50_msto *msto;
 914         int ret;
 915
 916         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 917                 return -ENOMEM;
 918
 919         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 920                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 921         if (ret) {
 922                 kfree(*pmsto);
 923                 *pmsto = NULL;
 924                 return ret;
 925         }
 926
 927         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 928         msto->encoder.possible_crtcs = heads;
 929         return 0;
 930 }
 931
 932 static struct drm_encoder *
 933 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 934                               struct drm_connector_state *connector_state)
 935 {
 936         struct nv50_head *head = nv50_head(connector_state->crtc);
 937         struct nv50_mstc *mstc = nv50_mstc(connector);
 938
 939         return &mstc->mstm->msto[head->base.index]->encoder;
 940 }
 941
 942 static struct drm_encoder *
 943 nv50_mstc_best_encoder(struct drm_connector *connector)
 944 {
 945         struct nv50_mstc *mstc = nv50_mstc(connector);
 946
 947         return &mstc->mstm->msto[0]->encoder;
 948 }
 949
 950 static enum drm_mode_status
 951 nv50_mstc_mode_valid(struct drm_connector *connector,
 952                      struct drm_display_mode *mode)
 953 {
 954         return MODE_OK;
 955 }
 956
 957 static int
 958 nv50_mstc_get_modes(struct drm_connector *connector)
 959 {
 960         struct nv50_mstc *mstc = nv50_mstc(connector);
 961         int ret = 0;
 962
 963         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 964         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 965         if (mstc->edid)
 966                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 967
 968         if (!mstc->connector.display_info.bpc)
 969                 mstc->connector.display_info.bpc = 8;
 970
 971         if (mstc->native)
 972                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 973         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 974         return ret;
 975 }
 976
 977 static int
 978 nv50_mstc_atomic_check(struct drm_connector *connector,
 979                        struct drm_atomic_state *state)
 980 {
 981         struct nv50_mstc *mstc = nv50_mstc(connector);
 982         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
 983         struct drm_connector_state *new_conn_state =
 984                 drm_atomic_get_new_connector_state(state, connector);
 985         struct drm_connector_state *old_conn_state =
 986                 drm_atomic_get_old_connector_state(state, connector);
 987         struct drm_crtc_state *crtc_state;
 988         struct drm_crtc *new_crtc = new_conn_state->crtc;
 989
 990         if (!old_conn_state->crtc)
 991                 return 0;
 992
 993         /* We only want to free VCPI if this state disables the CRTC on this
 994          * connector
 995          */
 996         if (new_crtc) {
 997                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
 998
 999                 if (!crtc_state ||
1000                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1001                     crtc_state->enable)
1002                         return 0;
1003         }
1004
1005         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1006 }
1007
1008 static int
1009 nv50_mstc_detect(struct drm_connector *connector,
1010                  struct drm_modeset_acquire_ctx *ctx, bool force)
1011 {
1012         struct nv50_mstc *mstc = nv50_mstc(connector);
1013         int ret;
1014
1015         if (drm_connector_is_unregistered(connector))
1016                 return connector_status_disconnected;
1017
1018         ret = pm_runtime_get_sync(connector->dev->dev);
1019         if (ret < 0 && ret != -EACCES)
1020                 return connector_status_disconnected;
1021
1022         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1023                                      mstc->port);
1024
1025         pm_runtime_mark_last_busy(connector->dev->dev);
1026         pm_runtime_put_autosuspend(connector->dev->dev);
1027         return ret;
1028 }
1029
1030 static const struct drm_connector_helper_funcs
1031 nv50_mstc_help = {
1032         .get_modes = nv50_mstc_get_modes,
1033         .mode_valid = nv50_mstc_mode_valid,
1034         .best_encoder = nv50_mstc_best_encoder,
1035         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1036         .atomic_check = nv50_mstc_atomic_check,
1037         .detect_ctx = nv50_mstc_detect,
1038 };
1039
1040 static void
1041 nv50_mstc_destroy(struct drm_connector *connector)
1042 {
1043         struct nv50_mstc *mstc = nv50_mstc(connector);
1044
1045         drm_connector_cleanup(&mstc->connector);
1046         drm_dp_mst_put_port_malloc(mstc->port);
1047
1048         kfree(mstc);
1049 }
1050
1051 static const struct drm_connector_funcs
1052 nv50_mstc = {
1053         .reset = nouveau_conn_reset,
1054         .fill_modes = drm_helper_probe_single_connector_modes,
1055         .destroy = nv50_mstc_destroy,
1056         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1057         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1058         .atomic_set_property = nouveau_conn_atomic_set_property,
1059         .atomic_get_property = nouveau_conn_atomic_get_property,
1060 };
1061
1062 static int
1063 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1064               const char *path, struct nv50_mstc **pmstc)
1065 {
1066         struct drm_device *dev = mstm->outp->base.base.dev;
1067         struct nv50_mstc *mstc;
1068         int ret, i;
1069
1070         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1071                 return -ENOMEM;
1072         mstc->mstm = mstm;
1073         mstc->port = port;
1074
1075         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1076                                  DRM_MODE_CONNECTOR_DisplayPort);
1077         if (ret) {
1078                 kfree(*pmstc);
1079                 *pmstc = NULL;
1080                 return ret;
1081         }
1082
1083         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1084
1085         mstc->connector.funcs->reset(&mstc->connector);
1086         nouveau_conn_attach_properties(&mstc->connector);
1087
1088         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
1089                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1090
1091         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1092         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1093         drm_connector_set_path_property(&mstc->connector, path);
1094         drm_dp_mst_get_port_malloc(port);
1095         return 0;
1096 }
1097
1098 static void
1099 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1100 {
1101         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1102         struct drm_encoder *encoder;
1103         int ret;
1104
1105         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1106         ret = drm_dp_check_act_status(&mstm->mgr);
1107
1108         ret = drm_dp_update_payload_part2(&mstm->mgr);
1109
1110         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1111                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1112                         struct nv50_msto *msto = nv50_msto(encoder);
1113                         struct nv50_mstc *mstc = msto->mstc;
1114                         if (mstc && mstc->mstm == mstm)
1115                                 nv50_msto_cleanup(msto);
1116                 }
1117         }
1118
1119         mstm->modified = false;
1120 }
1121
1122 static void
1123 nv50_mstm_prepare(struct nv50_mstm *mstm)
1124 {
1125         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1126         struct drm_encoder *encoder;
1127         int ret;
1128
1129         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1130         ret = drm_dp_update_payload_part1(&mstm->mgr);
1131
1132         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1133                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1134                         struct nv50_msto *msto = nv50_msto(encoder);
1135                         struct nv50_mstc *mstc = msto->mstc;
1136                         if (mstc && mstc->mstm == mstm)
1137                                 nv50_msto_prepare(msto);
1138                 }
1139         }
1140
1141         if (mstm->disabled) {
1142                 if (!mstm->links)
1143                         nv50_outp_release(mstm->outp);
1144                 mstm->disabled = false;
1145         }
1146 }
1147
1148 static void
1149 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1150                             struct drm_connector *connector)
1151 {
1152         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1153         struct nv50_mstc *mstc = nv50_mstc(connector);
1154
1155         drm_connector_unregister(&mstc->connector);
1156
1157         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1158
1159         drm_connector_put(&mstc->connector);
1160 }
1161
1162 static void
1163 nv50_mstm_register_connector(struct drm_connector *connector)
1164 {
1165         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1166
1167         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1168
1169         drm_connector_register(connector);
1170 }
1171
1172 static struct drm_connector *
1173 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1174                         struct drm_dp_mst_port *port, const char *path)
1175 {
1176         struct nv50_mstm *mstm = nv50_mstm(mgr);
1177         struct nv50_mstc *mstc;
1178         int ret;
1179
1180         ret = nv50_mstc_new(mstm, port, path, &mstc);
1181         if (ret)
1182                 return NULL;
1183
1184         return &mstc->connector;
1185 }
1186
1187 static const struct drm_dp_mst_topology_cbs
1188 nv50_mstm = {
1189         .add_connector = nv50_mstm_add_connector,
1190         .register_connector = nv50_mstm_register_connector,
1191         .destroy_connector = nv50_mstm_destroy_connector,
1192 };
1193
1194 void
1195 nv50_mstm_service(struct nv50_mstm *mstm)
1196 {
1197         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1198         bool handled = true;
1199         int ret;
1200         u8 esi[8] = {};
1201
1202         if (!aux)
1203                 return;
1204
1205         while (handled) {
1206                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1207                 if (ret != 8) {
1208                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1209                         return;
1210                 }
1211
1212                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1213                 if (!handled)
1214                         break;
1215
1216                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1217         }
1218 }
1219
1220 void
1221 nv50_mstm_remove(struct nv50_mstm *mstm)
1222 {
1223         if (mstm)
1224                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1225 }
1226
1227 static int
1228 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1229 {
1230         struct nouveau_encoder *outp = mstm->outp;
1231         struct {
1232                 struct nv50_disp_mthd_v1 base;
1233                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1234         } args = {
1235                 .base.version = 1,
1236                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1237                 .base.hasht = outp->dcb->hasht,
1238                 .base.hashm = outp->dcb->hashm,
1239                 .mst.state = state,
1240         };
1241         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1242         struct nvif_object *disp = &drm->display->disp.object;
1243         int ret;
1244
1245         if (dpcd >= 0x12) {
1246                 /* Even if we're enabling MST, start with disabling the
1247                  * branching unit to clear any sink-side MST topology state
1248                  * that wasn't set by us
1249                  */
1250                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1251                 if (ret < 0)
1252                         return ret;
1253
1254                 if (state) {
1255                         /* Now, start initializing */
1256                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1257                                                  DP_MST_EN);
1258                         if (ret < 0)
1259                                 return ret;
1260                 }
1261         }
1262
1263         return nvif_mthd(disp, 0, &args, sizeof(args));
1264 }
1265
1266 int
1267 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1268 {
1269         struct drm_dp_aux *aux;
1270         int ret;
1271         bool old_state, new_state;
1272         u8 mstm_ctrl;
1273
1274         if (!mstm)
1275                 return 0;
1276
1277         mutex_lock(&mstm->mgr.lock);
1278
1279         old_state = mstm->mgr.mst_state;
1280         new_state = old_state;
1281         aux = mstm->mgr.aux;
1282
1283         if (old_state) {
1284                 /* Just check that the MST hub is still as we expect it */
1285                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1286                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1287                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1288                         new_state = false;
1289                 }
1290         } else if (dpcd[0] >= 0x12) {
1291                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1292                 if (ret < 0)
1293                         goto probe_error;
1294
1295                 if (!(dpcd[1] & DP_MST_CAP))
1296                         dpcd[0] = 0x11;
1297                 else
1298                         new_state = allow;
1299         }
1300
1301         if (new_state == old_state) {
1302                 mutex_unlock(&mstm->mgr.lock);
1303                 return new_state;
1304         }
1305
1306         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1307         if (ret)
1308                 goto probe_error;
1309
1310         mutex_unlock(&mstm->mgr.lock);
1311
1312         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1313         if (ret)
1314                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1315
1316         return new_state;
1317
1318 probe_error:
1319         mutex_unlock(&mstm->mgr.lock);
1320         return ret;
1321 }
1322
1323 static void
1324 nv50_mstm_fini(struct nv50_mstm *mstm)
1325 {
1326         if (mstm && mstm->mgr.mst_state)
1327                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1328 }
1329
1330 static void
1331 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1332 {
1333         int ret;
1334
1335         if (!mstm || !mstm->mgr.mst_state)
1336                 return;
1337
1338         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1339         if (ret == -1) {
1340                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1341                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1342         }
1343 }
1344
1345 static void
1346 nv50_mstm_del(struct nv50_mstm **pmstm)
1347 {
1348         struct nv50_mstm *mstm = *pmstm;
1349         if (mstm) {
1350                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1351                 kfree(*pmstm);
1352                 *pmstm = NULL;
1353         }
1354 }
1355
1356 static int
1357 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1358               int conn_base_id, struct nv50_mstm **pmstm)
1359 {
1360         const int max_payloads = hweight8(outp->dcb->heads);
1361         struct drm_device *dev = outp->base.base.dev;
1362         struct nv50_mstm *mstm;
1363         int ret, i;
1364         u8 dpcd;
1365
1366         /* This is a workaround for some monitors not functioning
1367          * correctly in MST mode on initial module load.  I think
1368          * some bad interaction with the VBIOS may be responsible.
1369          *
1370          * A good ol' off and on again seems to work here ;)
1371          */
1372         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1373         if (ret >= 0 && dpcd >= 0x12)
1374                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1375
1376         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1377                 return -ENOMEM;
1378         mstm->outp = outp;
1379         mstm->mgr.cbs = &nv50_mstm;
1380
1381         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1382                                            max_payloads, conn_base_id);
1383         if (ret)
1384                 return ret;
1385
1386         for (i = 0; i < max_payloads; i++) {
1387                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1388                                     i, &mstm->msto[i]);
1389                 if (ret)
1390                         return ret;
1391         }
1392
1393         return 0;
1394 }
1395
1396 /******************************************************************************
1397  * SOR
1398  *****************************************************************************/
1399 static void
1400 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1401                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1402 {
1403         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1404         struct nv50_core *core = disp->core;
1405
1406         if (!asyh) {
1407                 nv_encoder->ctrl &= ~BIT(head);
1408                 if (!(nv_encoder->ctrl & 0x0000000f))
1409                         nv_encoder->ctrl = 0;
1410         } else {
1411                 nv_encoder->ctrl |= proto << 8;
1412                 nv_encoder->ctrl |= BIT(head);
1413                 asyh->or.depth = depth;
1414         }
1415
1416         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1417 }
1418
1419 static void
1420 nv50_sor_disable(struct drm_encoder *encoder)
1421 {
1422         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1423         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1424
1425         nv_encoder->crtc = NULL;
1426
1427         if (nv_crtc) {
1428                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1429                 u8 pwr;
1430
1431                 if (aux) {
1432                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1433                         if (ret == 0) {
1434                                 pwr &= ~DP_SET_POWER_MASK;
1435                                 pwr |=  DP_SET_POWER_D3;
1436                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1437                         }
1438                 }
1439
1440                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1441                 nv50_audio_disable(encoder, nv_crtc);
1442                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1443                 nv50_outp_release(nv_encoder);
1444         }
1445 }
1446
1447 static void
1448 nv50_sor_enable(struct drm_encoder *encoder)
1449 {
1450         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1451         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1452         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1453         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1454         struct {
1455                 struct nv50_disp_mthd_v1 base;
1456                 struct nv50_disp_sor_lvds_script_v0 lvds;
1457         } lvds = {
1458                 .base.version = 1,
1459                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1460                 .base.hasht   = nv_encoder->dcb->hasht,
1461                 .base.hashm   = nv_encoder->dcb->hashm,
1462         };
1463         struct nv50_disp *disp = nv50_disp(encoder->dev);
1464         struct drm_device *dev = encoder->dev;
1465         struct nouveau_drm *drm = nouveau_drm(dev);
1466         struct nouveau_connector *nv_connector;
1467         struct nvbios *bios = &drm->vbios;
1468         u8 proto = 0xf;
1469         u8 depth = 0x0;
1470
1471         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1472         nv_encoder->crtc = encoder->crtc;
1473         nv50_outp_acquire(nv_encoder);
1474
1475         switch (nv_encoder->dcb->type) {
1476         case DCB_OUTPUT_TMDS:
1477                 if (nv_encoder->link & 1) {
1478                         proto = 0x1;
1479                         /* Only enable dual-link if:
1480                          *  - Need to (i.e. rate > 165MHz)
1481                          *  - DCB says we can
1482                          *  - Not an HDMI monitor, since there's no dual-link
1483                          *    on HDMI.
1484                          */
1485                         if (mode->clock >= 165000 &&
1486                             nv_encoder->dcb->duallink_possible &&
1487                             !drm_detect_hdmi_monitor(nv_connector->edid))
1488                                 proto |= 0x4;
1489                 } else {
1490                         proto = 0x2;
1491                 }
1492
1493                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1494                 break;
1495         case DCB_OUTPUT_LVDS:
1496                 proto = 0x0;
1497
1498                 if (bios->fp_no_ddc) {
1499                         if (bios->fp.dual_link)
1500                                 lvds.lvds.script |= 0x0100;
1501                         if (bios->fp.if_is_24bit)
1502                                 lvds.lvds.script |= 0x0200;
1503                 } else {
1504                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1505                                 if (((u8 *)nv_connector->edid)[121] == 2)
1506                                         lvds.lvds.script |= 0x0100;
1507                         } else
1508                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1509                                 lvds.lvds.script |= 0x0100;
1510                         }
1511
1512                         if (lvds.lvds.script & 0x0100) {
1513                                 if (bios->fp.strapless_is_24bit & 2)
1514                                         lvds.lvds.script |= 0x0200;
1515                         } else {
1516                                 if (bios->fp.strapless_is_24bit & 1)
1517                                         lvds.lvds.script |= 0x0200;
1518                         }
1519
1520                         if (asyh->or.bpc == 8)
1521                                 lvds.lvds.script |= 0x0200;
1522                 }
1523
1524                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1525                 break;
1526         case DCB_OUTPUT_DP:
1527                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1528
1529                 if (nv_encoder->link & 1)
1530                         proto = 0x8;
1531                 else
1532                         proto = 0x9;
1533
1534                 nv50_audio_enable(encoder, mode);
1535                 break;
1536         default:
1537                 BUG();
1538                 break;
1539         }
1540
1541         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1542 }
1543
1544 static const struct drm_encoder_helper_funcs
1545 nv50_sor_help = {
1546         .atomic_check = nv50_outp_atomic_check,
1547         .enable = nv50_sor_enable,
1548         .disable = nv50_sor_disable,
1549 };
1550
1551 static void
1552 nv50_sor_destroy(struct drm_encoder *encoder)
1553 {
1554         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1555         nv50_mstm_del(&nv_encoder->dp.mstm);
1556         drm_encoder_cleanup(encoder);
1557         kfree(encoder);
1558 }
1559
1560 static const struct drm_encoder_funcs
1561 nv50_sor_func = {
1562         .destroy = nv50_sor_destroy,
1563 };
1564
1565 static int
1566 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1567 {
1568         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1569         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1570         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1571         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1572         struct nouveau_encoder *nv_encoder;
1573         struct drm_encoder *encoder;
1574         u8 ver, hdr, cnt, len;
1575         u32 data;
1576         int type, ret;
1577
1578         switch (dcbe->type) {
1579         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1580         case DCB_OUTPUT_TMDS:
1581         case DCB_OUTPUT_DP:
1582         default:
1583                 type = DRM_MODE_ENCODER_TMDS;
1584                 break;
1585         }
1586
1587         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1588         if (!nv_encoder)
1589                 return -ENOMEM;
1590         nv_encoder->dcb = dcbe;
1591         nv_encoder->update = nv50_sor_update;
1592
1593         encoder = to_drm_encoder(nv_encoder);
1594         encoder->possible_crtcs = dcbe->heads;
1595         encoder->possible_clones = 0;
1596         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1597                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1598         drm_encoder_helper_add(encoder, &nv50_sor_help);
1599
1600         drm_connector_attach_encoder(connector, encoder);
1601
1602         if (dcbe->type == DCB_OUTPUT_DP) {
1603                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1604                 struct nvkm_i2c_aux *aux =
1605                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1606                 if (aux) {
1607                         if (disp->disp->object.oclass < GF110_DISP) {
1608                                 /* HW has no support for address-only
1609                                  * transactions, so we're required to
1610                                  * use custom I2C-over-AUX code.
1611                                  */
1612                                 nv_encoder->i2c = &aux->i2c;
1613                         } else {
1614                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1615                         }
1616                         nv_encoder->aux = aux;
1617                 }
1618
1619                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1620                     (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1621                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1622                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1623                                             nv_connector->base.base.id,
1624                                             &nv_encoder->dp.mstm);
1625                         if (ret)
1626                                 return ret;
1627                 }
1628         } else {
1629                 struct nvkm_i2c_bus *bus =
1630                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1631                 if (bus)
1632                         nv_encoder->i2c = &bus->i2c;
1633         }
1634
1635         return 0;
1636 }
1637
1638 /******************************************************************************
1639  * PIOR
1640  *****************************************************************************/
1641 static int
1642 nv50_pior_atomic_check(struct drm_encoder *encoder,
1643                        struct drm_crtc_state *crtc_state,
1644                        struct drm_connector_state *conn_state)
1645 {
1646         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1647         if (ret)
1648                 return ret;
1649         crtc_state->adjusted_mode.clock *= 2;
1650         return 0;
1651 }
1652
1653 static void
1654 nv50_pior_disable(struct drm_encoder *encoder)
1655 {
1656         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1657         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1658         if (nv_encoder->crtc)
1659                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1660         nv_encoder->crtc = NULL;
1661         nv50_outp_release(nv_encoder);
1662 }
1663
1664 static void
1665 nv50_pior_enable(struct drm_encoder *encoder)
1666 {
1667         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1668         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1669         struct nouveau_connector *nv_connector;
1670         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1671         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1672         u8 owner = 1 << nv_crtc->index;
1673         u8 proto;
1674
1675         nv50_outp_acquire(nv_encoder);
1676
1677         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1678         switch (asyh->or.bpc) {
1679         case 10: asyh->or.depth = 0x6; break;
1680         case  8: asyh->or.depth = 0x5; break;
1681         case  6: asyh->or.depth = 0x2; break;
1682         default: asyh->or.depth = 0x0; break;
1683         }
1684
1685         switch (nv_encoder->dcb->type) {
1686         case DCB_OUTPUT_TMDS:
1687         case DCB_OUTPUT_DP:
1688                 proto = 0x0;
1689                 break;
1690         default:
1691                 BUG();
1692                 break;
1693         }
1694
1695         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1696         nv_encoder->crtc = encoder->crtc;
1697 }
1698
1699 static const struct drm_encoder_helper_funcs
1700 nv50_pior_help = {
1701         .atomic_check = nv50_pior_atomic_check,
1702         .enable = nv50_pior_enable,
1703         .disable = nv50_pior_disable,
1704 };
1705
1706 static void
1707 nv50_pior_destroy(struct drm_encoder *encoder)
1708 {
1709         drm_encoder_cleanup(encoder);
1710         kfree(encoder);
1711 }
1712
1713 static const struct drm_encoder_funcs
1714 nv50_pior_func = {
1715         .destroy = nv50_pior_destroy,
1716 };
1717
1718 static int
1719 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1720 {
1721         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1722         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1723         struct nvkm_i2c_bus *bus = NULL;
1724         struct nvkm_i2c_aux *aux = NULL;
1725         struct i2c_adapter *ddc;
1726         struct nouveau_encoder *nv_encoder;
1727         struct drm_encoder *encoder;
1728         int type;
1729
1730         switch (dcbe->type) {
1731         case DCB_OUTPUT_TMDS:
1732                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1733                 ddc  = bus ? &bus->i2c : NULL;
1734                 type = DRM_MODE_ENCODER_TMDS;
1735                 break;
1736         case DCB_OUTPUT_DP:
1737                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1738                 ddc  = aux ? &aux->i2c : NULL;
1739                 type = DRM_MODE_ENCODER_TMDS;
1740                 break;
1741         default:
1742                 return -ENODEV;
1743         }
1744
1745         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1746         if (!nv_encoder)
1747                 return -ENOMEM;
1748         nv_encoder->dcb = dcbe;
1749         nv_encoder->i2c = ddc;
1750         nv_encoder->aux = aux;
1751
1752         encoder = to_drm_encoder(nv_encoder);
1753         encoder->possible_crtcs = dcbe->heads;
1754         encoder->possible_clones = 0;
1755         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1756                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1757         drm_encoder_helper_add(encoder, &nv50_pior_help);
1758
1759         drm_connector_attach_encoder(connector, encoder);
1760         return 0;
1761 }
1762
1763 /******************************************************************************
1764  * Atomic
1765  *****************************************************************************/
1766
1767 static void
1768 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1769 {
1770         struct nouveau_drm *drm = nouveau_drm(state->dev);
1771         struct nv50_disp *disp = nv50_disp(drm->dev);
1772         struct nv50_core *core = disp->core;
1773         struct nv50_mstm *mstm;
1774         struct drm_encoder *encoder;
1775
1776         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1777
1778         drm_for_each_encoder(encoder, drm->dev) {
1779                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1780                         mstm = nouveau_encoder(encoder)->dp.mstm;
1781                         if (mstm && mstm->modified)
1782                                 nv50_mstm_prepare(mstm);
1783                 }
1784         }
1785
1786         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1787         core->func->update(core, interlock, true);
1788         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1789                                        disp->core->chan.base.device))
1790                 NV_ERROR(drm, "core notifier timeout\n");
1791
1792         drm_for_each_encoder(encoder, drm->dev) {
1793                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1794                         mstm = nouveau_encoder(encoder)->dp.mstm;
1795                         if (mstm && mstm->modified)
1796                                 nv50_mstm_cleanup(mstm);
1797                 }
1798         }
1799 }
1800
1801 static void
1802 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1803 {
1804         struct drm_plane_state *new_plane_state;
1805         struct drm_plane *plane;
1806         int i;
1807
1808         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1809                 struct nv50_wndw *wndw = nv50_wndw(plane);
1810                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1811                         if (wndw->func->update)
1812                                 wndw->func->update(wndw, interlock);
1813                 }
1814         }
1815 }
1816
1817 static void
1818 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1819 {
1820         struct drm_device *dev = state->dev;
1821         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1822         struct drm_crtc *crtc;
1823         struct drm_plane_state *new_plane_state;
1824         struct drm_plane *plane;
1825         struct nouveau_drm *drm = nouveau_drm(dev);
1826         struct nv50_disp *disp = nv50_disp(dev);
1827         struct nv50_atom *atom = nv50_atom(state);
1828         struct nv50_outp_atom *outp, *outt;
1829         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1830         int i;
1831
1832         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1833         drm_atomic_helper_wait_for_fences(dev, state, false);
1834         drm_atomic_helper_wait_for_dependencies(state);
1835         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1836
1837         if (atom->lock_core)
1838                 mutex_lock(&disp->mutex);
1839
1840         /* Disable head(s). */
1841         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1842                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1843                 struct nv50_head *head = nv50_head(crtc);
1844
1845                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1846                           asyh->clr.mask, asyh->set.mask);
1847
1848                 if (old_crtc_state->active && !new_crtc_state->active) {
1849                         pm_runtime_put_noidle(dev->dev);
1850                         drm_crtc_vblank_off(crtc);
1851                 }
1852
1853                 if (asyh->clr.mask) {
1854                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1855                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1856                 }
1857         }
1858
1859         /* Disable plane(s). */
1860         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1861                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1862                 struct nv50_wndw *wndw = nv50_wndw(plane);
1863
1864                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1865                           asyw->clr.mask, asyw->set.mask);
1866                 if (!asyw->clr.mask)
1867                         continue;
1868
1869                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1870         }
1871
1872         /* Disable output path(s). */
1873         list_for_each_entry(outp, &atom->outp, head) {
1874                 const struct drm_encoder_helper_funcs *help;
1875                 struct drm_encoder *encoder;
1876
1877                 encoder = outp->encoder;
1878                 help = encoder->helper_private;
1879
1880                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1881                           outp->clr.mask, outp->set.mask);
1882
1883                 if (outp->clr.mask) {
1884                         help->disable(encoder);
1885                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1886                         if (outp->flush_disable) {
1887                                 nv50_disp_atomic_commit_wndw(state, interlock);
1888                                 nv50_disp_atomic_commit_core(state, interlock);
1889                                 memset(interlock, 0x00, sizeof(interlock));
1890                         }
1891                 }
1892         }
1893
1894         /* Flush disable. */
1895         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1896                 if (atom->flush_disable) {
1897                         nv50_disp_atomic_commit_wndw(state, interlock);
1898                         nv50_disp_atomic_commit_core(state, interlock);
1899                         memset(interlock, 0x00, sizeof(interlock));
1900                 }
1901         }
1902
1903         /* Update output path(s). */
1904         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1905                 const struct drm_encoder_helper_funcs *help;
1906                 struct drm_encoder *encoder;
1907
1908                 encoder = outp->encoder;
1909                 help = encoder->helper_private;
1910
1911                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1912                           outp->set.mask, outp->clr.mask);
1913
1914                 if (outp->set.mask) {
1915                         help->enable(encoder);
1916                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1917                 }
1918
1919                 list_del(&outp->head);
1920                 kfree(outp);
1921         }
1922
1923         /* Update head(s). */
1924         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1925                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1926                 struct nv50_head *head = nv50_head(crtc);
1927
1928                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1929                           asyh->set.mask, asyh->clr.mask);
1930
1931                 if (asyh->set.mask) {
1932                         nv50_head_flush_set(head, asyh);
1933                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1934                 }
1935
1936                 if (new_crtc_state->active) {
1937                         if (!old_crtc_state->active) {
1938                                 drm_crtc_vblank_on(crtc);
1939                                 pm_runtime_get_noresume(dev->dev);
1940                         }
1941                         if (new_crtc_state->event)
1942                                 drm_crtc_vblank_get(crtc);
1943                 }
1944         }
1945
1946         /* Update plane(s). */
1947         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1948                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1949                 struct nv50_wndw *wndw = nv50_wndw(plane);
1950
1951                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1952                           asyw->set.mask, asyw->clr.mask);
1953                 if ( !asyw->set.mask &&
1954                     (!asyw->clr.mask || atom->flush_disable))
1955                         continue;
1956
1957                 nv50_wndw_flush_set(wndw, interlock, asyw);
1958         }
1959
1960         /* Flush update. */
1961         nv50_disp_atomic_commit_wndw(state, interlock);
1962
1963         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1964                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1965                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1966                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1967                     !atom->state.legacy_cursor_update)
1968                         nv50_disp_atomic_commit_core(state, interlock);
1969                 else
1970                         disp->core->func->update(disp->core, interlock, false);
1971         }
1972
1973         if (atom->lock_core)
1974                 mutex_unlock(&disp->mutex);
1975
1976         /* Wait for HW to signal completion. */
1977         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1978                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1979                 struct nv50_wndw *wndw = nv50_wndw(plane);
1980                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1981                 if (ret)
1982                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1983         }
1984
1985         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1986                 if (new_crtc_state->event) {
1987                         unsigned long flags;
1988                         /* Get correct count/ts if racing with vblank irq */
1989                         if (new_crtc_state->active)
1990                                 drm_crtc_accurate_vblank_count(crtc);
1991                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1992                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1993                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1994
1995                         new_crtc_state->event = NULL;
1996                         if (new_crtc_state->active)
1997                                 drm_crtc_vblank_put(crtc);
1998                 }
1999         }
2000
2001         drm_atomic_helper_commit_hw_done(state);
2002         drm_atomic_helper_cleanup_planes(dev, state);
2003         drm_atomic_helper_commit_cleanup_done(state);
2004         drm_atomic_state_put(state);
2005
2006         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2007         pm_runtime_mark_last_busy(dev->dev);
2008         pm_runtime_put_autosuspend(dev->dev);
2009 }
2010
2011 static void
2012 nv50_disp_atomic_commit_work(struct work_struct *work)
2013 {
2014         struct drm_atomic_state *state =
2015                 container_of(work, typeof(*state), commit_work);
2016         nv50_disp_atomic_commit_tail(state);
2017 }
2018
2019 static int
2020 nv50_disp_atomic_commit(struct drm_device *dev,
2021                         struct drm_atomic_state *state, bool nonblock)
2022 {
2023         struct drm_plane_state *new_plane_state;
2024         struct drm_plane *plane;
2025         int ret, i;
2026
2027         ret = pm_runtime_get_sync(dev->dev);
2028         if (ret < 0 && ret != -EACCES)
2029                 return ret;
2030
2031         ret = drm_atomic_helper_setup_commit(state, nonblock);
2032         if (ret)
2033                 goto done;
2034
2035         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2036
2037         ret = drm_atomic_helper_prepare_planes(dev, state);
2038         if (ret)
2039                 goto done;
2040
2041         if (!nonblock) {
2042                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2043                 if (ret)
2044                         goto err_cleanup;
2045         }
2046
2047         ret = drm_atomic_helper_swap_state(state, true);
2048         if (ret)
2049                 goto err_cleanup;
2050
2051         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2052                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2053                 struct nv50_wndw *wndw = nv50_wndw(plane);
2054
2055                 if (asyw->set.image)
2056                         nv50_wndw_ntfy_enable(wndw, asyw);
2057         }
2058
2059         drm_atomic_state_get(state);
2060
2061         /*
2062          * Grab another RPM ref for the commit tail, which will release the
2063          * ref when it's finished
2064          */
2065         pm_runtime_get_noresume(dev->dev);
2066
2067         if (nonblock)
2068                 queue_work(system_unbound_wq, &state->commit_work);
2069         else
2070                 nv50_disp_atomic_commit_tail(state);
2071
2072 err_cleanup:
2073         if (ret)
2074                 drm_atomic_helper_cleanup_planes(dev, state);
2075 done:
2076         pm_runtime_put_autosuspend(dev->dev);
2077         return ret;
2078 }
2079
2080 static struct nv50_outp_atom *
2081 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2082 {
2083         struct nv50_outp_atom *outp;
2084
2085         list_for_each_entry(outp, &atom->outp, head) {
2086                 if (outp->encoder == encoder)
2087                         return outp;
2088         }
2089
2090         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2091         if (!outp)
2092                 return ERR_PTR(-ENOMEM);
2093
2094         list_add(&outp->head, &atom->outp);
2095         outp->encoder = encoder;
2096         return outp;
2097 }
2098
2099 static int
2100 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2101                                 struct drm_connector_state *old_connector_state)
2102 {
2103         struct drm_encoder *encoder = old_connector_state->best_encoder;
2104         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2105         struct drm_crtc *crtc;
2106         struct nv50_outp_atom *outp;
2107
2108         if (!(crtc = old_connector_state->crtc))
2109                 return 0;
2110
2111         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2112         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2113         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2114                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2115                 if (IS_ERR(outp))
2116                         return PTR_ERR(outp);
2117
2118                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2119                         outp->flush_disable = true;
2120                         atom->flush_disable = true;
2121                 }
2122                 outp->clr.ctrl = true;
2123                 atom->lock_core = true;
2124         }
2125
2126         return 0;
2127 }
2128
2129 static int
2130 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2131                                 struct drm_connector_state *connector_state)
2132 {
2133         struct drm_encoder *encoder = connector_state->best_encoder;
2134         struct drm_crtc_state *new_crtc_state;
2135         struct drm_crtc *crtc;
2136         struct nv50_outp_atom *outp;
2137
2138         if (!(crtc = connector_state->crtc))
2139                 return 0;
2140
2141         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2142         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2143                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2144                 if (IS_ERR(outp))
2145                         return PTR_ERR(outp);
2146
2147                 outp->set.ctrl = true;
2148                 atom->lock_core = true;
2149         }
2150
2151         return 0;
2152 }
2153
2154 static int
2155 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2156 {
2157         struct nv50_atom *atom = nv50_atom(state);
2158         struct drm_connector_state *old_connector_state, *new_connector_state;
2159         struct drm_connector *connector;
2160         struct drm_crtc_state *new_crtc_state;
2161         struct drm_crtc *crtc;
2162         int ret, i;
2163
2164         /* We need to handle colour management on a per-plane basis. */
2165         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2166                 if (new_crtc_state->color_mgmt_changed) {
2167                         ret = drm_atomic_add_affected_planes(state, crtc);
2168                         if (ret)
2169                                 return ret;
2170                 }
2171         }
2172
2173         ret = drm_atomic_helper_check(dev, state);
2174         if (ret)
2175                 return ret;
2176
2177         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2178                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2179                 if (ret)
2180                         return ret;
2181
2182                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2183                 if (ret)
2184                         return ret;
2185         }
2186
2187         ret = drm_dp_mst_atomic_check(state);
2188         if (ret)
2189                 return ret;
2190
2191         return 0;
2192 }
2193
2194 static void
2195 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2196 {
2197         struct nv50_atom *atom = nv50_atom(state);
2198         struct nv50_outp_atom *outp, *outt;
2199
2200         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2201                 list_del(&outp->head);
2202                 kfree(outp);
2203         }
2204
2205         drm_atomic_state_default_clear(state);
2206 }
2207
2208 static void
2209 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2210 {
2211         struct nv50_atom *atom = nv50_atom(state);
2212         drm_atomic_state_default_release(&atom->state);
2213         kfree(atom);
2214 }
2215
2216 static struct drm_atomic_state *
2217 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2218 {
2219         struct nv50_atom *atom;
2220         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2221             drm_atomic_state_init(dev, &atom->state) < 0) {
2222                 kfree(atom);
2223                 return NULL;
2224         }
2225         INIT_LIST_HEAD(&atom->outp);
2226         return &atom->state;
2227 }
2228
2229 static const struct drm_mode_config_funcs
2230 nv50_disp_func = {
2231         .fb_create = nouveau_user_framebuffer_create,
2232         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2233         .atomic_check = nv50_disp_atomic_check,
2234         .atomic_commit = nv50_disp_atomic_commit,
2235         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2236         .atomic_state_clear = nv50_disp_atomic_state_clear,
2237         .atomic_state_free = nv50_disp_atomic_state_free,
2238 };
2239
2240 /******************************************************************************
2241  * Init
2242  *****************************************************************************/
2243
2244 static void
2245 nv50_display_fini(struct drm_device *dev, bool suspend)
2246 {
2247         struct nouveau_encoder *nv_encoder;
2248         struct drm_encoder *encoder;
2249         struct drm_plane *plane;
2250
2251         drm_for_each_plane(plane, dev) {
2252                 struct nv50_wndw *wndw = nv50_wndw(plane);
2253                 if (plane->funcs != &nv50_wndw)
2254                         continue;
2255                 nv50_wndw_fini(wndw);
2256         }
2257
2258         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2259                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2260                         nv_encoder = nouveau_encoder(encoder);
2261                         nv50_mstm_fini(nv_encoder->dp.mstm);
2262                 }
2263         }
2264 }
2265
2266 static int
2267 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2268 {
2269         struct nv50_core *core = nv50_disp(dev)->core;
2270         struct drm_encoder *encoder;
2271         struct drm_plane *plane;
2272
2273         core->func->init(core);
2274
2275         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2276                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2277                         struct nouveau_encoder *nv_encoder =
2278                                 nouveau_encoder(encoder);
2279                         nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2280                 }
2281         }
2282
2283         drm_for_each_plane(plane, dev) {
2284                 struct nv50_wndw *wndw = nv50_wndw(plane);
2285                 if (plane->funcs != &nv50_wndw)
2286                         continue;
2287                 nv50_wndw_init(wndw);
2288         }
2289
2290         return 0;
2291 }
2292
2293 static void
2294 nv50_display_destroy(struct drm_device *dev)
2295 {
2296         struct nv50_disp *disp = nv50_disp(dev);
2297
2298         nv50_core_del(&disp->core);
2299
2300         nouveau_bo_unmap(disp->sync);
2301         if (disp->sync)
2302                 nouveau_bo_unpin(disp->sync);
2303         nouveau_bo_ref(NULL, &disp->sync);
2304
2305         nouveau_display(dev)->priv = NULL;
2306         kfree(disp);
2307 }
2308
2309 int
2310 nv50_display_create(struct drm_device *dev)
2311 {
2312         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2313         struct nouveau_drm *drm = nouveau_drm(dev);
2314         struct dcb_table *dcb = &drm->vbios.dcb;
2315         struct drm_connector *connector, *tmp;
2316         struct nv50_disp *disp;
2317         struct dcb_output *dcbe;
2318         int crtcs, ret, i;
2319
2320         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2321         if (!disp)
2322                 return -ENOMEM;
2323
2324         mutex_init(&disp->mutex);
2325
2326         nouveau_display(dev)->priv = disp;
2327         nouveau_display(dev)->dtor = nv50_display_destroy;
2328         nouveau_display(dev)->init = nv50_display_init;
2329         nouveau_display(dev)->fini = nv50_display_fini;
2330         disp->disp = &nouveau_display(dev)->disp;
2331         dev->mode_config.funcs = &nv50_disp_func;
2332         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2333         dev->mode_config.normalize_zpos = true;
2334
2335         /* small shared memory area we use for notifiers and semaphores */
2336         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2337                              0, 0x0000, NULL, NULL, &disp->sync);
2338         if (!ret) {
2339                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2340                 if (!ret) {
2341                         ret = nouveau_bo_map(disp->sync);
2342                         if (ret)
2343                                 nouveau_bo_unpin(disp->sync);
2344                 }
2345                 if (ret)
2346                         nouveau_bo_ref(NULL, &disp->sync);
2347         }
2348
2349         if (ret)
2350                 goto out;
2351
2352         /* allocate master evo channel */
2353         ret = nv50_core_new(drm, &disp->core);
2354         if (ret)
2355                 goto out;
2356
2357         /* create crtc objects to represent the hw heads */
2358         if (disp->disp->object.oclass >= GV100_DISP)
2359                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2360         else
2361         if (disp->disp->object.oclass >= GF110_DISP)
2362                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2363         else
2364                 crtcs = 0x3;
2365
2366         for (i = 0; i < fls(crtcs); i++) {
2367                 if (!(crtcs & (1 << i)))
2368                         continue;
2369                 ret = nv50_head_create(dev, i);
2370                 if (ret)
2371                         goto out;
2372         }
2373
2374         /* create encoder/connector objects based on VBIOS DCB table */
2375         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2376                 connector = nouveau_connector_create(dev, dcbe);
2377                 if (IS_ERR(connector))
2378                         continue;
2379
2380                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2381                         switch (dcbe->type) {
2382                         case DCB_OUTPUT_TMDS:
2383                         case DCB_OUTPUT_LVDS:
2384                         case DCB_OUTPUT_DP:
2385                                 ret = nv50_sor_create(connector, dcbe);
2386                                 break;
2387                         case DCB_OUTPUT_ANALOG:
2388                                 ret = nv50_dac_create(connector, dcbe);
2389                                 break;
2390                         default:
2391                                 ret = -ENODEV;
2392                                 break;
2393                         }
2394                 } else {
2395                         ret = nv50_pior_create(connector, dcbe);
2396                 }
2397
2398                 if (ret) {
2399                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2400                                      dcbe->location, dcbe->type,
2401                                      ffs(dcbe->or) - 1, ret);
2402                         ret = 0;
2403                 }
2404         }
2405
2406         /* cull any connectors we created that don't have an encoder */
2407         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2408                 if (connector->possible_encoders)
2409                         continue;
2410
2411                 NV_WARN(drm, "%s has no encoders, removing\n",
2412                         connector->name);
2413                 connector->funcs->destroy(connector);
2414         }
2415
2416         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2417         dev->vblank_disable_immediate = true;
2418
2419 out:
2420         if (ret)
2421                 nv50_display_destroy(dev);
2422         return ret;
2423 }