2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/dma-mapping.h>
31 #include <linux/hdmi.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_dp_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_fb_helper.h>
37 #include <drm/drm_plane_helper.h>
38 #include <drm/drm_probe_helper.h>
39 #include <drm/drm_scdc_helper.h>
40 #include <drm/drm_vblank.h>
42 #include <nvif/class.h>
43 #include <nvif/cl0002.h>
44 #include <nvif/cl5070.h>
45 #include <nvif/cl507d.h>
46 #include <nvif/event.h>
48 #include "nouveau_drv.h"
49 #include "nouveau_dma.h"
50 #include "nouveau_gem.h"
51 #include "nouveau_connector.h"
52 #include "nouveau_encoder.h"
53 #include "nouveau_fence.h"
54 #include "nouveau_fbcon.h"
56 #include <subdev/bios/dp.h>
58 /******************************************************************************
60 *****************************************************************************/
62 struct nv50_outp_atom {
63 struct list_head head;
65 struct drm_encoder *encoder;
68 union nv50_outp_atom_mask {
76 /******************************************************************************
78 *****************************************************************************/
81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
82 const s32 *oclass, u8 head, void *data, u32 size,
83 struct nv50_chan *chan)
85 struct nvif_sclass *sclass;
88 chan->device = device;
90 ret = n = nvif_object_sclass_get(disp, &sclass);
95 for (i = 0; i < n; i++) {
96 if (sclass[i].oclass == oclass[0]) {
97 ret = nvif_object_init(disp, 0, oclass[0],
98 data, size, &chan->user);
100 nvif_object_map(&chan->user, NULL, 0);
101 nvif_object_sclass_put(&sclass);
108 nvif_object_sclass_put(&sclass);
113 nv50_chan_destroy(struct nv50_chan *chan)
115 nvif_object_fini(&chan->user);
118 /******************************************************************************
120 *****************************************************************************/
123 nv50_dmac_destroy(struct nv50_dmac *dmac)
125 nvif_object_fini(&dmac->vram);
126 nvif_object_fini(&dmac->sync);
128 nv50_chan_destroy(&dmac->base);
130 nvif_mem_fini(&dmac->push);
134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
135 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
136 struct nv50_dmac *dmac)
138 struct nouveau_cli *cli = (void *)device->object.client;
139 struct nv50_disp_core_channel_dma_v0 *args = data;
140 u8 type = NVIF_MEM_COHERENT;
143 mutex_init(&dmac->lock);
145 /* Pascal added support for 47-bit physical addresses, but some
146 * parts of EVO still only accept 40-bit PAs.
148 * To avoid issues on systems with large amounts of RAM, and on
149 * systems where an IOMMU maps pages at a high address, we need
150 * to allocate push buffers in VRAM instead.
152 * This appears to match NVIDIA's behaviour on Pascal.
154 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
155 type |= NVIF_MEM_VRAM;
157 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
161 dmac->ptr = dmac->push.object.map.ptr;
163 args->pushbuf = nvif_handle(&dmac->push.object);
165 ret = nv50_chan_create(device, disp, oclass, head, data, size,
173 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
174 &(struct nv_dma_v0) {
175 .target = NV_DMA_V0_TARGET_VRAM,
176 .access = NV_DMA_V0_ACCESS_RDWR,
177 .start = syncbuf + 0x0000,
178 .limit = syncbuf + 0x0fff,
179 }, sizeof(struct nv_dma_v0),
184 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
185 &(struct nv_dma_v0) {
186 .target = NV_DMA_V0_TARGET_VRAM,
187 .access = NV_DMA_V0_ACCESS_RDWR,
189 .limit = device->info.ram_user - 1,
190 }, sizeof(struct nv_dma_v0),
198 /******************************************************************************
199 * EVO channel helpers
200 *****************************************************************************/
202 evo_flush(struct nv50_dmac *dmac)
204 /* Push buffer fetches are not coherent with BAR1, we need to ensure
205 * writes have been flushed right through to VRAM before writing PUT.
207 if (dmac->push.type & NVIF_MEM_VRAM) {
208 struct nvif_device *device = dmac->base.device;
209 nvif_wr32(&device->object, 0x070000, 0x00000001);
210 nvif_msec(device, 2000,
211 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
218 evo_wait(struct nv50_dmac *evoc, int nr)
220 struct nv50_dmac *dmac = evoc;
221 struct nvif_device *device = dmac->base.device;
222 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
224 mutex_lock(&dmac->lock);
225 if (put + nr >= (PAGE_SIZE / 4) - 8) {
226 dmac->ptr[put] = 0x20000000;
229 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
230 if (nvif_msec(device, 2000,
231 if (!nvif_rd32(&dmac->base.user, 0x0004))
234 mutex_unlock(&dmac->lock);
235 pr_err("nouveau: evo channel stalled\n");
242 return dmac->ptr + put;
246 evo_kick(u32 *push, struct nv50_dmac *evoc)
248 struct nv50_dmac *dmac = evoc;
252 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
253 mutex_unlock(&dmac->lock);
256 /******************************************************************************
257 * Output path helpers
258 *****************************************************************************/
260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
262 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
264 struct nv50_disp_mthd_v1 base;
267 .base.method = NV50_DISP_MTHD_V1_RELEASE,
268 .base.hasht = nv_encoder->dcb->hasht,
269 .base.hashm = nv_encoder->dcb->hashm,
272 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
274 nv_encoder->link = 0;
278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
280 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
281 struct nv50_disp *disp = nv50_disp(drm->dev);
283 struct nv50_disp_mthd_v1 base;
284 struct nv50_disp_acquire_v0 info;
287 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
288 .base.hasht = nv_encoder->dcb->hasht,
289 .base.hashm = nv_encoder->dcb->hashm,
293 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
295 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
299 nv_encoder->or = args.info.or;
300 nv_encoder->link = args.info.link;
305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
306 struct drm_crtc_state *crtc_state,
307 struct drm_connector_state *conn_state,
308 struct drm_display_mode *native_mode)
310 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
311 struct drm_display_mode *mode = &crtc_state->mode;
312 struct drm_connector *connector = conn_state->connector;
313 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
314 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
316 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
317 asyc->scaler.full = false;
321 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
322 switch (connector->connector_type) {
323 case DRM_MODE_CONNECTOR_LVDS:
324 case DRM_MODE_CONNECTOR_eDP:
325 /* Don't force scaler for EDID modes with
326 * same size as the native one (e.g. different
329 if (adjusted_mode->hdisplay == native_mode->hdisplay &&
330 adjusted_mode->vdisplay == native_mode->vdisplay &&
331 adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
334 asyc->scaler.full = true;
343 if (!drm_mode_equal(adjusted_mode, mode)) {
344 drm_mode_copy(adjusted_mode, mode);
345 crtc_state->mode_changed = true;
352 nv50_outp_atomic_check(struct drm_encoder *encoder,
353 struct drm_crtc_state *crtc_state,
354 struct drm_connector_state *conn_state)
356 struct nouveau_connector *nv_connector =
357 nouveau_connector(conn_state->connector);
358 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
359 nv_connector->native_mode);
362 /******************************************************************************
364 *****************************************************************************/
366 nv50_dac_disable(struct drm_encoder *encoder)
368 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
369 struct nv50_core *core = nv50_disp(encoder->dev)->core;
370 if (nv_encoder->crtc)
371 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
372 nv_encoder->crtc = NULL;
373 nv50_outp_release(nv_encoder);
377 nv50_dac_enable(struct drm_encoder *encoder)
379 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
380 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
381 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
382 struct nv50_core *core = nv50_disp(encoder->dev)->core;
384 nv50_outp_acquire(nv_encoder);
386 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
389 nv_encoder->crtc = encoder->crtc;
392 static enum drm_connector_status
393 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
395 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
396 struct nv50_disp *disp = nv50_disp(encoder->dev);
398 struct nv50_disp_mthd_v1 base;
399 struct nv50_disp_dac_load_v0 load;
402 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
403 .base.hasht = nv_encoder->dcb->hasht,
404 .base.hashm = nv_encoder->dcb->hashm,
408 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
409 if (args.load.data == 0)
410 args.load.data = 340;
412 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
413 if (ret || !args.load.load)
414 return connector_status_disconnected;
416 return connector_status_connected;
419 static const struct drm_encoder_helper_funcs
421 .atomic_check = nv50_outp_atomic_check,
422 .enable = nv50_dac_enable,
423 .disable = nv50_dac_disable,
424 .detect = nv50_dac_detect
428 nv50_dac_destroy(struct drm_encoder *encoder)
430 drm_encoder_cleanup(encoder);
434 static const struct drm_encoder_funcs
436 .destroy = nv50_dac_destroy,
440 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
442 struct nouveau_drm *drm = nouveau_drm(connector->dev);
443 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
444 struct nvkm_i2c_bus *bus;
445 struct nouveau_encoder *nv_encoder;
446 struct drm_encoder *encoder;
447 int type = DRM_MODE_ENCODER_DAC;
449 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
452 nv_encoder->dcb = dcbe;
454 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
456 nv_encoder->i2c = &bus->i2c;
458 encoder = to_drm_encoder(nv_encoder);
459 encoder->possible_crtcs = dcbe->heads;
460 encoder->possible_clones = 0;
461 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
462 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
463 drm_encoder_helper_add(encoder, &nv50_dac_help);
465 drm_connector_attach_encoder(connector, encoder);
469 /******************************************************************************
471 *****************************************************************************/
473 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
475 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
476 struct nv50_disp *disp = nv50_disp(encoder->dev);
478 struct nv50_disp_mthd_v1 base;
479 struct nv50_disp_sor_hda_eld_v0 eld;
482 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
483 .base.hasht = nv_encoder->dcb->hasht,
484 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
485 (0x0100 << nv_crtc->index),
488 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
492 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
494 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
495 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
496 struct nouveau_connector *nv_connector;
497 struct nv50_disp *disp = nv50_disp(encoder->dev);
500 struct nv50_disp_mthd_v1 mthd;
501 struct nv50_disp_sor_hda_eld_v0 eld;
503 u8 data[sizeof(nv_connector->base.eld)];
505 .base.mthd.version = 1,
506 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
507 .base.mthd.hasht = nv_encoder->dcb->hasht,
508 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
509 (0x0100 << nv_crtc->index),
512 nv_connector = nouveau_encoder_connector_get(nv_encoder);
513 if (!drm_detect_monitor_audio(nv_connector->edid))
516 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
518 nvif_mthd(&disp->disp->object, 0, &args,
519 sizeof(args.base) + drm_eld_size(args.data));
522 /******************************************************************************
524 *****************************************************************************/
526 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
528 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
529 struct nv50_disp *disp = nv50_disp(encoder->dev);
531 struct nv50_disp_mthd_v1 base;
532 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
535 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
536 .base.hasht = nv_encoder->dcb->hasht,
537 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
538 (0x0100 << nv_crtc->index),
541 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
545 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
547 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
548 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
549 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
550 struct nv50_disp *disp = nv50_disp(encoder->dev);
552 struct nv50_disp_mthd_v1 base;
553 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
554 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
557 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
558 .base.hasht = nv_encoder->dcb->hasht,
559 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
560 (0x0100 << nv_crtc->index),
562 .pwr.rekey = 56, /* binary driver, and tegra, constant */
564 struct nouveau_connector *nv_connector;
565 struct drm_hdmi_info *hdmi;
567 union hdmi_infoframe avi_frame;
568 union hdmi_infoframe vendor_frame;
569 bool high_tmds_clock_ratio = false, scrambling = false;
574 nv_connector = nouveau_encoder_connector_get(nv_encoder);
575 if (!drm_detect_hdmi_monitor(nv_connector->edid))
578 hdmi = &nv_connector->base.display_info.hdmi;
580 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
581 &nv_connector->base, mode);
583 /* We have an AVI InfoFrame, populate it to the display */
584 args.pwr.avi_infoframe_length
585 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
588 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
589 &nv_connector->base, mode);
591 /* We have a Vendor InfoFrame, populate it to the display */
592 args.pwr.vendor_infoframe_length
593 = hdmi_infoframe_pack(&vendor_frame,
595 + args.pwr.avi_infoframe_length,
599 max_ac_packet = mode->htotal - mode->hdisplay;
600 max_ac_packet -= args.pwr.rekey;
601 max_ac_packet -= 18; /* constant from tegra */
602 args.pwr.max_ac_packet = max_ac_packet / 32;
604 if (hdmi->scdc.scrambling.supported) {
605 high_tmds_clock_ratio = mode->clock > 340000;
606 scrambling = high_tmds_clock_ratio ||
607 hdmi->scdc.scrambling.low_rates;
611 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
612 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
614 size = sizeof(args.base)
616 + args.pwr.avi_infoframe_length
617 + args.pwr.vendor_infoframe_length;
618 nvif_mthd(&disp->disp->object, 0, &args, size);
620 nv50_audio_enable(encoder, mode);
622 /* If SCDC is supported by the downstream monitor, update
623 * divider / scrambling settings to what we programmed above.
625 if (!hdmi->scdc.scrambling.supported)
628 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
630 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
633 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
634 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
635 config |= SCDC_SCRAMBLING_ENABLE * scrambling;
636 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
638 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
642 /******************************************************************************
644 *****************************************************************************/
645 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
646 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
647 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
650 struct nouveau_encoder *outp;
652 struct drm_dp_mst_topology_mgr mgr;
653 struct nv50_msto *msto[4];
661 struct nv50_mstm *mstm;
662 struct drm_dp_mst_port *port;
663 struct drm_connector connector;
665 struct drm_display_mode *native;
670 struct drm_encoder encoder;
672 struct nv50_head *head;
673 struct nv50_mstc *mstc;
677 static struct drm_dp_payload *
678 nv50_msto_payload(struct nv50_msto *msto)
680 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
681 struct nv50_mstc *mstc = msto->mstc;
682 struct nv50_mstm *mstm = mstc->mstm;
683 int vcpi = mstc->port->vcpi.vcpi, i;
685 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
687 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
688 for (i = 0; i < mstm->mgr.max_payloads; i++) {
689 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
690 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
691 mstm->outp->base.base.name, i, payload->vcpi,
692 payload->start_slot, payload->num_slots);
695 for (i = 0; i < mstm->mgr.max_payloads; i++) {
696 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
697 if (payload->vcpi == vcpi)
705 nv50_msto_cleanup(struct nv50_msto *msto)
707 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
708 struct nv50_mstc *mstc = msto->mstc;
709 struct nv50_mstm *mstm = mstc->mstm;
714 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
716 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
720 msto->disabled = false;
724 nv50_msto_prepare(struct nv50_msto *msto)
726 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
727 struct nv50_mstc *mstc = msto->mstc;
728 struct nv50_mstm *mstm = mstc->mstm;
730 struct nv50_disp_mthd_v1 base;
731 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
734 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
735 .base.hasht = mstm->outp->dcb->hasht,
736 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
737 (0x0100 << msto->head->base.index),
740 mutex_lock(&mstm->mgr.payload_lock);
742 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
743 if (mstc->port->vcpi.vcpi > 0) {
744 struct drm_dp_payload *payload = nv50_msto_payload(msto);
746 args.vcpi.start_slot = payload->start_slot;
747 args.vcpi.num_slots = payload->num_slots;
748 args.vcpi.pbn = mstc->port->vcpi.pbn;
749 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
753 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
754 msto->encoder.name, msto->head->base.base.name,
755 args.vcpi.start_slot, args.vcpi.num_slots,
756 args.vcpi.pbn, args.vcpi.aligned_pbn);
758 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
759 mutex_unlock(&mstm->mgr.payload_lock);
763 nv50_msto_atomic_check(struct drm_encoder *encoder,
764 struct drm_crtc_state *crtc_state,
765 struct drm_connector_state *conn_state)
767 struct drm_atomic_state *state = crtc_state->state;
768 struct drm_connector *connector = conn_state->connector;
769 struct nv50_mstc *mstc = nv50_mstc(connector);
770 struct nv50_mstm *mstm = mstc->mstm;
771 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
774 if (crtc_state->mode_changed || crtc_state->connectors_changed) {
776 * When restoring duplicated states, we need to make sure that
777 * the bw remains the same and avoid recalculating it, as the
778 * connector's bpc may have changed after the state was
781 if (!state->duplicated) {
782 const int bpp = connector->display_info.bpc * 3;
783 const int clock = crtc_state->adjusted_mode.clock;
785 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp);
788 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
797 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
802 nv50_msto_enable(struct drm_encoder *encoder)
804 struct nv50_head *head = nv50_head(encoder->crtc);
805 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
806 struct nv50_msto *msto = nv50_msto(encoder);
807 struct nv50_mstc *mstc = NULL;
808 struct nv50_mstm *mstm = NULL;
809 struct drm_connector *connector;
810 struct drm_connector_list_iter conn_iter;
814 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
815 drm_for_each_connector_iter(connector, &conn_iter) {
816 if (connector->state->best_encoder == &msto->encoder) {
817 mstc = nv50_mstc(connector);
822 drm_connector_list_iter_end(&conn_iter);
827 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
830 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
833 nv50_outp_acquire(mstm->outp);
835 if (mstm->outp->link & 1)
840 switch (mstc->connector.display_info.bpc) {
841 case 6: depth = 0x2; break;
842 case 8: depth = 0x5; break;
844 default: depth = 0x6; break;
847 mstm->outp->update(mstm->outp, head->base.index, armh, proto, depth);
851 mstm->modified = true;
855 nv50_msto_disable(struct drm_encoder *encoder)
857 struct nv50_msto *msto = nv50_msto(encoder);
858 struct nv50_mstc *mstc = msto->mstc;
859 struct nv50_mstm *mstm = mstc->mstm;
861 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
863 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
864 mstm->modified = true;
866 mstm->disabled = true;
867 msto->disabled = true;
870 static const struct drm_encoder_helper_funcs
872 .disable = nv50_msto_disable,
873 .enable = nv50_msto_enable,
874 .atomic_check = nv50_msto_atomic_check,
878 nv50_msto_destroy(struct drm_encoder *encoder)
880 struct nv50_msto *msto = nv50_msto(encoder);
881 drm_encoder_cleanup(&msto->encoder);
885 static const struct drm_encoder_funcs
887 .destroy = nv50_msto_destroy,
891 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
892 struct nv50_msto **pmsto)
894 struct nv50_msto *msto;
897 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
900 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
901 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
908 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
909 msto->encoder.possible_crtcs = heads;
913 static struct drm_encoder *
914 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
915 struct drm_connector_state *connector_state)
917 struct nv50_head *head = nv50_head(connector_state->crtc);
918 struct nv50_mstc *mstc = nv50_mstc(connector);
920 return &mstc->mstm->msto[head->base.index]->encoder;
923 static struct drm_encoder *
924 nv50_mstc_best_encoder(struct drm_connector *connector)
926 struct nv50_mstc *mstc = nv50_mstc(connector);
928 return &mstc->mstm->msto[0]->encoder;
931 static enum drm_mode_status
932 nv50_mstc_mode_valid(struct drm_connector *connector,
933 struct drm_display_mode *mode)
939 nv50_mstc_get_modes(struct drm_connector *connector)
941 struct nv50_mstc *mstc = nv50_mstc(connector);
944 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
945 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
947 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
949 if (!mstc->connector.display_info.bpc)
950 mstc->connector.display_info.bpc = 8;
953 drm_mode_destroy(mstc->connector.dev, mstc->native);
954 mstc->native = nouveau_conn_native_mode(&mstc->connector);
959 nv50_mstc_atomic_check(struct drm_connector *connector,
960 struct drm_atomic_state *state)
962 struct nv50_mstc *mstc = nv50_mstc(connector);
963 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
964 struct drm_connector_state *new_conn_state =
965 drm_atomic_get_new_connector_state(state, connector);
966 struct drm_connector_state *old_conn_state =
967 drm_atomic_get_old_connector_state(state, connector);
968 struct drm_crtc_state *crtc_state;
969 struct drm_crtc *new_crtc = new_conn_state->crtc;
971 if (!old_conn_state->crtc)
974 /* We only want to free VCPI if this state disables the CRTC on this
978 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
981 !drm_atomic_crtc_needs_modeset(crtc_state) ||
986 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
990 nv50_mstc_detect(struct drm_connector *connector,
991 struct drm_modeset_acquire_ctx *ctx, bool force)
993 struct nv50_mstc *mstc = nv50_mstc(connector);
996 if (drm_connector_is_unregistered(connector))
997 return connector_status_disconnected;
999 ret = pm_runtime_get_sync(connector->dev->dev);
1000 if (ret < 0 && ret != -EACCES)
1001 return connector_status_disconnected;
1003 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1006 pm_runtime_mark_last_busy(connector->dev->dev);
1007 pm_runtime_put_autosuspend(connector->dev->dev);
1011 static const struct drm_connector_helper_funcs
1013 .get_modes = nv50_mstc_get_modes,
1014 .mode_valid = nv50_mstc_mode_valid,
1015 .best_encoder = nv50_mstc_best_encoder,
1016 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1017 .atomic_check = nv50_mstc_atomic_check,
1018 .detect_ctx = nv50_mstc_detect,
1022 nv50_mstc_destroy(struct drm_connector *connector)
1024 struct nv50_mstc *mstc = nv50_mstc(connector);
1026 drm_connector_cleanup(&mstc->connector);
1027 drm_dp_mst_put_port_malloc(mstc->port);
1032 static const struct drm_connector_funcs
1034 .reset = nouveau_conn_reset,
1035 .fill_modes = drm_helper_probe_single_connector_modes,
1036 .destroy = nv50_mstc_destroy,
1037 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1038 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1039 .atomic_set_property = nouveau_conn_atomic_set_property,
1040 .atomic_get_property = nouveau_conn_atomic_get_property,
1044 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1045 const char *path, struct nv50_mstc **pmstc)
1047 struct drm_device *dev = mstm->outp->base.base.dev;
1048 struct nv50_mstc *mstc;
1051 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1056 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1057 DRM_MODE_CONNECTOR_DisplayPort);
1064 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1066 mstc->connector.funcs->reset(&mstc->connector);
1067 nouveau_conn_attach_properties(&mstc->connector);
1069 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
1070 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1072 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1073 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1074 drm_connector_set_path_property(&mstc->connector, path);
1075 drm_dp_mst_get_port_malloc(port);
1080 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1082 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1083 struct drm_encoder *encoder;
1086 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1087 ret = drm_dp_check_act_status(&mstm->mgr);
1089 ret = drm_dp_update_payload_part2(&mstm->mgr);
1091 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1092 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1093 struct nv50_msto *msto = nv50_msto(encoder);
1094 struct nv50_mstc *mstc = msto->mstc;
1095 if (mstc && mstc->mstm == mstm)
1096 nv50_msto_cleanup(msto);
1100 mstm->modified = false;
1104 nv50_mstm_prepare(struct nv50_mstm *mstm)
1106 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1107 struct drm_encoder *encoder;
1110 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1111 ret = drm_dp_update_payload_part1(&mstm->mgr);
1113 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1114 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1115 struct nv50_msto *msto = nv50_msto(encoder);
1116 struct nv50_mstc *mstc = msto->mstc;
1117 if (mstc && mstc->mstm == mstm)
1118 nv50_msto_prepare(msto);
1122 if (mstm->disabled) {
1124 nv50_outp_release(mstm->outp);
1125 mstm->disabled = false;
1130 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1131 struct drm_connector *connector)
1133 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1134 struct nv50_mstc *mstc = nv50_mstc(connector);
1136 drm_connector_unregister(&mstc->connector);
1138 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1140 drm_connector_put(&mstc->connector);
1144 nv50_mstm_register_connector(struct drm_connector *connector)
1146 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1148 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1150 drm_connector_register(connector);
1153 static struct drm_connector *
1154 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1155 struct drm_dp_mst_port *port, const char *path)
1157 struct nv50_mstm *mstm = nv50_mstm(mgr);
1158 struct nv50_mstc *mstc;
1161 ret = nv50_mstc_new(mstm, port, path, &mstc);
1165 return &mstc->connector;
1168 static const struct drm_dp_mst_topology_cbs
1170 .add_connector = nv50_mstm_add_connector,
1171 .register_connector = nv50_mstm_register_connector,
1172 .destroy_connector = nv50_mstm_destroy_connector,
1176 nv50_mstm_service(struct nv50_mstm *mstm)
1178 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1179 bool handled = true;
1187 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1189 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1193 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1197 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1202 nv50_mstm_remove(struct nv50_mstm *mstm)
1205 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1209 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1211 struct nouveau_encoder *outp = mstm->outp;
1213 struct nv50_disp_mthd_v1 base;
1214 struct nv50_disp_sor_dp_mst_link_v0 mst;
1217 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1218 .base.hasht = outp->dcb->hasht,
1219 .base.hashm = outp->dcb->hashm,
1222 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1223 struct nvif_object *disp = &drm->display->disp.object;
1227 /* Even if we're enabling MST, start with disabling the
1228 * branching unit to clear any sink-side MST topology state
1229 * that wasn't set by us
1231 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1236 /* Now, start initializing */
1237 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1244 return nvif_mthd(disp, 0, &args, sizeof(args));
1248 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1250 struct drm_dp_aux *aux;
1252 bool old_state, new_state;
1258 mutex_lock(&mstm->mgr.lock);
1260 old_state = mstm->mgr.mst_state;
1261 new_state = old_state;
1262 aux = mstm->mgr.aux;
1265 /* Just check that the MST hub is still as we expect it */
1266 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1267 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1268 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1271 } else if (dpcd[0] >= 0x12) {
1272 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1276 if (!(dpcd[1] & DP_MST_CAP))
1282 if (new_state == old_state) {
1283 mutex_unlock(&mstm->mgr.lock);
1287 ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1291 mutex_unlock(&mstm->mgr.lock);
1293 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1295 return nv50_mstm_enable(mstm, dpcd[0], 0);
1300 mutex_unlock(&mstm->mgr.lock);
1305 nv50_mstm_fini(struct nv50_mstm *mstm)
1307 if (mstm && mstm->mgr.mst_state)
1308 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1312 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1316 if (!mstm || !mstm->mgr.mst_state)
1319 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1321 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1322 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1327 nv50_mstm_del(struct nv50_mstm **pmstm)
1329 struct nv50_mstm *mstm = *pmstm;
1331 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1338 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1339 int conn_base_id, struct nv50_mstm **pmstm)
1341 const int max_payloads = hweight8(outp->dcb->heads);
1342 struct drm_device *dev = outp->base.base.dev;
1343 struct nv50_mstm *mstm;
1347 /* This is a workaround for some monitors not functioning
1348 * correctly in MST mode on initial module load. I think
1349 * some bad interaction with the VBIOS may be responsible.
1351 * A good ol' off and on again seems to work here ;)
1353 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1354 if (ret >= 0 && dpcd >= 0x12)
1355 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1357 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1360 mstm->mgr.cbs = &nv50_mstm;
1362 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1363 max_payloads, conn_base_id);
1367 for (i = 0; i < max_payloads; i++) {
1368 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1377 /******************************************************************************
1379 *****************************************************************************/
1381 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1382 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1384 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1385 struct nv50_core *core = disp->core;
1388 nv_encoder->ctrl &= ~BIT(head);
1389 if (!(nv_encoder->ctrl & 0x0000000f))
1390 nv_encoder->ctrl = 0;
1392 nv_encoder->ctrl |= proto << 8;
1393 nv_encoder->ctrl |= BIT(head);
1394 asyh->or.depth = depth;
1397 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1401 nv50_sor_disable(struct drm_encoder *encoder)
1403 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1404 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1406 nv_encoder->crtc = NULL;
1409 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1413 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1415 pwr &= ~DP_SET_POWER_MASK;
1416 pwr |= DP_SET_POWER_D3;
1417 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1421 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1422 nv50_audio_disable(encoder, nv_crtc);
1423 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1424 nv50_outp_release(nv_encoder);
1429 nv50_sor_enable(struct drm_encoder *encoder)
1431 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1432 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1433 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1434 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1436 struct nv50_disp_mthd_v1 base;
1437 struct nv50_disp_sor_lvds_script_v0 lvds;
1440 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1441 .base.hasht = nv_encoder->dcb->hasht,
1442 .base.hashm = nv_encoder->dcb->hashm,
1444 struct nv50_disp *disp = nv50_disp(encoder->dev);
1445 struct drm_device *dev = encoder->dev;
1446 struct nouveau_drm *drm = nouveau_drm(dev);
1447 struct nouveau_connector *nv_connector;
1448 struct nvbios *bios = &drm->vbios;
1452 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1453 nv_encoder->crtc = encoder->crtc;
1454 nv50_outp_acquire(nv_encoder);
1456 switch (nv_encoder->dcb->type) {
1457 case DCB_OUTPUT_TMDS:
1458 if (nv_encoder->link & 1) {
1460 /* Only enable dual-link if:
1461 * - Need to (i.e. rate > 165MHz)
1463 * - Not an HDMI monitor, since there's no dual-link
1466 if (mode->clock >= 165000 &&
1467 nv_encoder->dcb->duallink_possible &&
1468 !drm_detect_hdmi_monitor(nv_connector->edid))
1474 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1476 case DCB_OUTPUT_LVDS:
1479 if (bios->fp_no_ddc) {
1480 if (bios->fp.dual_link)
1481 lvds.lvds.script |= 0x0100;
1482 if (bios->fp.if_is_24bit)
1483 lvds.lvds.script |= 0x0200;
1485 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1486 if (((u8 *)nv_connector->edid)[121] == 2)
1487 lvds.lvds.script |= 0x0100;
1489 if (mode->clock >= bios->fp.duallink_transition_clk) {
1490 lvds.lvds.script |= 0x0100;
1493 if (lvds.lvds.script & 0x0100) {
1494 if (bios->fp.strapless_is_24bit & 2)
1495 lvds.lvds.script |= 0x0200;
1497 if (bios->fp.strapless_is_24bit & 1)
1498 lvds.lvds.script |= 0x0200;
1501 if (nv_connector->base.display_info.bpc == 8)
1502 lvds.lvds.script |= 0x0200;
1505 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1508 if (nv_connector->base.display_info.bpc == 6)
1511 if (nv_connector->base.display_info.bpc == 8)
1516 if (nv_encoder->link & 1)
1521 nv50_audio_enable(encoder, mode);
1528 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1531 static const struct drm_encoder_helper_funcs
1533 .atomic_check = nv50_outp_atomic_check,
1534 .enable = nv50_sor_enable,
1535 .disable = nv50_sor_disable,
1539 nv50_sor_destroy(struct drm_encoder *encoder)
1541 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1542 nv50_mstm_del(&nv_encoder->dp.mstm);
1543 drm_encoder_cleanup(encoder);
1547 static const struct drm_encoder_funcs
1549 .destroy = nv50_sor_destroy,
1553 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1555 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1556 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1557 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1558 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1559 struct nouveau_encoder *nv_encoder;
1560 struct drm_encoder *encoder;
1561 u8 ver, hdr, cnt, len;
1565 switch (dcbe->type) {
1566 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1567 case DCB_OUTPUT_TMDS:
1570 type = DRM_MODE_ENCODER_TMDS;
1574 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1577 nv_encoder->dcb = dcbe;
1578 nv_encoder->update = nv50_sor_update;
1580 encoder = to_drm_encoder(nv_encoder);
1581 encoder->possible_crtcs = dcbe->heads;
1582 encoder->possible_clones = 0;
1583 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1584 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1585 drm_encoder_helper_add(encoder, &nv50_sor_help);
1587 drm_connector_attach_encoder(connector, encoder);
1589 if (dcbe->type == DCB_OUTPUT_DP) {
1590 struct nv50_disp *disp = nv50_disp(encoder->dev);
1591 struct nvkm_i2c_aux *aux =
1592 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1594 if (disp->disp->object.oclass < GF110_DISP) {
1595 /* HW has no support for address-only
1596 * transactions, so we're required to
1597 * use custom I2C-over-AUX code.
1599 nv_encoder->i2c = &aux->i2c;
1601 nv_encoder->i2c = &nv_connector->aux.ddc;
1603 nv_encoder->aux = aux;
1606 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1607 (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1608 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1609 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1610 nv_connector->base.base.id,
1611 &nv_encoder->dp.mstm);
1616 struct nvkm_i2c_bus *bus =
1617 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1619 nv_encoder->i2c = &bus->i2c;
1625 /******************************************************************************
1627 *****************************************************************************/
1629 nv50_pior_atomic_check(struct drm_encoder *encoder,
1630 struct drm_crtc_state *crtc_state,
1631 struct drm_connector_state *conn_state)
1633 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1636 crtc_state->adjusted_mode.clock *= 2;
1641 nv50_pior_disable(struct drm_encoder *encoder)
1643 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1644 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1645 if (nv_encoder->crtc)
1646 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1647 nv_encoder->crtc = NULL;
1648 nv50_outp_release(nv_encoder);
1652 nv50_pior_enable(struct drm_encoder *encoder)
1654 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1655 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1656 struct nouveau_connector *nv_connector;
1657 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1658 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1659 u8 owner = 1 << nv_crtc->index;
1662 nv50_outp_acquire(nv_encoder);
1664 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1665 switch (nv_connector->base.display_info.bpc) {
1666 case 10: asyh->or.depth = 0x6; break;
1667 case 8: asyh->or.depth = 0x5; break;
1668 case 6: asyh->or.depth = 0x2; break;
1669 default: asyh->or.depth = 0x0; break;
1672 switch (nv_encoder->dcb->type) {
1673 case DCB_OUTPUT_TMDS:
1682 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1683 nv_encoder->crtc = encoder->crtc;
1686 static const struct drm_encoder_helper_funcs
1688 .atomic_check = nv50_pior_atomic_check,
1689 .enable = nv50_pior_enable,
1690 .disable = nv50_pior_disable,
1694 nv50_pior_destroy(struct drm_encoder *encoder)
1696 drm_encoder_cleanup(encoder);
1700 static const struct drm_encoder_funcs
1702 .destroy = nv50_pior_destroy,
1706 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1708 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1709 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1710 struct nvkm_i2c_bus *bus = NULL;
1711 struct nvkm_i2c_aux *aux = NULL;
1712 struct i2c_adapter *ddc;
1713 struct nouveau_encoder *nv_encoder;
1714 struct drm_encoder *encoder;
1717 switch (dcbe->type) {
1718 case DCB_OUTPUT_TMDS:
1719 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1720 ddc = bus ? &bus->i2c : NULL;
1721 type = DRM_MODE_ENCODER_TMDS;
1724 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1725 ddc = aux ? &aux->i2c : NULL;
1726 type = DRM_MODE_ENCODER_TMDS;
1732 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1735 nv_encoder->dcb = dcbe;
1736 nv_encoder->i2c = ddc;
1737 nv_encoder->aux = aux;
1739 encoder = to_drm_encoder(nv_encoder);
1740 encoder->possible_crtcs = dcbe->heads;
1741 encoder->possible_clones = 0;
1742 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1743 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1744 drm_encoder_helper_add(encoder, &nv50_pior_help);
1746 drm_connector_attach_encoder(connector, encoder);
1750 /******************************************************************************
1752 *****************************************************************************/
1755 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1757 struct nouveau_drm *drm = nouveau_drm(state->dev);
1758 struct nv50_disp *disp = nv50_disp(drm->dev);
1759 struct nv50_core *core = disp->core;
1760 struct nv50_mstm *mstm;
1761 struct drm_encoder *encoder;
1763 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1765 drm_for_each_encoder(encoder, drm->dev) {
1766 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1767 mstm = nouveau_encoder(encoder)->dp.mstm;
1768 if (mstm && mstm->modified)
1769 nv50_mstm_prepare(mstm);
1773 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1774 core->func->update(core, interlock, true);
1775 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1776 disp->core->chan.base.device))
1777 NV_ERROR(drm, "core notifier timeout\n");
1779 drm_for_each_encoder(encoder, drm->dev) {
1780 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1781 mstm = nouveau_encoder(encoder)->dp.mstm;
1782 if (mstm && mstm->modified)
1783 nv50_mstm_cleanup(mstm);
1789 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1791 struct drm_plane_state *new_plane_state;
1792 struct drm_plane *plane;
1795 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1796 struct nv50_wndw *wndw = nv50_wndw(plane);
1797 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1798 if (wndw->func->update)
1799 wndw->func->update(wndw, interlock);
1805 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1807 struct drm_device *dev = state->dev;
1808 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1809 struct drm_crtc *crtc;
1810 struct drm_plane_state *new_plane_state;
1811 struct drm_plane *plane;
1812 struct nouveau_drm *drm = nouveau_drm(dev);
1813 struct nv50_disp *disp = nv50_disp(dev);
1814 struct nv50_atom *atom = nv50_atom(state);
1815 struct nv50_outp_atom *outp, *outt;
1816 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1819 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1820 drm_atomic_helper_wait_for_fences(dev, state, false);
1821 drm_atomic_helper_wait_for_dependencies(state);
1822 drm_atomic_helper_update_legacy_modeset_state(dev, state);
1824 if (atom->lock_core)
1825 mutex_lock(&disp->mutex);
1827 /* Disable head(s). */
1828 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1829 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1830 struct nv50_head *head = nv50_head(crtc);
1832 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1833 asyh->clr.mask, asyh->set.mask);
1835 if (old_crtc_state->active && !new_crtc_state->active) {
1836 pm_runtime_put_noidle(dev->dev);
1837 drm_crtc_vblank_off(crtc);
1840 if (asyh->clr.mask) {
1841 nv50_head_flush_clr(head, asyh, atom->flush_disable);
1842 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1846 /* Disable plane(s). */
1847 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1848 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1849 struct nv50_wndw *wndw = nv50_wndw(plane);
1851 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1852 asyw->clr.mask, asyw->set.mask);
1853 if (!asyw->clr.mask)
1856 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1859 /* Disable output path(s). */
1860 list_for_each_entry(outp, &atom->outp, head) {
1861 const struct drm_encoder_helper_funcs *help;
1862 struct drm_encoder *encoder;
1864 encoder = outp->encoder;
1865 help = encoder->helper_private;
1867 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1868 outp->clr.mask, outp->set.mask);
1870 if (outp->clr.mask) {
1871 help->disable(encoder);
1872 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1873 if (outp->flush_disable) {
1874 nv50_disp_atomic_commit_wndw(state, interlock);
1875 nv50_disp_atomic_commit_core(state, interlock);
1876 memset(interlock, 0x00, sizeof(interlock));
1881 /* Flush disable. */
1882 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1883 if (atom->flush_disable) {
1884 nv50_disp_atomic_commit_wndw(state, interlock);
1885 nv50_disp_atomic_commit_core(state, interlock);
1886 memset(interlock, 0x00, sizeof(interlock));
1890 /* Update output path(s). */
1891 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1892 const struct drm_encoder_helper_funcs *help;
1893 struct drm_encoder *encoder;
1895 encoder = outp->encoder;
1896 help = encoder->helper_private;
1898 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1899 outp->set.mask, outp->clr.mask);
1901 if (outp->set.mask) {
1902 help->enable(encoder);
1903 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1906 list_del(&outp->head);
1910 /* Update head(s). */
1911 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1912 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1913 struct nv50_head *head = nv50_head(crtc);
1915 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1916 asyh->set.mask, asyh->clr.mask);
1918 if (asyh->set.mask) {
1919 nv50_head_flush_set(head, asyh);
1920 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1923 if (new_crtc_state->active) {
1924 if (!old_crtc_state->active) {
1925 drm_crtc_vblank_on(crtc);
1926 pm_runtime_get_noresume(dev->dev);
1928 if (new_crtc_state->event)
1929 drm_crtc_vblank_get(crtc);
1933 /* Update plane(s). */
1934 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1935 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1936 struct nv50_wndw *wndw = nv50_wndw(plane);
1938 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1939 asyw->set.mask, asyw->clr.mask);
1940 if ( !asyw->set.mask &&
1941 (!asyw->clr.mask || atom->flush_disable))
1944 nv50_wndw_flush_set(wndw, interlock, asyw);
1948 nv50_disp_atomic_commit_wndw(state, interlock);
1950 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1951 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1952 interlock[NV50_DISP_INTERLOCK_OVLY] ||
1953 interlock[NV50_DISP_INTERLOCK_WNDW] ||
1954 !atom->state.legacy_cursor_update)
1955 nv50_disp_atomic_commit_core(state, interlock);
1957 disp->core->func->update(disp->core, interlock, false);
1960 if (atom->lock_core)
1961 mutex_unlock(&disp->mutex);
1963 /* Wait for HW to signal completion. */
1964 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1965 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1966 struct nv50_wndw *wndw = nv50_wndw(plane);
1967 int ret = nv50_wndw_wait_armed(wndw, asyw);
1969 NV_ERROR(drm, "%s: timeout\n", plane->name);
1972 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1973 if (new_crtc_state->event) {
1974 unsigned long flags;
1975 /* Get correct count/ts if racing with vblank irq */
1976 if (new_crtc_state->active)
1977 drm_crtc_accurate_vblank_count(crtc);
1978 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1979 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1980 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1982 new_crtc_state->event = NULL;
1983 if (new_crtc_state->active)
1984 drm_crtc_vblank_put(crtc);
1988 drm_atomic_helper_commit_hw_done(state);
1989 drm_atomic_helper_cleanup_planes(dev, state);
1990 drm_atomic_helper_commit_cleanup_done(state);
1991 drm_atomic_state_put(state);
1993 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
1994 pm_runtime_mark_last_busy(dev->dev);
1995 pm_runtime_put_autosuspend(dev->dev);
1999 nv50_disp_atomic_commit_work(struct work_struct *work)
2001 struct drm_atomic_state *state =
2002 container_of(work, typeof(*state), commit_work);
2003 nv50_disp_atomic_commit_tail(state);
2007 nv50_disp_atomic_commit(struct drm_device *dev,
2008 struct drm_atomic_state *state, bool nonblock)
2010 struct drm_plane_state *new_plane_state;
2011 struct drm_plane *plane;
2014 ret = pm_runtime_get_sync(dev->dev);
2015 if (ret < 0 && ret != -EACCES)
2018 ret = drm_atomic_helper_setup_commit(state, nonblock);
2022 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2024 ret = drm_atomic_helper_prepare_planes(dev, state);
2029 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2034 ret = drm_atomic_helper_swap_state(state, true);
2038 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2039 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2040 struct nv50_wndw *wndw = nv50_wndw(plane);
2042 if (asyw->set.image)
2043 nv50_wndw_ntfy_enable(wndw, asyw);
2046 drm_atomic_state_get(state);
2049 * Grab another RPM ref for the commit tail, which will release the
2050 * ref when it's finished
2052 pm_runtime_get_noresume(dev->dev);
2055 queue_work(system_unbound_wq, &state->commit_work);
2057 nv50_disp_atomic_commit_tail(state);
2061 drm_atomic_helper_cleanup_planes(dev, state);
2063 pm_runtime_put_autosuspend(dev->dev);
2067 static struct nv50_outp_atom *
2068 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2070 struct nv50_outp_atom *outp;
2072 list_for_each_entry(outp, &atom->outp, head) {
2073 if (outp->encoder == encoder)
2077 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2079 return ERR_PTR(-ENOMEM);
2081 list_add(&outp->head, &atom->outp);
2082 outp->encoder = encoder;
2087 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2088 struct drm_connector_state *old_connector_state)
2090 struct drm_encoder *encoder = old_connector_state->best_encoder;
2091 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2092 struct drm_crtc *crtc;
2093 struct nv50_outp_atom *outp;
2095 if (!(crtc = old_connector_state->crtc))
2098 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2099 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2100 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2101 outp = nv50_disp_outp_atomic_add(atom, encoder);
2103 return PTR_ERR(outp);
2105 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2106 outp->flush_disable = true;
2107 atom->flush_disable = true;
2109 outp->clr.ctrl = true;
2110 atom->lock_core = true;
2117 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2118 struct drm_connector_state *connector_state)
2120 struct drm_encoder *encoder = connector_state->best_encoder;
2121 struct drm_crtc_state *new_crtc_state;
2122 struct drm_crtc *crtc;
2123 struct nv50_outp_atom *outp;
2125 if (!(crtc = connector_state->crtc))
2128 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2129 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2130 outp = nv50_disp_outp_atomic_add(atom, encoder);
2132 return PTR_ERR(outp);
2134 outp->set.ctrl = true;
2135 atom->lock_core = true;
2142 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2144 struct nv50_atom *atom = nv50_atom(state);
2145 struct drm_connector_state *old_connector_state, *new_connector_state;
2146 struct drm_connector *connector;
2147 struct drm_crtc_state *new_crtc_state;
2148 struct drm_crtc *crtc;
2151 /* We need to handle colour management on a per-plane basis. */
2152 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2153 if (new_crtc_state->color_mgmt_changed) {
2154 ret = drm_atomic_add_affected_planes(state, crtc);
2160 ret = drm_atomic_helper_check(dev, state);
2164 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2165 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2169 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2174 ret = drm_dp_mst_atomic_check(state);
2182 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2184 struct nv50_atom *atom = nv50_atom(state);
2185 struct nv50_outp_atom *outp, *outt;
2187 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2188 list_del(&outp->head);
2192 drm_atomic_state_default_clear(state);
2196 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2198 struct nv50_atom *atom = nv50_atom(state);
2199 drm_atomic_state_default_release(&atom->state);
2203 static struct drm_atomic_state *
2204 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2206 struct nv50_atom *atom;
2207 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2208 drm_atomic_state_init(dev, &atom->state) < 0) {
2212 INIT_LIST_HEAD(&atom->outp);
2213 return &atom->state;
2216 static const struct drm_mode_config_funcs
2218 .fb_create = nouveau_user_framebuffer_create,
2219 .output_poll_changed = nouveau_fbcon_output_poll_changed,
2220 .atomic_check = nv50_disp_atomic_check,
2221 .atomic_commit = nv50_disp_atomic_commit,
2222 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2223 .atomic_state_clear = nv50_disp_atomic_state_clear,
2224 .atomic_state_free = nv50_disp_atomic_state_free,
2227 /******************************************************************************
2229 *****************************************************************************/
2232 nv50_display_fini(struct drm_device *dev, bool suspend)
2234 struct nouveau_encoder *nv_encoder;
2235 struct drm_encoder *encoder;
2236 struct drm_plane *plane;
2238 drm_for_each_plane(plane, dev) {
2239 struct nv50_wndw *wndw = nv50_wndw(plane);
2240 if (plane->funcs != &nv50_wndw)
2242 nv50_wndw_fini(wndw);
2245 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2246 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2247 nv_encoder = nouveau_encoder(encoder);
2248 nv50_mstm_fini(nv_encoder->dp.mstm);
2254 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2256 struct nv50_core *core = nv50_disp(dev)->core;
2257 struct drm_encoder *encoder;
2258 struct drm_plane *plane;
2260 core->func->init(core);
2262 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2263 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2264 struct nouveau_encoder *nv_encoder =
2265 nouveau_encoder(encoder);
2266 nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2270 drm_for_each_plane(plane, dev) {
2271 struct nv50_wndw *wndw = nv50_wndw(plane);
2272 if (plane->funcs != &nv50_wndw)
2274 nv50_wndw_init(wndw);
2281 nv50_display_destroy(struct drm_device *dev)
2283 struct nv50_disp *disp = nv50_disp(dev);
2285 nv50_core_del(&disp->core);
2287 nouveau_bo_unmap(disp->sync);
2289 nouveau_bo_unpin(disp->sync);
2290 nouveau_bo_ref(NULL, &disp->sync);
2292 nouveau_display(dev)->priv = NULL;
2297 nv50_display_create(struct drm_device *dev)
2299 struct nvif_device *device = &nouveau_drm(dev)->client.device;
2300 struct nouveau_drm *drm = nouveau_drm(dev);
2301 struct dcb_table *dcb = &drm->vbios.dcb;
2302 struct drm_connector *connector, *tmp;
2303 struct nv50_disp *disp;
2304 struct dcb_output *dcbe;
2307 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2311 mutex_init(&disp->mutex);
2313 nouveau_display(dev)->priv = disp;
2314 nouveau_display(dev)->dtor = nv50_display_destroy;
2315 nouveau_display(dev)->init = nv50_display_init;
2316 nouveau_display(dev)->fini = nv50_display_fini;
2317 disp->disp = &nouveau_display(dev)->disp;
2318 dev->mode_config.funcs = &nv50_disp_func;
2319 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2320 dev->mode_config.normalize_zpos = true;
2322 /* small shared memory area we use for notifiers and semaphores */
2323 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2324 0, 0x0000, NULL, NULL, &disp->sync);
2326 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2328 ret = nouveau_bo_map(disp->sync);
2330 nouveau_bo_unpin(disp->sync);
2333 nouveau_bo_ref(NULL, &disp->sync);
2339 /* allocate master evo channel */
2340 ret = nv50_core_new(drm, &disp->core);
2344 /* create crtc objects to represent the hw heads */
2345 if (disp->disp->object.oclass >= GV100_DISP)
2346 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2348 if (disp->disp->object.oclass >= GF110_DISP)
2349 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2353 for (i = 0; i < fls(crtcs); i++) {
2354 if (!(crtcs & (1 << i)))
2356 ret = nv50_head_create(dev, i);
2361 /* create encoder/connector objects based on VBIOS DCB table */
2362 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2363 connector = nouveau_connector_create(dev, dcbe);
2364 if (IS_ERR(connector))
2367 if (dcbe->location == DCB_LOC_ON_CHIP) {
2368 switch (dcbe->type) {
2369 case DCB_OUTPUT_TMDS:
2370 case DCB_OUTPUT_LVDS:
2372 ret = nv50_sor_create(connector, dcbe);
2374 case DCB_OUTPUT_ANALOG:
2375 ret = nv50_dac_create(connector, dcbe);
2382 ret = nv50_pior_create(connector, dcbe);
2386 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2387 dcbe->location, dcbe->type,
2388 ffs(dcbe->or) - 1, ret);
2393 /* cull any connectors we created that don't have an encoder */
2394 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2395 if (connector->possible_encoders)
2398 NV_WARN(drm, "%s has no encoders, removing\n",
2400 connector->funcs->destroy(connector);
2403 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2404 dev->vblank_disable_immediate = true;
2408 nv50_display_destroy(dev);