2 * Copyright 2018 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <nvif/class.h>
26 #include <nvif/cl0002.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_fourcc.h>
31 #include "nouveau_bo.h"
34 nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma)
36 nvif_object_fini(&ctxdma->object);
37 list_del(&ctxdma->head);
41 static struct nv50_wndw_ctxdma *
42 nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct nouveau_framebuffer *fb)
44 struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
45 struct nv50_wndw_ctxdma *ctxdma;
46 const u8 kind = fb->nvbo->kind;
47 const u32 handle = 0xfb000000 | kind;
49 struct nv_dma_v0 base;
51 struct nv50_dma_v0 nv50;
52 struct gf100_dma_v0 gf100;
53 struct gf119_dma_v0 gf119;
56 u32 argc = sizeof(args.base);
59 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) {
60 if (ctxdma->object.handle == handle)
64 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
65 return ERR_PTR(-ENOMEM);
66 list_add(&ctxdma->head, &wndw->ctxdma.list);
68 args.base.target = NV_DMA_V0_TARGET_VRAM;
69 args.base.access = NV_DMA_V0_ACCESS_RDWR;
71 args.base.limit = drm->client.device.info.ram_user - 1;
73 if (drm->client.device.info.chipset < 0x80) {
74 args.nv50.part = NV50_DMA_V0_PART_256;
75 argc += sizeof(args.nv50);
77 if (drm->client.device.info.chipset < 0xc0) {
78 args.nv50.part = NV50_DMA_V0_PART_256;
79 args.nv50.kind = kind;
80 argc += sizeof(args.nv50);
82 if (drm->client.device.info.chipset < 0xd0) {
83 args.gf100.kind = kind;
84 argc += sizeof(args.gf100);
86 args.gf119.page = GF119_DMA_V0_PAGE_LP;
87 args.gf119.kind = kind;
88 argc += sizeof(args.gf119);
91 ret = nvif_object_init(wndw->ctxdma.parent, handle, NV_DMA_IN_MEMORY,
92 &args, argc, &ctxdma->object);
94 nv50_wndw_ctxdma_del(ctxdma);
102 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
104 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
105 if (asyw->set.ntfy) {
106 return wndw->func->ntfy_wait_begun(disp->sync,
108 wndw->wndw.base.device);
114 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush,
115 struct nv50_wndw_atom *asyw)
117 union nv50_wndw_atom_mask clr = {
118 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask),
120 if (clr.sema ) wndw->func-> sema_clr(wndw);
121 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw);
122 if (clr.xlut ) wndw->func-> xlut_clr(wndw);
123 if (clr.csc ) wndw->func-> csc_clr(wndw);
124 if (clr.image) wndw->func->image_clr(wndw);
126 interlock[wndw->interlock.type] |= wndw->interlock.data;
130 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock,
131 struct nv50_wndw_atom *asyw)
133 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
134 asyw->image.mode = 0;
135 asyw->image.interval = 1;
138 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
139 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
140 if (asyw->set.image) wndw->func->image_set(wndw, asyw);
142 if (asyw->set.xlut ) {
144 asyw->xlut.i.offset =
145 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer,
146 asyw->ilut, asyw->xlut.i.load);
148 wndw->func->xlut_set(wndw, asyw);
151 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw);
152 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw);
153 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw);
154 if (asyw->set.point) {
155 if (asyw->set.point = false, asyw->set.mask)
156 interlock[wndw->interlock.type] |= wndw->interlock.data;
157 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm;
159 wndw->immd->point(wndw, asyw);
160 wndw->immd->update(wndw, interlock);
162 interlock[wndw->interlock.type] |= wndw->interlock.data;
167 nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
169 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
171 asyw->ntfy.handle = wndw->wndw.sync.handle;
172 asyw->ntfy.offset = wndw->ntfy;
173 asyw->ntfy.awaken = false;
174 asyw->set.ntfy = true;
176 wndw->func->ntfy_reset(disp->sync, wndw->ntfy);
181 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
182 struct nv50_wndw_atom *asyw,
183 struct nv50_head_atom *asyh)
185 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
186 NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
187 wndw->func->release(wndw, asyw, asyh);
188 asyw->ntfy.handle = 0;
189 asyw->sema.handle = 0;
193 nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw)
195 switch (asyw->state.fb->format->format) {
196 case DRM_FORMAT_YUYV: asyw->image.format = 0x28; break;
197 case DRM_FORMAT_UYVY: asyw->image.format = 0x29; break;
202 asyw->image.colorspace = 1;
207 nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw)
209 switch (asyw->state.fb->format->format) {
210 case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break;
211 case DRM_FORMAT_XRGB8888 :
212 case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break;
213 case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break;
214 case DRM_FORMAT_XRGB1555 :
215 case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break;
216 case DRM_FORMAT_XBGR2101010 :
217 case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break;
218 case DRM_FORMAT_XBGR8888 :
219 case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break;
220 case DRM_FORMAT_XRGB2101010 :
221 case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break;
222 case DRM_FORMAT_XBGR16161616F:
223 case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break;
227 asyw->image.colorspace = 0;
232 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
233 struct nv50_wndw_atom *armw,
234 struct nv50_wndw_atom *asyw,
235 struct nv50_head_atom *asyh)
237 struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
238 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
241 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
243 if (asyw->state.fb != armw->state.fb || !armw->visible || modeset) {
244 asyw->image.w = fb->base.width;
245 asyw->image.h = fb->base.height;
246 asyw->image.kind = fb->nvbo->kind;
248 ret = nv50_wndw_atomic_check_acquire_rgb(asyw);
250 ret = nv50_wndw_atomic_check_acquire_yuv(asyw);
255 if (asyw->image.kind) {
256 asyw->image.layout = 0;
257 if (drm->client.device.info.chipset >= 0xc0)
258 asyw->image.blockh = fb->nvbo->mode >> 4;
260 asyw->image.blockh = fb->nvbo->mode;
261 asyw->image.blocks[0] = fb->base.pitches[0] / 64;
262 asyw->image.pitch[0] = 0;
264 asyw->image.layout = 1;
265 asyw->image.blockh = 0;
266 asyw->image.blocks[0] = 0;
267 asyw->image.pitch[0] = fb->base.pitches[0];
270 if (!(asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC))
271 asyw->image.interval = 1;
273 asyw->image.interval = 0;
274 asyw->image.mode = asyw->image.interval ? 0 : 1;
275 asyw->set.image = wndw->func->image_set != NULL;
278 if (wndw->func->scale_set) {
279 asyw->scale.sx = asyw->state.src_x >> 16;
280 asyw->scale.sy = asyw->state.src_y >> 16;
281 asyw->scale.sw = asyw->state.src_w >> 16;
282 asyw->scale.sh = asyw->state.src_h >> 16;
283 asyw->scale.dw = asyw->state.crtc_w;
284 asyw->scale.dh = asyw->state.crtc_h;
285 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale)))
286 asyw->set.scale = true;
289 if (wndw->func->blend_set) {
290 asyw->blend.depth = 255 - asyw->state.normalized_zpos;
291 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend)))
292 asyw->set.blend = true;
296 asyw->point.x = asyw->state.crtc_x;
297 asyw->point.y = asyw->state.crtc_y;
298 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
299 asyw->set.point = true;
302 return wndw->func->acquire(wndw, asyw, asyh);
306 nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw,
307 struct nv50_wndw_atom *armw,
308 struct nv50_wndw_atom *asyw,
309 struct nv50_head_atom *asyh)
311 struct drm_property_blob *ilut = asyh->state.degamma_lut;
313 /* I8 format without an input LUT makes no sense, and the
314 * HW error-checks for this.
316 * In order to handle legacy gamma, when there's no input
317 * LUT we need to steal the output LUT and use it instead.
319 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) {
320 /* This should be an error, but there's legacy clients
321 * that do a modeset before providing a gamma table.
323 * We keep the window disabled to avoid angering HW.
325 if (!(ilut = asyh->state.gamma_lut)) {
326 asyw->visible = false;
330 if (wndw->func->ilut)
331 asyh->wndw.olut |= BIT(wndw->id);
333 asyh->wndw.olut &= ~BIT(wndw->id);
336 if (!ilut && wndw->func->ilut_identity &&
337 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F &&
338 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) {
339 static struct drm_property_blob dummy = {};
343 /* Recalculate LUT state. */
344 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut));
345 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) {
346 wndw->func->ilut(wndw, asyw);
347 asyw->xlut.handle = wndw->wndw.vram.handle;
348 asyw->xlut.i.buffer = !asyw->xlut.i.buffer;
349 asyw->set.xlut = true;
351 asyw->clr.xlut = armw->xlut.handle != 0;
354 /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */
355 if (wndw->func->olut_core &&
356 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle)))
357 asyw->set.xlut = true;
359 if (wndw->func->csc && asyh->state.ctm) {
360 const struct drm_color_ctm *ctm = asyh->state.ctm->data;
361 wndw->func->csc(wndw, asyw, ctm);
362 asyw->csc.valid = true;
363 asyw->set.csc = true;
365 asyw->csc.valid = false;
366 asyw->clr.csc = armw->csc.valid;
369 /* Can't do an immediate flip while changing the LUT. */
370 asyh->state.pageflip_flags &= ~DRM_MODE_PAGE_FLIP_ASYNC;
374 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
376 struct nouveau_drm *drm = nouveau_drm(plane->dev);
377 struct nv50_wndw *wndw = nv50_wndw(plane);
378 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
379 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
380 struct nv50_head_atom *harm = NULL, *asyh = NULL;
381 bool modeset = false;
384 NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
386 /* Fetch the assembly state for the head the window will belong to,
387 * and determine whether the window will be visible.
389 if (asyw->state.crtc) {
390 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
392 return PTR_ERR(asyh);
393 modeset = drm_atomic_crtc_needs_modeset(&asyh->state);
394 asyw->visible = asyh->state.active;
396 asyw->visible = false;
399 /* Fetch assembly state for the head the window used to belong to. */
400 if (armw->state.crtc) {
401 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
403 return PTR_ERR(harm);
406 /* LUT configuration can potentially cause the window to be disabled. */
407 if (asyw->visible && wndw->func->xlut_set &&
409 asyh->state.color_mgmt_changed ||
410 asyw->state.fb->format->format !=
411 armw->state.fb->format->format))
412 nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh);
414 /* Calculate new window state. */
416 ret = nv50_wndw_atomic_check_acquire(wndw, modeset,
421 asyh->wndw.mask |= BIT(wndw->id);
424 nv50_wndw_atomic_check_release(wndw, asyw, harm);
425 harm->wndw.mask &= ~BIT(wndw->id);
430 /* Aside from the obvious case where the window is actively being
431 * disabled, we might also need to temporarily disable the window
432 * when performing certain modeset operations.
434 if (!asyw->visible || modeset) {
435 asyw->clr.ntfy = armw->ntfy.handle != 0;
436 asyw->clr.sema = armw->sema.handle != 0;
437 asyw->clr.xlut = armw->xlut.handle != 0;
438 asyw->clr.csc = armw->csc.valid;
439 if (wndw->func->image_clr)
440 asyw->clr.image = armw->image.handle[0] != 0;
447 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
449 struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
450 struct nouveau_drm *drm = nouveau_drm(plane->dev);
452 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
456 nouveau_bo_unpin(fb->nvbo);
460 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
462 struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
463 struct nouveau_drm *drm = nouveau_drm(plane->dev);
464 struct nv50_wndw *wndw = nv50_wndw(plane);
465 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
466 struct nv50_head_atom *asyh;
467 struct nv50_wndw_ctxdma *ctxdma;
470 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
474 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
478 if (wndw->ctxdma.parent) {
479 ctxdma = nv50_wndw_ctxdma_new(wndw, fb);
480 if (IS_ERR(ctxdma)) {
481 nouveau_bo_unpin(fb->nvbo);
482 return PTR_ERR(ctxdma);
485 asyw->image.handle[0] = ctxdma->object.handle;
488 asyw->state.fence = dma_resv_get_excl_rcu(fb->nvbo->bo.base.resv);
489 asyw->image.offset[0] = fb->nvbo->bo.offset;
491 if (wndw->func->prepare) {
492 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
494 return PTR_ERR(asyh);
496 wndw->func->prepare(wndw, asyh, asyw);
502 static const struct drm_plane_helper_funcs
504 .prepare_fb = nv50_wndw_prepare_fb,
505 .cleanup_fb = nv50_wndw_cleanup_fb,
506 .atomic_check = nv50_wndw_atomic_check,
510 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
511 struct drm_plane_state *state)
513 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
514 __drm_atomic_helper_plane_destroy_state(&asyw->state);
518 static struct drm_plane_state *
519 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
521 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
522 struct nv50_wndw_atom *asyw;
523 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
525 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
526 asyw->sema = armw->sema;
527 asyw->ntfy = armw->ntfy;
529 asyw->xlut = armw->xlut;
530 asyw->csc = armw->csc;
531 asyw->image = armw->image;
532 asyw->point = armw->point;
539 nv50_wndw_zpos_default(struct drm_plane *plane)
541 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 :
542 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255;
546 nv50_wndw_reset(struct drm_plane *plane)
548 struct nv50_wndw_atom *asyw;
550 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
554 plane->funcs->atomic_destroy_state(plane, plane->state);
556 __drm_atomic_helper_plane_reset(plane, &asyw->state);
557 plane->state->zpos = nv50_wndw_zpos_default(plane);
558 plane->state->normalized_zpos = nv50_wndw_zpos_default(plane);
562 nv50_wndw_destroy(struct drm_plane *plane)
564 struct nv50_wndw *wndw = nv50_wndw(plane);
565 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp;
567 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) {
568 nv50_wndw_ctxdma_del(ctxdma);
571 nvif_notify_fini(&wndw->notify);
572 nv50_dmac_destroy(&wndw->wimm);
573 nv50_dmac_destroy(&wndw->wndw);
575 nv50_lut_fini(&wndw->ilut);
577 drm_plane_cleanup(&wndw->plane);
581 const struct drm_plane_funcs
583 .update_plane = drm_atomic_helper_update_plane,
584 .disable_plane = drm_atomic_helper_disable_plane,
585 .destroy = nv50_wndw_destroy,
586 .reset = nv50_wndw_reset,
587 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
588 .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
592 nv50_wndw_notify(struct nvif_notify *notify)
594 return NVIF_NOTIFY_KEEP;
598 nv50_wndw_fini(struct nv50_wndw *wndw)
600 nvif_notify_put(&wndw->notify);
604 nv50_wndw_init(struct nv50_wndw *wndw)
606 nvif_notify_get(&wndw->notify);
610 nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
611 enum drm_plane_type type, const char *name, int index,
612 const u32 *format, u32 heads,
613 enum nv50_disp_interlock_type interlock_type, u32 interlock_data,
614 struct nv50_wndw **pwndw)
616 struct nouveau_drm *drm = nouveau_drm(dev);
617 struct nvif_mmu *mmu = &drm->client.mmu;
618 struct nv50_disp *disp = nv50_disp(dev);
619 struct nv50_wndw *wndw;
623 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL)))
627 wndw->interlock.type = interlock_type;
628 wndw->interlock.data = interlock_data;
630 wndw->ctxdma.parent = &wndw->wndw.base.user;
631 INIT_LIST_HEAD(&wndw->ctxdma.list);
633 for (nformat = 0; format[nformat]; nformat++);
635 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw,
636 format, nformat, NULL,
637 type, "%s-%d", name, index);
644 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
646 if (wndw->func->ilut) {
647 ret = nv50_lut_init(disp, mmu, &wndw->ilut);
652 wndw->notify.func = nv50_wndw_notify;
654 if (wndw->func->blend_set) {
655 ret = drm_plane_create_zpos_property(&wndw->plane,
656 nv50_wndw_zpos_default(&wndw->plane), 0, 254);
660 ret = drm_plane_create_zpos_immutable_property(&wndw->plane,
661 nv50_wndw_zpos_default(&wndw->plane));
670 nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
671 struct nv50_wndw **pwndw)
676 int (*new)(struct nouveau_drm *, enum drm_plane_type,
677 int, s32, struct nv50_wndw **);
679 { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
680 { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
683 struct nv50_disp *disp = nv50_disp(drm->dev);
686 cid = nvif_mclass(&disp->disp->object, wndws);
688 NV_ERROR(drm, "No supported window class\n");
692 ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw);
696 return nv50_wimm_init(drm, *pwndw);