2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "nouveau_drv.h"
26 #include "nouveau_dma.h"
27 #include "nouveau_fence.h"
29 #include "nv50_display.h"
32 nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
34 int ret = RING_SPACE(chan, 8);
36 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
37 OUT_RING (chan, chan->vram.handle);
38 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
39 OUT_RING (chan, upper_32_bits(virtual));
40 OUT_RING (chan, lower_32_bits(virtual));
41 OUT_RING (chan, sequence);
42 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
43 OUT_RING (chan, 0x00000000);
50 nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
52 int ret = RING_SPACE(chan, 7);
54 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
55 OUT_RING (chan, chan->vram.handle);
56 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
57 OUT_RING (chan, upper_32_bits(virtual));
58 OUT_RING (chan, lower_32_bits(virtual));
59 OUT_RING (chan, sequence);
60 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
67 nv84_fence_emit(struct nouveau_fence *fence)
69 struct nouveau_channel *chan = fence->channel;
70 struct nv84_fence_chan *fctx = chan->fence;
71 u64 addr = chan->chid * 16;
74 addr += fctx->vma_gart.offset;
76 addr += fctx->vma.offset;
78 return fctx->base.emit32(chan, addr, fence->base.seqno);
82 nv84_fence_sync(struct nouveau_fence *fence,
83 struct nouveau_channel *prev, struct nouveau_channel *chan)
85 struct nv84_fence_chan *fctx = chan->fence;
86 u64 addr = prev->chid * 16;
89 addr += fctx->vma_gart.offset;
91 addr += fctx->vma.offset;
93 return fctx->base.sync32(chan, addr, fence->base.seqno);
97 nv84_fence_read(struct nouveau_channel *chan)
99 struct nv84_fence_priv *priv = chan->drm->fence;
100 return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
104 nv84_fence_context_del(struct nouveau_channel *chan)
106 struct nv84_fence_priv *priv = chan->drm->fence;
107 struct nv84_fence_chan *fctx = chan->fence;
109 nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
110 nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
111 nouveau_bo_vma_del(priv->bo, &fctx->vma);
112 nouveau_fence_context_del(&fctx->base);
114 nouveau_fence_context_free(&fctx->base);
118 nv84_fence_context_new(struct nouveau_channel *chan)
120 struct nouveau_cli *cli = (void *)chan->user.client;
121 struct nv84_fence_priv *priv = chan->drm->fence;
122 struct nv84_fence_chan *fctx;
125 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
129 nouveau_fence_context_new(chan, &fctx->base);
130 fctx->base.emit = nv84_fence_emit;
131 fctx->base.sync = nv84_fence_sync;
132 fctx->base.read = nv84_fence_read;
133 fctx->base.emit32 = nv84_fence_emit32;
134 fctx->base.sync32 = nv84_fence_sync32;
135 fctx->base.sequence = nv84_fence_read(chan);
137 ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma);
139 ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm,
144 nv84_fence_context_del(chan);
149 nv84_fence_suspend(struct nouveau_drm *drm)
151 struct nv84_fence_priv *priv = drm->fence;
154 priv->suspend = vmalloc(priv->base.contexts * sizeof(u32));
156 for (i = 0; i < priv->base.contexts; i++)
157 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
160 return priv->suspend != NULL;
164 nv84_fence_resume(struct nouveau_drm *drm)
166 struct nv84_fence_priv *priv = drm->fence;
170 for (i = 0; i < priv->base.contexts; i++)
171 nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
172 vfree(priv->suspend);
173 priv->suspend = NULL;
178 nv84_fence_destroy(struct nouveau_drm *drm)
180 struct nv84_fence_priv *priv = drm->fence;
181 nouveau_bo_unmap(priv->bo_gart);
183 nouveau_bo_unpin(priv->bo_gart);
184 nouveau_bo_ref(NULL, &priv->bo_gart);
185 nouveau_bo_unmap(priv->bo);
187 nouveau_bo_unpin(priv->bo);
188 nouveau_bo_ref(NULL, &priv->bo);
194 nv84_fence_create(struct nouveau_drm *drm)
196 struct nvkm_fifo *fifo = nvxx_fifo(&drm->device);
197 struct nv84_fence_priv *priv;
201 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
205 priv->base.dtor = nv84_fence_destroy;
206 priv->base.suspend = nv84_fence_suspend;
207 priv->base.resume = nv84_fence_resume;
208 priv->base.context_new = nv84_fence_context_new;
209 priv->base.context_del = nv84_fence_context_del;
211 priv->base.contexts = fifo->nr;
212 priv->base.context_base = dma_fence_context_alloc(priv->base.contexts);
213 priv->base.uevent = true;
215 /* Use VRAM if there is any ; otherwise fallback to system memory */
216 domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
218 * fences created in sysmem must be non-cached or we
219 * will lose CPU/GPU coherency!
221 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
222 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0,
223 0, NULL, NULL, &priv->bo);
225 ret = nouveau_bo_pin(priv->bo, domain, false);
227 ret = nouveau_bo_map(priv->bo);
229 nouveau_bo_unpin(priv->bo);
232 nouveau_bo_ref(NULL, &priv->bo);
236 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0,
237 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED, 0,
238 0, NULL, NULL, &priv->bo_gart);
240 ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT, false);
242 ret = nouveau_bo_map(priv->bo_gart);
244 nouveau_bo_unpin(priv->bo_gart);
247 nouveau_bo_ref(NULL, &priv->bo_gart);
251 nv84_fence_destroy(drm);