drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "gf100.h"
  25 #include "ctxgf100.h"
  26 #include "fuc/os.h"
  27
  28 #include <core/client.h>
  29 #include <core/option.h>
  30 #include <core/firmware.h>
  31 #include <subdev/secboot.h>
  32 #include <subdev/fb.h>
  33 #include <subdev/mc.h>
  34 #include <subdev/pmu.h>
  35 #include <subdev/therm.h>
  36 #include <subdev/timer.h>
  37 #include <engine/fifo.h>
  38
  39 #include <nvif/class.h>
  40 #include <nvif/cl9097.h>
  41 #include <nvif/if900d.h>
  42 #include <nvif/unpack.h>
  43
  44 /*******************************************************************************
  45  * Zero Bandwidth Clear
  46  ******************************************************************************/
  47
  48 static void
  49 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
  50 {
  51         struct nvkm_device *device = gr->base.engine.subdev.device;
  52         if (gr->zbc_color[zbc].format) {
  53                 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]);
  54                 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]);
  55                 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]);
  56                 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]);
  57         }
  58         nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format);
  59         nvkm_wr32(device, 0x405820, zbc);
  60         nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
  61 }
  62
  63 static int
  64 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
  65                        const u32 ds[4], const u32 l2[4])
  66 {
  67         struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
  68         int zbc = -ENOSPC, i;
  69
  70         for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
  71                 if (gr->zbc_color[i].format) {
  72                         if (gr->zbc_color[i].format != format)
  73                                 continue;
  74                         if (memcmp(gr->zbc_color[i].ds, ds, sizeof(
  75                                    gr->zbc_color[i].ds)))
  76                                 continue;
  77                         if (memcmp(gr->zbc_color[i].l2, l2, sizeof(
  78                                    gr->zbc_color[i].l2))) {
  79                                 WARN_ON(1);
  80                                 return -EINVAL;
  81                         }
  82                         return i;
  83                 } else {
  84                         zbc = (zbc < 0) ? i : zbc;
  85                 }
  86         }
  87
  88         if (zbc < 0)
  89                 return zbc;
  90
  91         memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
  92         memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
  93         gr->zbc_color[zbc].format = format;
  94         nvkm_ltc_zbc_color_get(ltc, zbc, l2);
  95         gr->func->zbc->clear_color(gr, zbc);
  96         return zbc;
  97 }
  98
  99 static void
 100 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
 101 {
 102         struct nvkm_device *device = gr->base.engine.subdev.device;
 103         if (gr->zbc_depth[zbc].format)
 104                 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds);
 105         nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format);
 106         nvkm_wr32(device, 0x405820, zbc);
 107         nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
 108 }
 109
 110 static int
 111 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
 112                        const u32 ds, const u32 l2)
 113 {
 114         struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
 115         int zbc = -ENOSPC, i;
 116
 117         for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
 118                 if (gr->zbc_depth[i].format) {
 119                         if (gr->zbc_depth[i].format != format)
 120                                 continue;
 121                         if (gr->zbc_depth[i].ds != ds)
 122                                 continue;
 123                         if (gr->zbc_depth[i].l2 != l2) {
 124                                 WARN_ON(1);
 125                                 return -EINVAL;
 126                         }
 127                         return i;
 128                 } else {
 129                         zbc = (zbc < 0) ? i : zbc;
 130                 }
 131         }
 132
 133         if (zbc < 0)
 134                 return zbc;
 135
 136         gr->zbc_depth[zbc].format = format;
 137         gr->zbc_depth[zbc].ds = ds;
 138         gr->zbc_depth[zbc].l2 = l2;
 139         nvkm_ltc_zbc_depth_get(ltc, zbc, l2);
 140         gr->func->zbc->clear_depth(gr, zbc);
 141         return zbc;
 142 }
 143
 144 const struct gf100_gr_func_zbc
 145 gf100_gr_zbc = {
 146         .clear_color = gf100_gr_zbc_clear_color,
 147         .clear_depth = gf100_gr_zbc_clear_depth,
 148 };
 149
 150 /*******************************************************************************
 151  * Graphics object classes
 152  ******************************************************************************/
 153 #define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object)
 154
 155 struct gf100_gr_object {
 156         struct nvkm_object object;
 157         struct gf100_gr_chan *chan;
 158 };
 159
 160 static int
 161 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
 162 {
 163         struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
 164         union {
 165                 struct fermi_a_zbc_color_v0 v0;
 166         } *args = data;
 167         int ret = -ENOSYS;
 168
 169         if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
 170                 switch (args->v0.format) {
 171                 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO:
 172                 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE:
 173                 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32:
 174                 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16:
 175                 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16:
 176                 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16:
 177                 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16:
 178                 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16:
 179                 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8:
 180                 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8:
 181                 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10:
 182                 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10:
 183                 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8:
 184                 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8:
 185                 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8:
 186                 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8:
 187                 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
 188                 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
 189                 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
 190                         ret = gf100_gr_zbc_color_get(gr, args->v0.format,
 191                                                            args->v0.ds,
 192                                                            args->v0.l2);
 193                         if (ret >= 0) {
 194                                 args->v0.index = ret;
 195                                 return 0;
 196                         }
 197                         break;
 198                 default:
 199                         return -EINVAL;
 200                 }
 201         }
 202
 203         return ret;
 204 }
 205
 206 static int
 207 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
 208 {
 209         struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
 210         union {
 211                 struct fermi_a_zbc_depth_v0 v0;
 212         } *args = data;
 213         int ret = -ENOSYS;
 214
 215         if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
 216                 switch (args->v0.format) {
 217                 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
 218                         ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
 219                                                            args->v0.ds,
 220                                                            args->v0.l2);
 221                         return (ret >= 0) ? 0 : -ENOSPC;
 222                 default:
 223                         return -EINVAL;
 224                 }
 225         }
 226
 227         return ret;
 228 }
 229
 230 static int
 231 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
 232 {
 233         nvif_ioctl(object, "fermi mthd %08x\n", mthd);
 234         switch (mthd) {
 235         case FERMI_A_ZBC_COLOR:
 236                 return gf100_fermi_mthd_zbc_color(object, data, size);
 237         case FERMI_A_ZBC_DEPTH:
 238                 return gf100_fermi_mthd_zbc_depth(object, data, size);
 239         default:
 240                 break;
 241         }
 242         return -EINVAL;
 243 }
 244
 245 const struct nvkm_object_func
 246 gf100_fermi = {
 247         .mthd = gf100_fermi_mthd,
 248 };
 249
 250 static void
 251 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data)
 252 {
 253         nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000);
 254         nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000);
 255 }
 256
 257 static bool
 258 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data)
 259 {
 260         switch (class & 0x00ff) {
 261         case 0x97:
 262         case 0xc0:
 263                 switch (mthd) {
 264                 case 0x1528:
 265                         gf100_gr_mthd_set_shader_exceptions(device, data);
 266                         return true;
 267                 default:
 268                         break;
 269                 }
 270                 break;
 271         default:
 272                 break;
 273         }
 274         return false;
 275 }
 276
 277 static const struct nvkm_object_func
 278 gf100_gr_object_func = {
 279 };
 280
 281 static int
 282 gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
 283                     struct nvkm_object **pobject)
 284 {
 285         struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent);
 286         struct gf100_gr_object *object;
 287
 288         if (!(object = kzalloc(sizeof(*object), GFP_KERNEL)))
 289                 return -ENOMEM;
 290         *pobject = &object->object;
 291
 292         nvkm_object_ctor(oclass->base.func ? oclass->base.func :
 293                          &gf100_gr_object_func, oclass, &object->object);
 294         object->chan = chan;
 295         return 0;
 296 }
 297
 298 static int
 299 gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass)
 300 {
 301         struct gf100_gr *gr = gf100_gr(base);
 302         int c = 0;
 303
 304         while (gr->func->sclass[c].oclass) {
 305                 if (c++ == index) {
 306                         *sclass = gr->func->sclass[index];
 307                         sclass->ctor = gf100_gr_object_new;
 308                         return index;
 309                 }
 310         }
 311
 312         return c;
 313 }
 314
 315 /*******************************************************************************
 316  * PGRAPH context
 317  ******************************************************************************/
 318
 319 static int
 320 gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
 321                    int align, struct nvkm_gpuobj **pgpuobj)
 322 {
 323         struct gf100_gr_chan *chan = gf100_gr_chan(object);
 324         struct gf100_gr *gr = chan->gr;
 325         int ret, i;
 326
 327         ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
 328                               align, false, parent, pgpuobj);
 329         if (ret)
 330                 return ret;
 331
 332         nvkm_kmap(*pgpuobj);
 333         for (i = 0; i < gr->size; i += 4)
 334                 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]);
 335
 336         if (!gr->firmware) {
 337                 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2);
 338                 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8);
 339         } else {
 340                 nvkm_wo32(*pgpuobj, 0xf4, 0);
 341                 nvkm_wo32(*pgpuobj, 0xf8, 0);
 342                 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2);
 343                 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr));
 344                 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr));
 345                 nvkm_wo32(*pgpuobj, 0x1c, 1);
 346                 nvkm_wo32(*pgpuobj, 0x20, 0);
 347                 nvkm_wo32(*pgpuobj, 0x28, 0);
 348                 nvkm_wo32(*pgpuobj, 0x2c, 0);
 349         }
 350         nvkm_done(*pgpuobj);
 351         return 0;
 352 }
 353
 354 static void *
 355 gf100_gr_chan_dtor(struct nvkm_object *object)
 356 {
 357         struct gf100_gr_chan *chan = gf100_gr_chan(object);
 358         int i;
 359
 360         for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
 361                 nvkm_vmm_put(chan->vmm, &chan->data[i].vma);
 362                 nvkm_memory_unref(&chan->data[i].mem);
 363         }
 364
 365         nvkm_vmm_put(chan->vmm, &chan->mmio_vma);
 366         nvkm_memory_unref(&chan->mmio);
 367         nvkm_vmm_unref(&chan->vmm);
 368         return chan;
 369 }
 370
 371 static const struct nvkm_object_func
 372 gf100_gr_chan = {
 373         .dtor = gf100_gr_chan_dtor,
 374         .bind = gf100_gr_chan_bind,
 375 };
 376
 377 static int
 378 gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
 379                   const struct nvkm_oclass *oclass,
 380                   struct nvkm_object **pobject)
 381 {
 382         struct gf100_gr *gr = gf100_gr(base);
 383         struct gf100_gr_data *data = gr->mmio_data;
 384         struct gf100_gr_mmio *mmio = gr->mmio_list;
 385         struct gf100_gr_chan *chan;
 386         struct gf100_vmm_map_v0 args = { .priv = 1 };
 387         struct nvkm_device *device = gr->base.engine.subdev.device;
 388         int ret, i;
 389
 390         if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
 391                 return -ENOMEM;
 392         nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object);
 393         chan->gr = gr;
 394         chan->vmm = nvkm_vmm_ref(fifoch->vmm);
 395         *pobject = &chan->object;
 396
 397         /* allocate memory for a "mmio list" buffer that's used by the HUB
 398          * fuc to modify some per-context register settings on first load
 399          * of the context.
 400          */
 401         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100,
 402                               false, &chan->mmio);
 403         if (ret)
 404                 return ret;
 405
 406         ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma);
 407         if (ret)
 408                 return ret;
 409
 410         ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm,
 411                               chan->mmio_vma, &args, sizeof(args));
 412         if (ret)
 413                 return ret;
 414
 415         /* allocate buffers referenced by mmio list */
 416         for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) {
 417                 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
 418                                       data->size, data->align, false,
 419                                       &chan->data[i].mem);
 420                 if (ret)
 421                         return ret;
 422
 423                 ret = nvkm_vmm_get(fifoch->vmm, 12,
 424                                    nvkm_memory_size(chan->data[i].mem),
 425                                    &chan->data[i].vma);
 426                 if (ret)
 427                         return ret;
 428
 429                 args.priv = data->priv;
 430
 431                 ret = nvkm_memory_map(chan->data[i].mem, 0, chan->vmm,
 432                                       chan->data[i].vma, &args, sizeof(args));
 433                 if (ret)
 434                         return ret;
 435
 436                 data++;
 437         }
 438
 439         /* finally, fill in the mmio list and point the context at it */
 440         nvkm_kmap(chan->mmio);
 441         for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {
 442                 u32 addr = mmio->addr;
 443                 u32 data = mmio->data;
 444
 445                 if (mmio->buffer >= 0) {
 446                         u64 info = chan->data[mmio->buffer].vma->addr;
 447                         data |= info >> mmio->shift;
 448                 }
 449
 450                 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
 451                 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
 452                 mmio++;
 453         }
 454         nvkm_done(chan->mmio);
 455         return 0;
 456 }
 457
 458 /*******************************************************************************
 459  * PGRAPH register lists
 460  ******************************************************************************/
 461
 462 const struct gf100_gr_init
 463 gf100_gr_init_main_0[] = {
 464         { 0x400080,   1, 0x04, 0x003083c2 },
 465         { 0x400088,   1, 0x04, 0x00006fe7 },
 466         { 0x40008c,   1, 0x04, 0x00000000 },
 467         { 0x400090,   1, 0x04, 0x00000030 },
 468         { 0x40013c,   1, 0x04, 0x013901f7 },
 469         { 0x400140,   1, 0x04, 0x00000100 },
 470         { 0x400144,   1, 0x04, 0x00000000 },
 471         { 0x400148,   1, 0x04, 0x00000110 },
 472         { 0x400138,   1, 0x04, 0x00000000 },
 473         { 0x400130,   2, 0x04, 0x00000000 },
 474         { 0x400124,   1, 0x04, 0x00000002 },
 475         {}
 476 };
 477
 478 const struct gf100_gr_init
 479 gf100_gr_init_fe_0[] = {
 480         { 0x40415c,   1, 0x04, 0x00000000 },
 481         { 0x404170,   1, 0x04, 0x00000000 },
 482         {}
 483 };
 484
 485 const struct gf100_gr_init
 486 gf100_gr_init_pri_0[] = {
 487         { 0x404488,   2, 0x04, 0x00000000 },
 488         {}
 489 };
 490
 491 const struct gf100_gr_init
 492 gf100_gr_init_rstr2d_0[] = {
 493         { 0x407808,   1, 0x04, 0x00000000 },
 494         {}
 495 };
 496
 497 const struct gf100_gr_init
 498 gf100_gr_init_pd_0[] = {
 499         { 0x406024,   1, 0x04, 0x00000000 },
 500         {}
 501 };
 502
 503 const struct gf100_gr_init
 504 gf100_gr_init_ds_0[] = {
 505         { 0x405844,   1, 0x04, 0x00ffffff },
 506         { 0x405850,   1, 0x04, 0x00000000 },
 507         { 0x405908,   1, 0x04, 0x00000000 },
 508         {}
 509 };
 510
 511 const struct gf100_gr_init
 512 gf100_gr_init_scc_0[] = {
 513         { 0x40803c,   1, 0x04, 0x00000000 },
 514         {}
 515 };
 516
 517 const struct gf100_gr_init
 518 gf100_gr_init_prop_0[] = {
 519         { 0x4184a0,   1, 0x04, 0x00000000 },
 520         {}
 521 };
 522
 523 const struct gf100_gr_init
 524 gf100_gr_init_gpc_unk_0[] = {
 525         { 0x418604,   1, 0x04, 0x00000000 },
 526         { 0x418680,   1, 0x04, 0x00000000 },
 527         { 0x418714,   1, 0x04, 0x80000000 },
 528         { 0x418384,   1, 0x04, 0x00000000 },
 529         {}
 530 };
 531
 532 const struct gf100_gr_init
 533 gf100_gr_init_setup_0[] = {
 534         { 0x418814,   3, 0x04, 0x00000000 },
 535         {}
 536 };
 537
 538 const struct gf100_gr_init
 539 gf100_gr_init_crstr_0[] = {
 540         { 0x418b04,   1, 0x04, 0x00000000 },
 541         {}
 542 };
 543
 544 const struct gf100_gr_init
 545 gf100_gr_init_setup_1[] = {
 546         { 0x4188c8,   1, 0x04, 0x80000000 },
 547         { 0x4188cc,   1, 0x04, 0x00000000 },
 548         { 0x4188d0,   1, 0x04, 0x00010000 },
 549         { 0x4188d4,   1, 0x04, 0x00000001 },
 550         {}
 551 };
 552
 553 const struct gf100_gr_init
 554 gf100_gr_init_zcull_0[] = {
 555         { 0x418910,   1, 0x04, 0x00010001 },
 556         { 0x418914,   1, 0x04, 0x00000301 },
 557         { 0x418918,   1, 0x04, 0x00800000 },
 558         { 0x418980,   1, 0x04, 0x77777770 },
 559         { 0x418984,   3, 0x04, 0x77777777 },
 560         {}
 561 };
 562
 563 const struct gf100_gr_init
 564 gf100_gr_init_gpm_0[] = {
 565         { 0x418c04,   1, 0x04, 0x00000000 },
 566         { 0x418c88,   1, 0x04, 0x00000000 },
 567         {}
 568 };
 569
 570 const struct gf100_gr_init
 571 gf100_gr_init_gpc_unk_1[] = {
 572         { 0x418d00,   1, 0x04, 0x00000000 },
 573         { 0x418f08,   1, 0x04, 0x00000000 },
 574         { 0x418e00,   1, 0x04, 0x00000050 },
 575         { 0x418e08,   1, 0x04, 0x00000000 },
 576         {}
 577 };
 578
 579 const struct gf100_gr_init
 580 gf100_gr_init_gcc_0[] = {
 581         { 0x41900c,   1, 0x04, 0x00000000 },
 582         { 0x419018,   1, 0x04, 0x00000000 },
 583         {}
 584 };
 585
 586 const struct gf100_gr_init
 587 gf100_gr_init_tpccs_0[] = {
 588         { 0x419d08,   2, 0x04, 0x00000000 },
 589         { 0x419d10,   1, 0x04, 0x00000014 },
 590         {}
 591 };
 592
 593 const struct gf100_gr_init
 594 gf100_gr_init_tex_0[] = {
 595         { 0x419ab0,   1, 0x04, 0x00000000 },
 596         { 0x419ab8,   1, 0x04, 0x000000e7 },
 597         { 0x419abc,   2, 0x04, 0x00000000 },
 598         {}
 599 };
 600
 601 const struct gf100_gr_init
 602 gf100_gr_init_pe_0[] = {
 603         { 0x41980c,   3, 0x04, 0x00000000 },
 604         { 0x419844,   1, 0x04, 0x00000000 },
 605         { 0x41984c,   1, 0x04, 0x00005bc5 },
 606         { 0x419850,   4, 0x04, 0x00000000 },
 607         {}
 608 };
 609
 610 const struct gf100_gr_init
 611 gf100_gr_init_l1c_0[] = {
 612         { 0x419c98,   1, 0x04, 0x00000000 },
 613         { 0x419ca8,   1, 0x04, 0x80000000 },
 614         { 0x419cb4,   1, 0x04, 0x00000000 },
 615         { 0x419cb8,   1, 0x04, 0x00008bf4 },
 616         { 0x419cbc,   1, 0x04, 0x28137606 },
 617         { 0x419cc0,   2, 0x04, 0x00000000 },
 618         {}
 619 };
 620
 621 const struct gf100_gr_init
 622 gf100_gr_init_wwdx_0[] = {
 623         { 0x419bd4,   1, 0x04, 0x00800000 },
 624         { 0x419bdc,   1, 0x04, 0x00000000 },
 625         {}
 626 };
 627
 628 const struct gf100_gr_init
 629 gf100_gr_init_tpccs_1[] = {
 630         { 0x419d2c,   1, 0x04, 0x00000000 },
 631         {}
 632 };
 633
 634 const struct gf100_gr_init
 635 gf100_gr_init_mpc_0[] = {
 636         { 0x419c0c,   1, 0x04, 0x00000000 },
 637         {}
 638 };
 639
 640 static const struct gf100_gr_init
 641 gf100_gr_init_sm_0[] = {
 642         { 0x419e00,   1, 0x04, 0x00000000 },
 643         { 0x419ea0,   1, 0x04, 0x00000000 },
 644         { 0x419ea4,   1, 0x04, 0x00000100 },
 645         { 0x419ea8,   1, 0x04, 0x00001100 },
 646         { 0x419eac,   1, 0x04, 0x11100702 },
 647         { 0x419eb0,   1, 0x04, 0x00000003 },
 648         { 0x419eb4,   4, 0x04, 0x00000000 },
 649         { 0x419ec8,   1, 0x04, 0x06060618 },
 650         { 0x419ed0,   1, 0x04, 0x0eff0e38 },
 651         { 0x419ed4,   1, 0x04, 0x011104f1 },
 652         { 0x419edc,   1, 0x04, 0x00000000 },
 653         { 0x419f00,   1, 0x04, 0x00000000 },
 654         { 0x419f2c,   1, 0x04, 0x00000000 },
 655         {}
 656 };
 657
 658 const struct gf100_gr_init
 659 gf100_gr_init_be_0[] = {
 660         { 0x40880c,   1, 0x04, 0x00000000 },
 661         { 0x408910,   9, 0x04, 0x00000000 },
 662         { 0x408950,   1, 0x04, 0x00000000 },
 663         { 0x408954,   1, 0x04, 0x0000ffff },
 664         { 0x408984,   1, 0x04, 0x00000000 },
 665         { 0x408988,   1, 0x04, 0x08040201 },
 666         { 0x40898c,   1, 0x04, 0x80402010 },
 667         {}
 668 };
 669
 670 const struct gf100_gr_init
 671 gf100_gr_init_fe_1[] = {
 672         { 0x4040f0,   1, 0x04, 0x00000000 },
 673         {}
 674 };
 675
 676 const struct gf100_gr_init
 677 gf100_gr_init_pe_1[] = {
 678         { 0x419880,   1, 0x04, 0x00000002 },
 679         {}
 680 };
 681
 682 static const struct gf100_gr_pack
 683 gf100_gr_pack_mmio[] = {
 684         { gf100_gr_init_main_0 },
 685         { gf100_gr_init_fe_0 },
 686         { gf100_gr_init_pri_0 },
 687         { gf100_gr_init_rstr2d_0 },
 688         { gf100_gr_init_pd_0 },
 689         { gf100_gr_init_ds_0 },
 690         { gf100_gr_init_scc_0 },
 691         { gf100_gr_init_prop_0 },
 692         { gf100_gr_init_gpc_unk_0 },
 693         { gf100_gr_init_setup_0 },
 694         { gf100_gr_init_crstr_0 },
 695         { gf100_gr_init_setup_1 },
 696         { gf100_gr_init_zcull_0 },
 697         { gf100_gr_init_gpm_0 },
 698         { gf100_gr_init_gpc_unk_1 },
 699         { gf100_gr_init_gcc_0 },
 700         { gf100_gr_init_tpccs_0 },
 701         { gf100_gr_init_tex_0 },
 702         { gf100_gr_init_pe_0 },
 703         { gf100_gr_init_l1c_0 },
 704         { gf100_gr_init_wwdx_0 },
 705         { gf100_gr_init_tpccs_1 },
 706         { gf100_gr_init_mpc_0 },
 707         { gf100_gr_init_sm_0 },
 708         { gf100_gr_init_be_0 },
 709         { gf100_gr_init_fe_1 },
 710         { gf100_gr_init_pe_1 },
 711         {}
 712 };
 713
 714 /*******************************************************************************
 715  * PGRAPH engine/subdev functions
 716  ******************************************************************************/
 717
 718 static int
 719 gf100_gr_fecs_discover_pm_image_size(struct gf100_gr *gr, u32 *psize)
 720 {
 721         struct nvkm_device *device = gr->base.engine.subdev.device;
 722
 723         nvkm_wr32(device, 0x409840, 0xffffffff);
 724         nvkm_wr32(device, 0x409500, 0x00000000);
 725         nvkm_wr32(device, 0x409504, 0x00000025);
 726         nvkm_msec(device, 2000,
 727                 if ((*psize = nvkm_rd32(device, 0x409800)))
 728                         return 0;
 729         );
 730
 731         return -ETIMEDOUT;
 732 }
 733
 734 static int
 735 gf100_gr_fecs_discover_zcull_image_size(struct gf100_gr *gr, u32 *psize)
 736 {
 737         struct nvkm_device *device = gr->base.engine.subdev.device;
 738
 739         nvkm_wr32(device, 0x409840, 0xffffffff);
 740         nvkm_wr32(device, 0x409500, 0x00000000);
 741         nvkm_wr32(device, 0x409504, 0x00000016);
 742         nvkm_msec(device, 2000,
 743                 if ((*psize = nvkm_rd32(device, 0x409800)))
 744                         return 0;
 745         );
 746
 747         return -ETIMEDOUT;
 748 }
 749
 750 static int
 751 gf100_gr_fecs_discover_image_size(struct gf100_gr *gr, u32 *psize)
 752 {
 753         struct nvkm_device *device = gr->base.engine.subdev.device;
 754
 755         nvkm_wr32(device, 0x409840, 0xffffffff);
 756         nvkm_wr32(device, 0x409500, 0x00000000);
 757         nvkm_wr32(device, 0x409504, 0x00000010);
 758         nvkm_msec(device, 2000,
 759                 if ((*psize = nvkm_rd32(device, 0x409800)))
 760                         return 0;
 761         );
 762
 763         return -ETIMEDOUT;
 764 }
 765
 766 static void
 767 gf100_gr_fecs_set_watchdog_timeout(struct gf100_gr *gr, u32 timeout)
 768 {
 769         struct nvkm_device *device = gr->base.engine.subdev.device;
 770
 771         nvkm_wr32(device, 0x409840, 0xffffffff);
 772         nvkm_wr32(device, 0x409500, timeout);
 773         nvkm_wr32(device, 0x409504, 0x00000021);
 774 }
 775
 776 static bool
 777 gf100_gr_chsw_load(struct nvkm_gr *base)
 778 {
 779         struct gf100_gr *gr = gf100_gr(base);
 780         if (!gr->firmware) {
 781                 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c);
 782                 if (trace & 0x00000040)
 783                         return true;
 784         } else {
 785                 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808);
 786                 if (mthd & 0x00080000)
 787                         return true;
 788         }
 789         return false;
 790 }
 791
 792 int
 793 gf100_gr_rops(struct gf100_gr *gr)
 794 {
 795         struct nvkm_device *device = gr->base.engine.subdev.device;
 796         return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;
 797 }
 798
 799 void
 800 gf100_gr_zbc_init(struct gf100_gr *gr)
 801 {
 802         const u32  zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 803                               0x00000000, 0x00000000, 0x00000000, 0x00000000 };
 804         const u32   one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
 805                               0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
 806         const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 807                               0x00000000, 0x00000000, 0x00000000, 0x00000000 };
 808         const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
 809                               0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
 810         struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
 811         int index, c = ltc->zbc_min, d = ltc->zbc_min, s = ltc->zbc_min;
 812
 813         if (!gr->zbc_color[0].format) {
 814                 gf100_gr_zbc_color_get(gr, 1,  & zero[0],   &zero[4]); c++;
 815                 gf100_gr_zbc_color_get(gr, 2,  &  one[0],    &one[4]); c++;
 816                 gf100_gr_zbc_color_get(gr, 4,  &f32_0[0],  &f32_0[4]); c++;
 817                 gf100_gr_zbc_color_get(gr, 4,  &f32_1[0],  &f32_1[4]); c++;
 818                 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++;
 819                 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++;
 820                 if (gr->func->zbc->stencil_get) {
 821                         gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++;
 822                         gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++;
 823                         gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++;
 824                 }
 825         }
 826
 827         for (index = c; index <= ltc->zbc_max; index++)
 828                 gr->func->zbc->clear_color(gr, index);
 829         for (index = d; index <= ltc->zbc_max; index++)
 830                 gr->func->zbc->clear_depth(gr, index);
 831
 832         if (gr->func->zbc->clear_stencil) {
 833                 for (index = s; index <= ltc->zbc_max; index++)
 834                         gr->func->zbc->clear_stencil(gr, index);
 835         }
 836 }
 837
 838 /**
 839  * Wait until GR goes idle. GR is considered idle if it is disabled by the
 840  * MC (0x200) register, or GR is not busy and a context switch is not in
 841  * progress.
 842  */
 843 int
 844 gf100_gr_wait_idle(struct gf100_gr *gr)
 845 {
 846         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
 847         struct nvkm_device *device = subdev->device;
 848         unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
 849         bool gr_enabled, ctxsw_active, gr_busy;
 850
 851         do {
 852                 /*
 853                  * required to make sure FIFO_ENGINE_STATUS (0x2640) is
 854                  * up-to-date
 855                  */
 856                 nvkm_rd32(device, 0x400700);
 857
 858                 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
 859                 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000;
 860                 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
 861
 862                 if (!gr_enabled || (!gr_busy && !ctxsw_active))
 863                         return 0;
 864         } while (time_before(jiffies, end_jiffies));
 865
 866         nvkm_error(subdev,
 867                    "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
 868                    gr_enabled, ctxsw_active, gr_busy);
 869         return -EAGAIN;
 870 }
 871
 872 void
 873 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
 874 {
 875         struct nvkm_device *device = gr->base.engine.subdev.device;
 876         const struct gf100_gr_pack *pack;
 877         const struct gf100_gr_init *init;
 878
 879         pack_for_each_init(init, pack, p) {
 880                 u32 next = init->addr + init->count * init->pitch;
 881                 u32 addr = init->addr;
 882                 while (addr < next) {
 883                         nvkm_wr32(device, addr, init->data);
 884                         addr += init->pitch;
 885                 }
 886         }
 887 }
 888
 889 void
 890 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
 891 {
 892         struct nvkm_device *device = gr->base.engine.subdev.device;
 893         const struct gf100_gr_pack *pack;
 894         const struct gf100_gr_init *init;
 895         u32 data = 0;
 896
 897         nvkm_wr32(device, 0x400208, 0x80000000);
 898
 899         pack_for_each_init(init, pack, p) {
 900                 u32 next = init->addr + init->count * init->pitch;
 901                 u32 addr = init->addr;
 902
 903                 if ((pack == p && init == p->init) || data != init->data) {
 904                         nvkm_wr32(device, 0x400204, init->data);
 905                         data = init->data;
 906                 }
 907
 908                 while (addr < next) {
 909                         nvkm_wr32(device, 0x400200, addr);
 910                         /**
 911                          * Wait for GR to go idle after submitting a
 912                          * GO_IDLE bundle
 913                          */
 914                         if ((addr & 0xffff) == 0xe100)
 915                                 gf100_gr_wait_idle(gr);
 916                         nvkm_msec(device, 2000,
 917                                 if (!(nvkm_rd32(device, 0x400700) & 0x00000004))
 918                                         break;
 919                         );
 920                         addr += init->pitch;
 921                 }
 922         }
 923
 924         nvkm_wr32(device, 0x400208, 0x00000000);
 925 }
 926
 927 void
 928 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
 929 {
 930         struct nvkm_device *device = gr->base.engine.subdev.device;
 931         const struct gf100_gr_pack *pack;
 932         const struct gf100_gr_init *init;
 933         u32 data = 0;
 934
 935         pack_for_each_init(init, pack, p) {
 936                 u32 ctrl = 0x80000000 | pack->type;
 937                 u32 next = init->addr + init->count * init->pitch;
 938                 u32 addr = init->addr;
 939
 940                 if ((pack == p && init == p->init) || data != init->data) {
 941                         nvkm_wr32(device, 0x40448c, init->data);
 942                         data = init->data;
 943                 }
 944
 945                 while (addr < next) {
 946                         nvkm_wr32(device, 0x404488, ctrl | (addr << 14));
 947                         addr += init->pitch;
 948                 }
 949         }
 950 }
 951
 952 u64
 953 gf100_gr_units(struct nvkm_gr *base)
 954 {
 955         struct gf100_gr *gr = gf100_gr(base);
 956         u64 cfg;
 957
 958         cfg  = (u32)gr->gpc_nr;
 959         cfg |= (u32)gr->tpc_total << 8;
 960         cfg |= (u64)gr->rop_nr << 32;
 961
 962         return cfg;
 963 }
 964
 965 static const struct nvkm_bitfield gf100_dispatch_error[] = {
 966         { 0x00000001, "INJECTED_BUNDLE_ERROR" },
 967         { 0x00000002, "CLASS_SUBCH_MISMATCH" },
 968         { 0x00000004, "SUBCHSW_DURING_NOTIFY" },
 969         {}
 970 };
 971
 972 static const struct nvkm_bitfield gf100_m2mf_error[] = {
 973         { 0x00000001, "PUSH_TOO_MUCH_DATA" },
 974         { 0x00000002, "PUSH_NOT_ENOUGH_DATA" },
 975         {}
 976 };
 977
 978 static const struct nvkm_bitfield gf100_unk6_error[] = {
 979         { 0x00000001, "TEMP_TOO_SMALL" },
 980         {}
 981 };
 982
 983 static const struct nvkm_bitfield gf100_ccache_error[] = {
 984         { 0x00000001, "INTR" },
 985         { 0x00000002, "LDCONST_OOB" },
 986         {}
 987 };
 988
 989 static const struct nvkm_bitfield gf100_macro_error[] = {
 990         { 0x00000001, "TOO_FEW_PARAMS" },
 991         { 0x00000002, "TOO_MANY_PARAMS" },
 992         { 0x00000004, "ILLEGAL_OPCODE" },
 993         { 0x00000008, "DOUBLE_BRANCH" },
 994         { 0x00000010, "WATCHDOG" },
 995         {}
 996 };
 997
 998 static const struct nvkm_bitfield gk104_sked_error[] = {
 999         { 0x00000040, "CTA_RESUME" },
1000         { 0x00000080, "CONSTANT_BUFFER_SIZE" },
1001         { 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
1002         { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
1003         { 0x00000800, "WARP_CSTACK_SIZE" },
1004         { 0x00001000, "TOTAL_TEMP_SIZE" },
1005         { 0x00002000, "REGISTER_COUNT" },
1006         { 0x00040000, "TOTAL_THREADS" },
1007         { 0x00100000, "PROGRAM_OFFSET" },
1008         { 0x00200000, "SHARED_MEMORY_SIZE" },
1009         { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" },
1010         { 0x01000000, "MEMORY_WINDOW_OVERLAP" },
1011         { 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
1012         { 0x04000000, "TOTAL_REGISTER_COUNT" },
1013         {}
1014 };
1015
1016 static const struct nvkm_bitfield gf100_gpc_rop_error[] = {
1017         { 0x00000002, "RT_PITCH_OVERRUN" },
1018         { 0x00000010, "RT_WIDTH_OVERRUN" },
1019         { 0x00000020, "RT_HEIGHT_OVERRUN" },
1020         { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
1021         { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
1022         { 0x00000400, "RT_LINEAR_MISMATCH" },
1023         {}
1024 };
1025
1026 static void
1027 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
1028 {
1029         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1030         struct nvkm_device *device = subdev->device;
1031         char error[128];
1032         u32 trap[4];
1033
1034         trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
1035         trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
1036         trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
1037         trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
1038
1039         nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]);
1040
1041         nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, "
1042                            "format = %x, storage type = %x\n",
1043                    gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16,
1044                    (trap[2] >> 8) & 0x3f, trap[3] & 0xff);
1045         nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
1046 }
1047
1048 const struct nvkm_enum gf100_mp_warp_error[] = {
1049         { 0x01, "STACK_ERROR" },
1050         { 0x02, "API_STACK_ERROR" },
1051         { 0x03, "RET_EMPTY_STACK_ERROR" },
1052         { 0x04, "PC_WRAP" },
1053         { 0x05, "MISALIGNED_PC" },
1054         { 0x06, "PC_OVERFLOW" },
1055         { 0x07, "MISALIGNED_IMMC_ADDR" },
1056         { 0x08, "MISALIGNED_REG" },
1057         { 0x09, "ILLEGAL_INSTR_ENCODING" },
1058         { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" },
1059         { 0x0b, "ILLEGAL_INSTR_PARAM" },
1060         { 0x0c, "INVALID_CONST_ADDR" },
1061         { 0x0d, "OOR_REG" },
1062         { 0x0e, "OOR_ADDR" },
1063         { 0x0f, "MISALIGNED_ADDR" },
1064         { 0x10, "INVALID_ADDR_SPACE" },
1065         { 0x11, "ILLEGAL_INSTR_PARAM2" },
1066         { 0x12, "INVALID_CONST_ADDR_LDC" },
1067         { 0x13, "GEOMETRY_SM_ERROR" },
1068         { 0x14, "DIVERGENT" },
1069         { 0x15, "WARP_EXIT" },
1070         {}
1071 };
1072
1073 const struct nvkm_bitfield gf100_mp_global_error[] = {
1074         { 0x00000001, "SM_TO_SM_FAULT" },
1075         { 0x00000002, "L1_ERROR" },
1076         { 0x00000004, "MULTIPLE_WARP_ERRORS" },
1077         { 0x00000008, "PHYSICAL_STACK_OVERFLOW" },
1078         { 0x00000010, "BPT_INT" },
1079         { 0x00000020, "BPT_PAUSE" },
1080         { 0x00000040, "SINGLE_STEP_COMPLETE" },
1081         { 0x20000000, "ECC_SEC_ERROR" },
1082         { 0x40000000, "ECC_DED_ERROR" },
1083         { 0x80000000, "TIMEOUT" },
1084         {}
1085 };
1086
1087 void
1088 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
1089 {
1090         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1091         struct nvkm_device *device = subdev->device;
1092         u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));
1093         u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));
1094         const struct nvkm_enum *warp;
1095         char glob[128];
1096
1097         nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
1098         warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
1099
1100         nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
1101                            "global %08x [%s] warp %04x [%s]\n",
1102                    gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
1103
1104         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
1105         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);
1106 }
1107
1108 static void
1109 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
1110 {
1111         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1112         struct nvkm_device *device = subdev->device;
1113         u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));
1114
1115         if (stat & 0x00000001) {
1116                 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));
1117                 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap);
1118                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
1119                 stat &= ~0x00000001;
1120         }
1121
1122         if (stat & 0x00000002) {
1123                 gr->func->trap_mp(gr, gpc, tpc);
1124                 stat &= ~0x00000002;
1125         }
1126
1127         if (stat & 0x00000004) {
1128                 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));
1129                 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap);
1130                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
1131                 stat &= ~0x00000004;
1132         }
1133
1134         if (stat & 0x00000008) {
1135                 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));
1136                 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap);
1137                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
1138                 stat &= ~0x00000008;
1139         }
1140
1141         if (stat & 0x00000010) {
1142                 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430));
1143                 nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap);
1144                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000);
1145                 stat &= ~0x00000010;
1146         }
1147
1148         if (stat) {
1149                 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat);
1150         }
1151 }
1152
1153 static void
1154 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
1155 {
1156         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1157         struct nvkm_device *device = subdev->device;
1158         u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));
1159         int tpc;
1160
1161         if (stat & 0x00000001) {
1162                 gf100_gr_trap_gpc_rop(gr, gpc);
1163                 stat &= ~0x00000001;
1164         }
1165
1166         if (stat & 0x00000002) {
1167                 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));
1168                 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap);
1169                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1170                 stat &= ~0x00000002;
1171         }
1172
1173         if (stat & 0x00000004) {
1174                 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));
1175                 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap);
1176                 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1177                 stat &= ~0x00000004;
1178         }
1179
1180         if (stat & 0x00000008) {
1181                 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));
1182                 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap);
1183                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
1184                 stat &= ~0x00000009;
1185         }
1186
1187         for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
1188                 u32 mask = 0x00010000 << tpc;
1189                 if (stat & mask) {
1190                         gf100_gr_trap_tpc(gr, gpc, tpc);
1191                         nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask);
1192                         stat &= ~mask;
1193                 }
1194         }
1195
1196         if (stat) {
1197                 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat);
1198         }
1199 }
1200
1201 static void
1202 gf100_gr_trap_intr(struct gf100_gr *gr)
1203 {
1204         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1205         struct nvkm_device *device = subdev->device;
1206         char error[128];
1207         u32 trap = nvkm_rd32(device, 0x400108);
1208         int rop, gpc;
1209
1210         if (trap & 0x00000001) {
1211                 u32 stat = nvkm_rd32(device, 0x404000);
1212
1213                 nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error,
1214                                stat & 0x3fffffff);
1215                 nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error);
1216                 nvkm_wr32(device, 0x404000, 0xc0000000);
1217                 nvkm_wr32(device, 0x400108, 0x00000001);
1218                 trap &= ~0x00000001;
1219         }
1220
1221         if (trap & 0x00000002) {
1222                 u32 stat = nvkm_rd32(device, 0x404600);
1223
1224                 nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error,
1225                                stat & 0x3fffffff);
1226                 nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error);
1227
1228                 nvkm_wr32(device, 0x404600, 0xc0000000);
1229                 nvkm_wr32(device, 0x400108, 0x00000002);
1230                 trap &= ~0x00000002;
1231         }
1232
1233         if (trap & 0x00000008) {
1234                 u32 stat = nvkm_rd32(device, 0x408030);
1235
1236                 nvkm_snprintbf(error, sizeof(error), gf100_ccache_error,
1237                                stat & 0x3fffffff);
1238                 nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error);
1239                 nvkm_wr32(device, 0x408030, 0xc0000000);
1240                 nvkm_wr32(device, 0x400108, 0x00000008);
1241                 trap &= ~0x00000008;
1242         }
1243
1244         if (trap & 0x00000010) {
1245                 u32 stat = nvkm_rd32(device, 0x405840);
1246                 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n",
1247                            stat, stat & 0xffffff, (stat >> 24) & 0x3f);
1248                 nvkm_wr32(device, 0x405840, 0xc0000000);
1249                 nvkm_wr32(device, 0x400108, 0x00000010);
1250                 trap &= ~0x00000010;
1251         }
1252
1253         if (trap & 0x00000040) {
1254                 u32 stat = nvkm_rd32(device, 0x40601c);
1255
1256                 nvkm_snprintbf(error, sizeof(error), gf100_unk6_error,
1257                                stat & 0x3fffffff);
1258                 nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error);
1259
1260                 nvkm_wr32(device, 0x40601c, 0xc0000000);
1261                 nvkm_wr32(device, 0x400108, 0x00000040);
1262                 trap &= ~0x00000040;
1263         }
1264
1265         if (trap & 0x00000080) {
1266                 u32 stat = nvkm_rd32(device, 0x404490);
1267                 u32 pc = nvkm_rd32(device, 0x404494);
1268                 u32 op = nvkm_rd32(device, 0x40449c);
1269
1270                 nvkm_snprintbf(error, sizeof(error), gf100_macro_error,
1271                                stat & 0x1fffffff);
1272                 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n",
1273                            stat, error, pc & 0x7ff,
1274                            (pc & 0x10000000) ? "" : " (invalid)",
1275                            op);
1276
1277                 nvkm_wr32(device, 0x404490, 0xc0000000);
1278                 nvkm_wr32(device, 0x400108, 0x00000080);
1279                 trap &= ~0x00000080;
1280         }
1281
1282         if (trap & 0x00000100) {
1283                 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;
1284
1285                 nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat);
1286                 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error);
1287
1288                 if (stat)
1289                         nvkm_wr32(device, 0x407020, 0x40000000);
1290                 nvkm_wr32(device, 0x400108, 0x00000100);
1291                 trap &= ~0x00000100;
1292         }
1293
1294         if (trap & 0x01000000) {
1295                 u32 stat = nvkm_rd32(device, 0x400118);
1296                 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) {
1297                         u32 mask = 0x00000001 << gpc;
1298                         if (stat & mask) {
1299                                 gf100_gr_trap_gpc(gr, gpc);
1300                                 nvkm_wr32(device, 0x400118, mask);
1301                                 stat &= ~mask;
1302                         }
1303                 }
1304                 nvkm_wr32(device, 0x400108, 0x01000000);
1305                 trap &= ~0x01000000;
1306         }
1307
1308         if (trap & 0x02000000) {
1309                 for (rop = 0; rop < gr->rop_nr; rop++) {
1310                         u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));
1311                         u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));
1312                         nvkm_error(subdev, "ROP%d %08x %08x\n",
1313                                  rop, statz, statc);
1314                         nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
1315                         nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
1316                 }
1317                 nvkm_wr32(device, 0x400108, 0x02000000);
1318                 trap &= ~0x02000000;
1319         }
1320
1321         if (trap) {
1322                 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap);
1323                 nvkm_wr32(device, 0x400108, trap);
1324         }
1325 }
1326
1327 static void
1328 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
1329 {
1330         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1331         struct nvkm_device *device = subdev->device;
1332         nvkm_error(subdev, "%06x - done %08x\n", base,
1333                    nvkm_rd32(device, base + 0x400));
1334         nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1335                    nvkm_rd32(device, base + 0x800),
1336                    nvkm_rd32(device, base + 0x804),
1337                    nvkm_rd32(device, base + 0x808),
1338                    nvkm_rd32(device, base + 0x80c));
1339         nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1340                    nvkm_rd32(device, base + 0x810),
1341                    nvkm_rd32(device, base + 0x814),
1342                    nvkm_rd32(device, base + 0x818),
1343                    nvkm_rd32(device, base + 0x81c));
1344 }
1345
1346 void
1347 gf100_gr_ctxctl_debug(struct gf100_gr *gr)
1348 {
1349         struct nvkm_device *device = gr->base.engine.subdev.device;
1350         u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff;
1351         u32 gpc;
1352
1353         gf100_gr_ctxctl_debug_unit(gr, 0x409000);
1354         for (gpc = 0; gpc < gpcnr; gpc++)
1355                 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000));
1356 }
1357
1358 static void
1359 gf100_gr_ctxctl_isr(struct gf100_gr *gr)
1360 {
1361         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1362         struct nvkm_device *device = subdev->device;
1363         u32 stat = nvkm_rd32(device, 0x409c18);
1364
1365         if (!gr->firmware && (stat & 0x00000001)) {
1366                 u32 code = nvkm_rd32(device, 0x409814);
1367                 if (code == E_BAD_FWMTHD) {
1368                         u32 class = nvkm_rd32(device, 0x409808);
1369                         u32  addr = nvkm_rd32(device, 0x40980c);
1370                         u32  subc = (addr & 0x00070000) >> 16;
1371                         u32  mthd = (addr & 0x00003ffc);
1372                         u32  data = nvkm_rd32(device, 0x409810);
1373
1374                         nvkm_error(subdev, "FECS MTHD subc %d class %04x "
1375                                            "mthd %04x data %08x\n",
1376                                    subc, class, mthd, data);
1377                 } else {
1378                         nvkm_error(subdev, "FECS ucode error %d\n", code);
1379                 }
1380                 nvkm_wr32(device, 0x409c20, 0x00000001);
1381                 stat &= ~0x00000001;
1382         }
1383
1384         if (!gr->firmware && (stat & 0x00080000)) {
1385                 nvkm_error(subdev, "FECS watchdog timeout\n");
1386                 gf100_gr_ctxctl_debug(gr);
1387                 nvkm_wr32(device, 0x409c20, 0x00080000);
1388                 stat &= ~0x00080000;
1389         }
1390
1391         if (stat) {
1392                 nvkm_error(subdev, "FECS %08x\n", stat);
1393                 gf100_gr_ctxctl_debug(gr);
1394                 nvkm_wr32(device, 0x409c20, stat);
1395         }
1396 }
1397
1398 static void
1399 gf100_gr_intr(struct nvkm_gr *base)
1400 {
1401         struct gf100_gr *gr = gf100_gr(base);
1402         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1403         struct nvkm_device *device = subdev->device;
1404         struct nvkm_fifo_chan *chan;
1405         unsigned long flags;
1406         u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;
1407         u32 stat = nvkm_rd32(device, 0x400100);
1408         u32 addr = nvkm_rd32(device, 0x400704);
1409         u32 mthd = (addr & 0x00003ffc);
1410         u32 subc = (addr & 0x00070000) >> 16;
1411         u32 data = nvkm_rd32(device, 0x400708);
1412         u32 code = nvkm_rd32(device, 0x400110);
1413         u32 class;
1414         const char *name = "unknown";
1415         int chid = -1;
1416
1417         chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags);
1418         if (chan) {
1419                 name = chan->object.client->name;
1420                 chid = chan->chid;
1421         }
1422
1423         if (device->card_type < NV_E0 || subc < 4)
1424                 class = nvkm_rd32(device, 0x404200 + (subc * 4));
1425         else
1426                 class = 0x0000;
1427
1428         if (stat & 0x00000001) {
1429                 /*
1430                  * notifier interrupt, only needed for cyclestats
1431                  * can be safely ignored
1432                  */
1433                 nvkm_wr32(device, 0x400100, 0x00000001);
1434                 stat &= ~0x00000001;
1435         }
1436
1437         if (stat & 0x00000010) {
1438                 if (!gf100_gr_mthd_sw(device, class, mthd, data)) {
1439                         nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] "
1440                                    "subc %d class %04x mthd %04x data %08x\n",
1441                                    chid, inst << 12, name, subc,
1442                                    class, mthd, data);
1443                 }
1444                 nvkm_wr32(device, 0x400100, 0x00000010);
1445                 stat &= ~0x00000010;
1446         }
1447
1448         if (stat & 0x00000020) {
1449                 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] "
1450                            "subc %d class %04x mthd %04x data %08x\n",
1451                            chid, inst << 12, name, subc, class, mthd, data);
1452                 nvkm_wr32(device, 0x400100, 0x00000020);
1453                 stat &= ~0x00000020;
1454         }
1455
1456         if (stat & 0x00100000) {
1457                 const struct nvkm_enum *en =
1458                         nvkm_enum_find(nv50_data_error_names, code);
1459                 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] "
1460                                    "subc %d class %04x mthd %04x data %08x\n",
1461                            code, en ? en->name : "", chid, inst << 12,
1462                            name, subc, class, mthd, data);
1463                 nvkm_wr32(device, 0x400100, 0x00100000);
1464                 stat &= ~0x00100000;
1465         }
1466
1467         if (stat & 0x00200000) {
1468                 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n",
1469                            chid, inst << 12, name);
1470                 gf100_gr_trap_intr(gr);
1471                 nvkm_wr32(device, 0x400100, 0x00200000);
1472                 stat &= ~0x00200000;
1473         }
1474
1475         if (stat & 0x00080000) {
1476                 gf100_gr_ctxctl_isr(gr);
1477                 nvkm_wr32(device, 0x400100, 0x00080000);
1478                 stat &= ~0x00080000;
1479         }
1480
1481         if (stat) {
1482                 nvkm_error(subdev, "intr %08x\n", stat);
1483                 nvkm_wr32(device, 0x400100, stat);
1484         }
1485
1486         nvkm_wr32(device, 0x400500, 0x00010001);
1487         nvkm_fifo_chan_put(device->fifo, flags, &chan);
1488 }
1489
1490 static void
1491 gf100_gr_init_fw(struct nvkm_falcon *falcon,
1492                  struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
1493 {
1494         nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0);
1495         nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false);
1496 }
1497
1498 static void
1499 gf100_gr_init_csdata(struct gf100_gr *gr,
1500                      const struct gf100_gr_pack *pack,
1501                      u32 falcon, u32 starstar, u32 base)
1502 {
1503         struct nvkm_device *device = gr->base.engine.subdev.device;
1504         const struct gf100_gr_pack *iter;
1505         const struct gf100_gr_init *init;
1506         u32 addr = ~0, prev = ~0, xfer = 0;
1507         u32 star, temp;
1508
1509         nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);
1510         star = nvkm_rd32(device, falcon + 0x01c4);
1511         temp = nvkm_rd32(device, falcon + 0x01c4);
1512         if (temp > star)
1513                 star = temp;
1514         nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);
1515
1516         pack_for_each_init(init, iter, pack) {
1517                 u32 head = init->addr - base;
1518                 u32 tail = head + init->count * init->pitch;
1519                 while (head < tail) {
1520                         if (head != prev + 4 || xfer >= 32) {
1521                                 if (xfer) {
1522                                         u32 data = ((--xfer << 26) | addr);
1523                                         nvkm_wr32(device, falcon + 0x01c4, data);
1524                                         star += 4;
1525                                 }
1526                                 addr = head;
1527                                 xfer = 0;
1528                         }
1529                         prev = head;
1530                         xfer = xfer + 1;
1531                         head = head + init->pitch;
1532                 }
1533         }
1534
1535         nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);
1536         nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);
1537         nvkm_wr32(device, falcon + 0x01c4, star + 4);
1538 }
1539
1540 /* Initialize context from an external (secure or not) firmware */
1541 static int
1542 gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
1543 {
1544         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1545         struct nvkm_device *device = subdev->device;
1546         struct nvkm_secboot *sb = device->secboot;
1547         u32 secboot_mask = 0;
1548         int ret;
1549
1550         /* load fuc microcode */
1551         nvkm_mc_unk260(device, 0);
1552
1553         /* securely-managed falcons must be reset using secure boot */
1554         if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
1555                 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_FECS);
1556         else
1557                 gf100_gr_init_fw(gr->fecs, &gr->fuc409c, &gr->fuc409d);
1558
1559         if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
1560                 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_GPCCS);
1561         else
1562                 gf100_gr_init_fw(gr->gpccs, &gr->fuc41ac, &gr->fuc41ad);
1563
1564         if (secboot_mask != 0) {
1565                 int ret = nvkm_secboot_reset(sb, secboot_mask);
1566                 if (ret)
1567                         return ret;
1568         }
1569
1570         nvkm_mc_unk260(device, 1);
1571
1572         /* start both of them running */
1573         nvkm_wr32(device, 0x409840, 0xffffffff);
1574         nvkm_wr32(device, 0x41a10c, 0x00000000);
1575         nvkm_wr32(device, 0x40910c, 0x00000000);
1576
1577         nvkm_falcon_start(gr->gpccs);
1578         nvkm_falcon_start(gr->fecs);
1579
1580         if (nvkm_msec(device, 2000,
1581                 if (nvkm_rd32(device, 0x409800) & 0x00000001)
1582                         break;
1583         ) < 0)
1584                 return -EBUSY;
1585
1586         gf100_gr_fecs_set_watchdog_timeout(gr, 0x7fffffff);
1587
1588         /* Determine how much memory is required to store main context image. */
1589         ret = gf100_gr_fecs_discover_image_size(gr, &gr->size);
1590         if (ret)
1591                 return ret;
1592
1593         /* Determine how much memory is required to store ZCULL image. */
1594         ret = gf100_gr_fecs_discover_zcull_image_size(gr, &gr->size_zcull);
1595         if (ret)
1596                 return ret;
1597
1598         /* Determine how much memory is required to store PerfMon image. */
1599         ret = gf100_gr_fecs_discover_pm_image_size(gr, &gr->size_pm);
1600         if (ret)
1601                 return ret;
1602
1603         if (device->chipset >= 0xe0) {
1604                 nvkm_wr32(device, 0x409800, 0x00000000);
1605                 nvkm_wr32(device, 0x409500, 0x00000001);
1606                 nvkm_wr32(device, 0x409504, 0x00000030);
1607                 if (nvkm_msec(device, 2000,
1608                         if (nvkm_rd32(device, 0x409800))
1609                                 break;
1610                 ) < 0)
1611                         return -EBUSY;
1612
1613                 nvkm_wr32(device, 0x409810, 0xb00095c8);
1614                 nvkm_wr32(device, 0x409800, 0x00000000);
1615                 nvkm_wr32(device, 0x409500, 0x00000001);
1616                 nvkm_wr32(device, 0x409504, 0x00000031);
1617                 if (nvkm_msec(device, 2000,
1618                         if (nvkm_rd32(device, 0x409800))
1619                                 break;
1620                 ) < 0)
1621                         return -EBUSY;
1622
1623                 nvkm_wr32(device, 0x409810, 0x00080420);
1624                 nvkm_wr32(device, 0x409800, 0x00000000);
1625                 nvkm_wr32(device, 0x409500, 0x00000001);
1626                 nvkm_wr32(device, 0x409504, 0x00000032);
1627                 if (nvkm_msec(device, 2000,
1628                         if (nvkm_rd32(device, 0x409800))
1629                                 break;
1630                 ) < 0)
1631                         return -EBUSY;
1632
1633                 nvkm_wr32(device, 0x409614, 0x00000070);
1634                 nvkm_wr32(device, 0x409614, 0x00000770);
1635                 nvkm_wr32(device, 0x40802c, 0x00000001);
1636         }
1637
1638         if (gr->data == NULL) {
1639                 int ret = gf100_grctx_generate(gr);
1640                 if (ret) {
1641                         nvkm_error(subdev, "failed to construct context\n");
1642                         return ret;
1643                 }
1644         }
1645
1646         return 0;
1647 }
1648
1649 static int
1650 gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
1651 {
1652         const struct gf100_grctx_func *grctx = gr->func->grctx;
1653         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1654         struct nvkm_device *device = subdev->device;
1655
1656         if (!gr->func->fecs.ucode) {
1657                 return -ENOSYS;
1658         }
1659
1660         /* load HUB microcode */
1661         nvkm_mc_unk260(device, 0);
1662         nvkm_falcon_load_dmem(gr->fecs, gr->func->fecs.ucode->data.data, 0x0,
1663                               gr->func->fecs.ucode->data.size, 0);
1664         nvkm_falcon_load_imem(gr->fecs, gr->func->fecs.ucode->code.data, 0x0,
1665                               gr->func->fecs.ucode->code.size, 0, 0, false);
1666
1667         /* load GPC microcode */
1668         nvkm_falcon_load_dmem(gr->gpccs, gr->func->gpccs.ucode->data.data, 0x0,
1669                               gr->func->gpccs.ucode->data.size, 0);
1670         nvkm_falcon_load_imem(gr->gpccs, gr->func->gpccs.ucode->code.data, 0x0,
1671                               gr->func->gpccs.ucode->code.size, 0, 0, false);
1672         nvkm_mc_unk260(device, 1);
1673
1674         /* load register lists */
1675         gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000);
1676         gf100_gr_init_csdata(gr, grctx->gpc_0, 0x41a000, 0x000, 0x418000);
1677         gf100_gr_init_csdata(gr, grctx->gpc_1, 0x41a000, 0x000, 0x418000);
1678         gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800);
1679         gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00);
1680
1681         /* start HUB ucode running, it'll init the GPCs */
1682         nvkm_wr32(device, 0x40910c, 0x00000000);
1683         nvkm_wr32(device, 0x409100, 0x00000002);
1684         if (nvkm_msec(device, 2000,
1685                 if (nvkm_rd32(device, 0x409800) & 0x80000000)
1686                         break;
1687         ) < 0) {
1688                 gf100_gr_ctxctl_debug(gr);
1689                 return -EBUSY;
1690         }
1691
1692         gr->size = nvkm_rd32(device, 0x409804);
1693         if (gr->data == NULL) {
1694                 int ret = gf100_grctx_generate(gr);
1695                 if (ret) {
1696                         nvkm_error(subdev, "failed to construct context\n");
1697                         return ret;
1698                 }
1699         }
1700
1701         return 0;
1702 }
1703
1704 int
1705 gf100_gr_init_ctxctl(struct gf100_gr *gr)
1706 {
1707         int ret;
1708
1709         if (gr->firmware)
1710                 ret = gf100_gr_init_ctxctl_ext(gr);
1711         else
1712                 ret = gf100_gr_init_ctxctl_int(gr);
1713
1714         return ret;
1715 }
1716
1717 void
1718 gf100_gr_oneinit_sm_id(struct gf100_gr *gr)
1719 {
1720         int tpc, gpc;
1721         for (tpc = 0; tpc < gr->tpc_max; tpc++) {
1722                 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1723                         if (tpc < gr->tpc_nr[gpc]) {
1724                                 gr->sm[gr->sm_nr].gpc = gpc;
1725                                 gr->sm[gr->sm_nr].tpc = tpc;
1726                                 gr->sm_nr++;
1727                         }
1728                 }
1729         }
1730 }
1731
1732 void
1733 gf100_gr_oneinit_tiles(struct gf100_gr *gr)
1734 {
1735         static const u8 primes[] = {
1736                 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61
1737         };
1738         int init_frac[GPC_MAX], init_err[GPC_MAX], run_err[GPC_MAX], i, j;
1739         u32 mul_factor, comm_denom;
1740         u8  gpc_map[GPC_MAX];
1741         bool sorted;
1742
1743         switch (gr->tpc_total) {
1744         case 15: gr->screen_tile_row_offset = 0x06; break;
1745         case 14: gr->screen_tile_row_offset = 0x05; break;
1746         case 13: gr->screen_tile_row_offset = 0x02; break;
1747         case 11: gr->screen_tile_row_offset = 0x07; break;
1748         case 10: gr->screen_tile_row_offset = 0x06; break;
1749         case  7:
1750         case  5: gr->screen_tile_row_offset = 0x01; break;
1751         case  3: gr->screen_tile_row_offset = 0x02; break;
1752         case  2:
1753         case  1: gr->screen_tile_row_offset = 0x01; break;
1754         default: gr->screen_tile_row_offset = 0x03;
1755                 for (i = 0; i < ARRAY_SIZE(primes); i++) {
1756                         if (gr->tpc_total % primes[i]) {
1757                                 gr->screen_tile_row_offset = primes[i];
1758                                 break;
1759                         }
1760                 }
1761                 break;
1762         }
1763
1764         /* Sort GPCs by TPC count, highest-to-lowest. */
1765         for (i = 0; i < gr->gpc_nr; i++)
1766                 gpc_map[i] = i;
1767         sorted = false;
1768
1769         while (!sorted) {
1770                 for (sorted = true, i = 0; i < gr->gpc_nr - 1; i++) {
1771                         if (gr->tpc_nr[gpc_map[i + 1]] >
1772                             gr->tpc_nr[gpc_map[i + 0]]) {
1773                                 u8 swap = gpc_map[i];
1774                                 gpc_map[i + 0] = gpc_map[i + 1];
1775                                 gpc_map[i + 1] = swap;
1776                                 sorted = false;
1777                         }
1778                 }
1779         }
1780
1781         /* Determine tile->GPC mapping */
1782         mul_factor = gr->gpc_nr * gr->tpc_max;
1783         if (mul_factor & 1)
1784                 mul_factor = 2;
1785         else
1786                 mul_factor = 1;
1787
1788         comm_denom = gr->gpc_nr * gr->tpc_max * mul_factor;
1789
1790         for (i = 0; i < gr->gpc_nr; i++) {
1791                 init_frac[i] = gr->tpc_nr[gpc_map[i]] * gr->gpc_nr * mul_factor;
1792                  init_err[i] = i * gr->tpc_max * mul_factor - comm_denom/2;
1793                   run_err[i] = init_frac[i] + init_err[i];
1794         }
1795
1796         for (i = 0; i < gr->tpc_total;) {
1797                 for (j = 0; j < gr->gpc_nr; j++) {
1798                         if ((run_err[j] * 2) >= comm_denom) {
1799                                 gr->tile[i++] = gpc_map[j];
1800                                 run_err[j] += init_frac[j] - comm_denom;
1801                         } else {
1802                                 run_err[j] += init_frac[j];
1803                         }
1804                 }
1805         }
1806 }
1807
1808 static int
1809 gf100_gr_oneinit(struct nvkm_gr *base)
1810 {
1811         struct gf100_gr *gr = gf100_gr(base);
1812         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1813         struct nvkm_device *device = subdev->device;
1814         int i, j;
1815         int ret;
1816
1817         ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs);
1818         if (ret)
1819                 return ret;
1820
1821         ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs);
1822         if (ret)
1823                 return ret;
1824
1825         nvkm_pmu_pgob(device->pmu, false);
1826
1827         gr->rop_nr = gr->func->rops(gr);
1828         gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f;
1829         for (i = 0; i < gr->gpc_nr; i++) {
1830                 gr->tpc_nr[i]  = nvkm_rd32(device, GPC_UNIT(i, 0x2608));
1831                 gr->tpc_max = max(gr->tpc_max, gr->tpc_nr[i]);
1832                 gr->tpc_total += gr->tpc_nr[i];
1833                 gr->ppc_nr[i]  = gr->func->ppc_nr;
1834                 for (j = 0; j < gr->ppc_nr[i]; j++) {
1835                         gr->ppc_tpc_mask[i][j] =
1836                                 nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
1837                         if (gr->ppc_tpc_mask[i][j] == 0)
1838                                 continue;
1839                         gr->ppc_mask[i] |= (1 << j);
1840                         gr->ppc_tpc_nr[i][j] = hweight8(gr->ppc_tpc_mask[i][j]);
1841                         if (gr->ppc_tpc_min == 0 ||
1842                             gr->ppc_tpc_min > gr->ppc_tpc_nr[i][j])
1843                                 gr->ppc_tpc_min = gr->ppc_tpc_nr[i][j];
1844                         if (gr->ppc_tpc_max < gr->ppc_tpc_nr[i][j])
1845                                 gr->ppc_tpc_max = gr->ppc_tpc_nr[i][j];
1846                 }
1847         }
1848
1849         memset(gr->tile, 0xff, sizeof(gr->tile));
1850         gr->func->oneinit_tiles(gr);
1851         gr->func->oneinit_sm_id(gr);
1852         return 0;
1853 }
1854
1855 static int
1856 gf100_gr_init_(struct nvkm_gr *base)
1857 {
1858         struct gf100_gr *gr = gf100_gr(base);
1859         struct nvkm_subdev *subdev = &base->engine.subdev;
1860         u32 ret;
1861
1862         nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);
1863
1864         ret = nvkm_falcon_get(gr->fecs, subdev);
1865         if (ret)
1866                 return ret;
1867
1868         ret = nvkm_falcon_get(gr->gpccs, subdev);
1869         if (ret)
1870                 return ret;
1871
1872         return gr->func->init(gr);
1873 }
1874
1875 static int
1876 gf100_gr_fini_(struct nvkm_gr *base, bool suspend)
1877 {
1878         struct gf100_gr *gr = gf100_gr(base);
1879         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1880         nvkm_falcon_put(gr->gpccs, subdev);
1881         nvkm_falcon_put(gr->fecs, subdev);
1882         return 0;
1883 }
1884
1885 void
1886 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
1887 {
1888         kfree(fuc->data);
1889         fuc->data = NULL;
1890 }
1891
1892 static void
1893 gf100_gr_dtor_init(struct gf100_gr_pack *pack)
1894 {
1895         vfree(pack);
1896 }
1897
1898 void *
1899 gf100_gr_dtor(struct nvkm_gr *base)
1900 {
1901         struct gf100_gr *gr = gf100_gr(base);
1902
1903         if (gr->func->dtor)
1904                 gr->func->dtor(gr);
1905         kfree(gr->data);
1906
1907         nvkm_falcon_del(&gr->gpccs);
1908         nvkm_falcon_del(&gr->fecs);
1909
1910         gf100_gr_dtor_fw(&gr->fuc409c);
1911         gf100_gr_dtor_fw(&gr->fuc409d);
1912         gf100_gr_dtor_fw(&gr->fuc41ac);
1913         gf100_gr_dtor_fw(&gr->fuc41ad);
1914
1915         gf100_gr_dtor_init(gr->fuc_bundle);
1916         gf100_gr_dtor_init(gr->fuc_method);
1917         gf100_gr_dtor_init(gr->fuc_sw_ctx);
1918         gf100_gr_dtor_init(gr->fuc_sw_nonctx);
1919
1920         return gr;
1921 }
1922
1923 static const struct nvkm_gr_func
1924 gf100_gr_ = {
1925         .dtor = gf100_gr_dtor,
1926         .oneinit = gf100_gr_oneinit,
1927         .init = gf100_gr_init_,
1928         .fini = gf100_gr_fini_,
1929         .intr = gf100_gr_intr,
1930         .units = gf100_gr_units,
1931         .chan_new = gf100_gr_chan_new,
1932         .object_get = gf100_gr_object_get,
1933         .chsw_load = gf100_gr_chsw_load,
1934 };
1935
1936 int
1937 gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname,
1938                         struct gf100_gr_fuc *fuc, int ret)
1939 {
1940         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1941         struct nvkm_device *device = subdev->device;
1942         const struct firmware *fw;
1943         char f[32];
1944
1945         /* see if this firmware has a legacy path */
1946         if (!strcmp(fwname, "fecs_inst"))
1947                 fwname = "fuc409c";
1948         else if (!strcmp(fwname, "fecs_data"))
1949                 fwname = "fuc409d";
1950         else if (!strcmp(fwname, "gpccs_inst"))
1951                 fwname = "fuc41ac";
1952         else if (!strcmp(fwname, "gpccs_data"))
1953                 fwname = "fuc41ad";
1954         else {
1955                 /* nope, let's just return the error we got */
1956                 nvkm_error(subdev, "failed to load %s\n", fwname);
1957                 return ret;
1958         }
1959
1960         /* yes, try to load from the legacy path */
1961         nvkm_debug(subdev, "%s: falling back to legacy path\n", fwname);
1962
1963         snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
1964         ret = request_firmware(&fw, f, device->dev);
1965         if (ret) {
1966                 snprintf(f, sizeof(f), "nouveau/%s", fwname);
1967                 ret = request_firmware(&fw, f, device->dev);
1968                 if (ret) {
1969                         nvkm_error(subdev, "failed to load %s\n", fwname);
1970                         return ret;
1971                 }
1972         }
1973
1974         fuc->size = fw->size;
1975         fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
1976         release_firmware(fw);
1977         return (fuc->data != NULL) ? 0 : -ENOMEM;
1978 }
1979
1980 int
1981 gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
1982                  struct gf100_gr_fuc *fuc)
1983 {
1984         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1985         struct nvkm_device *device = subdev->device;
1986         const struct firmware *fw;
1987         int ret;
1988
1989         ret = nvkm_firmware_get(device, fwname, &fw);
1990         if (ret) {
1991                 ret = gf100_gr_ctor_fw_legacy(gr, fwname, fuc, ret);
1992                 if (ret)
1993                         return -ENODEV;
1994                 return 0;
1995         }
1996
1997         fuc->size = fw->size;
1998         fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
1999         nvkm_firmware_put(fw);
2000         return (fuc->data != NULL) ? 0 : -ENOMEM;
2001 }
2002
2003 int
2004 gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device,
2005               int index, struct gf100_gr *gr)
2006 {
2007         gr->func = func;
2008         gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW",
2009                                     func->fecs.ucode == NULL);
2010
2011         return nvkm_gr_ctor(&gf100_gr_, device, index,
2012                             gr->firmware || func->fecs.ucode != NULL,
2013                             &gr->base);
2014 }
2015
2016 int
2017 gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
2018               int index, struct nvkm_gr **pgr)
2019 {
2020         struct gf100_gr *gr;
2021         int ret;
2022
2023         if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
2024                 return -ENOMEM;
2025         *pgr = &gr->base;
2026
2027         ret = gf100_gr_ctor(func, device, index, gr);
2028         if (ret)
2029                 return ret;
2030
2031         if (gr->firmware) {
2032                 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
2033                     gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
2034                     gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||
2035                     gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
2036                         return -ENODEV;
2037         }
2038
2039         return 0;
2040 }
2041
2042 void
2043 gf100_gr_init_400054(struct gf100_gr *gr)
2044 {
2045         nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464);
2046 }
2047
2048 void
2049 gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
2050 {
2051         struct nvkm_device *device = gr->base.engine.subdev.device;
2052         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
2053         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
2054 }
2055
2056 void
2057 gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc)
2058 {
2059         struct nvkm_device *device = gr->base.engine.subdev.device;
2060         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
2061 }
2062
2063 void
2064 gf100_gr_init_419eb4(struct gf100_gr *gr)
2065 {
2066         struct nvkm_device *device = gr->base.engine.subdev.device;
2067         nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
2068 }
2069
2070 void
2071 gf100_gr_init_419cc0(struct gf100_gr *gr)
2072 {
2073         struct nvkm_device *device = gr->base.engine.subdev.device;
2074         int gpc, tpc;
2075
2076         nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
2077
2078         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
2079                 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++)
2080                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
2081         }
2082 }
2083
2084 void
2085 gf100_gr_init_40601c(struct gf100_gr *gr)
2086 {
2087         nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000);
2088 }
2089
2090 void
2091 gf100_gr_init_fecs_exceptions(struct gf100_gr *gr)
2092 {
2093         const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001;
2094         nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data);
2095 }
2096
2097 void
2098 gf100_gr_init_gpc_mmu(struct gf100_gr *gr)
2099 {
2100         struct nvkm_device *device = gr->base.engine.subdev.device;
2101         struct nvkm_fb *fb = device->fb;
2102
2103         nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001);
2104         nvkm_wr32(device, 0x4188a4, 0x03000000);
2105         nvkm_wr32(device, 0x418888, 0x00000000);
2106         nvkm_wr32(device, 0x41888c, 0x00000000);
2107         nvkm_wr32(device, 0x418890, 0x00000000);
2108         nvkm_wr32(device, 0x418894, 0x00000000);
2109         nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8);
2110         nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8);
2111 }
2112
2113 void
2114 gf100_gr_init_num_active_ltcs(struct gf100_gr *gr)
2115 {
2116         struct nvkm_device *device = gr->base.engine.subdev.device;
2117         nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
2118 }
2119
2120 void
2121 gf100_gr_init_zcull(struct gf100_gr *gr)
2122 {
2123         struct nvkm_device *device = gr->base.engine.subdev.device;
2124         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
2125         const u8 tile_nr = ALIGN(gr->tpc_total, 32);
2126         u8 bank[GPC_MAX] = {}, gpc, i, j;
2127         u32 data;
2128
2129         for (i = 0; i < tile_nr; i += 8) {
2130                 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
2131                         data |= bank[gr->tile[i + j]] << (j * 4);
2132                         bank[gr->tile[i + j]]++;
2133                 }
2134                 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
2135         }
2136
2137         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
2138                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
2139                           gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
2140                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
2141                                                          gr->tpc_total);
2142                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
2143         }
2144
2145         nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);
2146 }
2147
2148 void
2149 gf100_gr_init_vsc_stream_master(struct gf100_gr *gr)
2150 {
2151         struct nvkm_device *device = gr->base.engine.subdev.device;
2152         nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001);
2153 }
2154
2155 int
2156 gf100_gr_init(struct gf100_gr *gr)
2157 {
2158         struct nvkm_device *device = gr->base.engine.subdev.device;
2159         int gpc, tpc, rop;
2160
2161         if (gr->func->init_419bd8)
2162                 gr->func->init_419bd8(gr);
2163
2164         gr->func->init_gpc_mmu(gr);
2165
2166         if (gr->fuc_sw_nonctx)
2167                 gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
2168         else
2169                 gf100_gr_mmio(gr, gr->func->mmio);
2170
2171         gf100_gr_wait_idle(gr);
2172
2173         if (gr->func->init_r405a14)
2174                 gr->func->init_r405a14(gr);
2175
2176         if (gr->func->clkgate_pack)
2177                 nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack);
2178
2179         if (gr->func->init_bios)
2180                 gr->func->init_bios(gr);
2181
2182         gr->func->init_vsc_stream_master(gr);
2183         gr->func->init_zcull(gr);
2184         gr->func->init_num_active_ltcs(gr);
2185         if (gr->func->init_rop_active_fbps)
2186                 gr->func->init_rop_active_fbps(gr);
2187         if (gr->func->init_bios_2)
2188                 gr->func->init_bios_2(gr);
2189         if (gr->func->init_swdx_pes_mask)
2190                 gr->func->init_swdx_pes_mask(gr);
2191
2192         nvkm_wr32(device, 0x400500, 0x00010001);
2193
2194         nvkm_wr32(device, 0x400100, 0xffffffff);
2195         nvkm_wr32(device, 0x40013c, 0xffffffff);
2196         nvkm_wr32(device, 0x400124, 0x00000002);
2197
2198         gr->func->init_fecs_exceptions(gr);
2199         if (gr->func->init_ds_hww_esr_2)
2200                 gr->func->init_ds_hww_esr_2(gr);
2201
2202         nvkm_wr32(device, 0x404000, 0xc0000000);
2203         nvkm_wr32(device, 0x404600, 0xc0000000);
2204         nvkm_wr32(device, 0x408030, 0xc0000000);
2205
2206         if (gr->func->init_40601c)
2207                 gr->func->init_40601c(gr);
2208
2209         nvkm_wr32(device, 0x404490, 0xc0000000);
2210         nvkm_wr32(device, 0x406018, 0xc0000000);
2211
2212         if (gr->func->init_sked_hww_esr)
2213                 gr->func->init_sked_hww_esr(gr);
2214
2215         nvkm_wr32(device, 0x405840, 0xc0000000);
2216         nvkm_wr32(device, 0x405844, 0x00ffffff);
2217
2218         if (gr->func->init_419cc0)
2219                 gr->func->init_419cc0(gr);
2220         if (gr->func->init_419eb4)
2221                 gr->func->init_419eb4(gr);
2222         if (gr->func->init_419c9c)
2223                 gr->func->init_419c9c(gr);
2224
2225         if (gr->func->init_ppc_exceptions)
2226                 gr->func->init_ppc_exceptions(gr);
2227
2228         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
2229                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
2230                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
2231                 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
2232                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
2233                 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
2234                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
2235                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
2236                         if (gr->func->init_tex_hww_esr)
2237                                 gr->func->init_tex_hww_esr(gr, gpc, tpc);
2238                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
2239                         if (gr->func->init_504430)
2240                                 gr->func->init_504430(gr, gpc, tpc);
2241                         gr->func->init_shader_exceptions(gr, gpc, tpc);
2242                 }
2243                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
2244                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
2245         }
2246
2247         for (rop = 0; rop < gr->rop_nr; rop++) {
2248                 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
2249                 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
2250                 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
2251                 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
2252         }
2253
2254         nvkm_wr32(device, 0x400108, 0xffffffff);
2255         nvkm_wr32(device, 0x400138, 0xffffffff);
2256         nvkm_wr32(device, 0x400118, 0xffffffff);
2257         nvkm_wr32(device, 0x400130, 0xffffffff);
2258         nvkm_wr32(device, 0x40011c, 0xffffffff);
2259         nvkm_wr32(device, 0x400134, 0xffffffff);
2260
2261         if (gr->func->init_400054)
2262                 gr->func->init_400054(gr);
2263
2264         gf100_gr_zbc_init(gr);
2265
2266         if (gr->func->init_4188a4)
2267                 gr->func->init_4188a4(gr);
2268
2269         return gf100_gr_init_ctxctl(gr);
2270 }
2271
2272 #include "fuc/hubgf100.fuc3.h"
2273
2274 struct gf100_gr_ucode
2275 gf100_gr_fecs_ucode = {
2276         .code.data = gf100_grhub_code,
2277         .code.size = sizeof(gf100_grhub_code),
2278         .data.data = gf100_grhub_data,
2279         .data.size = sizeof(gf100_grhub_data),
2280 };
2281
2282 #include "fuc/gpcgf100.fuc3.h"
2283
2284 struct gf100_gr_ucode
2285 gf100_gr_gpccs_ucode = {
2286         .code.data = gf100_grgpc_code,
2287         .code.size = sizeof(gf100_grgpc_code),
2288         .data.data = gf100_grgpc_data,
2289         .data.size = sizeof(gf100_grgpc_data),
2290 };
2291
2292 static const struct gf100_gr_func
2293 gf100_gr = {
2294         .oneinit_tiles = gf100_gr_oneinit_tiles,
2295         .oneinit_sm_id = gf100_gr_oneinit_sm_id,
2296         .init = gf100_gr_init,
2297         .init_gpc_mmu = gf100_gr_init_gpc_mmu,
2298         .init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
2299         .init_zcull = gf100_gr_init_zcull,
2300         .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
2301         .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
2302         .init_40601c = gf100_gr_init_40601c,
2303         .init_419cc0 = gf100_gr_init_419cc0,
2304         .init_419eb4 = gf100_gr_init_419eb4,
2305         .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
2306         .init_shader_exceptions = gf100_gr_init_shader_exceptions,
2307         .init_400054 = gf100_gr_init_400054,
2308         .trap_mp = gf100_gr_trap_mp,
2309         .mmio = gf100_gr_pack_mmio,
2310         .fecs.ucode = &gf100_gr_fecs_ucode,
2311         .gpccs.ucode = &gf100_gr_gpccs_ucode,
2312         .rops = gf100_gr_rops,
2313         .grctx = &gf100_grctx,
2314         .zbc = &gf100_gr_zbc,
2315         .sclass = {
2316                 { -1, -1, FERMI_TWOD_A },
2317                 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
2318                 { -1, -1, FERMI_A, &gf100_fermi },
2319                 { -1, -1, FERMI_COMPUTE_A },
2320                 {}
2321         }
2322 };
2323
2324 int
2325 gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
2326 {
2327         return gf100_gr_new_(&gf100_gr, device, index, pgr);
2328 }