2 * Copyright 2019 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #include <core/firmware.h>
25 #include <core/memory.h>
26 #include <subdev/gsp.h>
27 #include <subdev/pmu.h>
28 #include <engine/sec2.h>
33 tu102_acr_init(struct nvkm_acr *acr)
35 int ret = nvkm_acr_hsf_boot(acr, "AHESASC");
39 return nvkm_acr_hsf_boot(acr, "ASB");
43 tu102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
45 struct nvkm_acr_lsfw *lsfw;
49 /*XXX: shared sub-WPR headers, fill terminator for now. */
50 nvkm_wo32(acr->wpr, 0x200, 0xffffffff);
52 /* Fill per-LSF structures. */
53 list_for_each_entry(lsfw, &acr->lsfw, head) {
54 struct lsf_signature_v1 *sig = (void *)lsfw->sig->data;
55 struct wpr_header_v1 hdr = {
56 .falcon_id = lsfw->id,
57 .lsb_offset = lsfw->offset.lsb,
58 .bootstrap_owner = NVKM_ACR_LSF_GSPLITE,
60 .bin_version = sig->version,
61 .status = WPR_HEADER_V1_STATUS_COPY,
64 /* Write WPR header. */
65 nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
66 offset += sizeof(hdr);
68 /* Write LSB header. */
69 ret = gp102_acr_wpr_build_lsb(acr, lsfw);
73 /* Write ucode image. */
74 nvkm_wobj(acr->wpr, lsfw->offset.img,
78 /* Write bootloader data. */
79 lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
83 nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID);
88 tu102_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
90 return gm200_acr_hsfw_boot(acr, hsf, 0, 0);
94 tu102_acr_hsfw_nofw(struct nvkm_acr *acr, const char *bl, const char *fw,
95 const char *name, int version,
96 const struct nvkm_acr_hsf_fwif *fwif)
101 MODULE_FIRMWARE("nvidia/tu102/acr/unload_bl.bin");
102 MODULE_FIRMWARE("nvidia/tu102/acr/ucode_unload.bin");
104 MODULE_FIRMWARE("nvidia/tu104/acr/unload_bl.bin");
105 MODULE_FIRMWARE("nvidia/tu104/acr/ucode_unload.bin");
107 MODULE_FIRMWARE("nvidia/tu106/acr/unload_bl.bin");
108 MODULE_FIRMWARE("nvidia/tu106/acr/ucode_unload.bin");
110 static const struct nvkm_acr_hsf_fwif
111 tu102_acr_unload_fwif[] = {
112 { 0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 },
113 { -1, tu102_acr_hsfw_nofw },
118 tu102_acr_asb_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
120 return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->gsp->falcon);
123 static const struct nvkm_acr_hsf_func
125 .load = tu102_acr_asb_load,
126 .boot = tu102_acr_hsfw_boot,
127 .bld = gp108_acr_hsfw_bld,
130 MODULE_FIRMWARE("nvidia/tu102/acr/ucode_asb.bin");
131 MODULE_FIRMWARE("nvidia/tu104/acr/ucode_asb.bin");
132 MODULE_FIRMWARE("nvidia/tu106/acr/ucode_asb.bin");
134 static const struct nvkm_acr_hsf_fwif
135 tu102_acr_asb_fwif[] = {
136 { 0, nvkm_acr_hsfw_load, &tu102_acr_asb_0 },
137 { -1, tu102_acr_hsfw_nofw },
141 static const struct nvkm_acr_hsf_func
142 tu102_acr_ahesasc_0 = {
143 .load = gp102_acr_load_load,
144 .boot = tu102_acr_hsfw_boot,
145 .bld = gp108_acr_hsfw_bld,
148 MODULE_FIRMWARE("nvidia/tu102/acr/bl.bin");
149 MODULE_FIRMWARE("nvidia/tu102/acr/ucode_ahesasc.bin");
151 MODULE_FIRMWARE("nvidia/tu104/acr/bl.bin");
152 MODULE_FIRMWARE("nvidia/tu104/acr/ucode_ahesasc.bin");
154 MODULE_FIRMWARE("nvidia/tu106/acr/bl.bin");
155 MODULE_FIRMWARE("nvidia/tu106/acr/ucode_ahesasc.bin");
157 static const struct nvkm_acr_hsf_fwif
158 tu102_acr_ahesasc_fwif[] = {
159 { 0, nvkm_acr_hsfw_load, &tu102_acr_ahesasc_0 },
160 { -1, tu102_acr_hsfw_nofw },
164 static const struct nvkm_acr_func
166 .ahesasc = tu102_acr_ahesasc_fwif,
167 .asb = tu102_acr_asb_fwif,
168 .unload = tu102_acr_unload_fwif,
169 .wpr_parse = gp102_acr_wpr_parse,
170 .wpr_layout = gp102_acr_wpr_layout,
171 .wpr_alloc = gp102_acr_wpr_alloc,
172 .wpr_patch = gp102_acr_wpr_patch,
173 .wpr_build = tu102_acr_wpr_build,
174 .wpr_check = gm200_acr_wpr_check,
175 .init = tu102_acr_init,
179 tu102_acr_load(struct nvkm_acr *acr, int version,
180 const struct nvkm_acr_fwif *fwif)
182 struct nvkm_subdev *subdev = &acr->subdev;
183 const struct nvkm_acr_hsf_fwif *hsfwif;
185 hsfwif = nvkm_firmware_load(subdev, fwif->func->ahesasc, "AcrAHESASC",
186 acr, "acr/bl", "acr/ucode_ahesasc",
189 return PTR_ERR(hsfwif);
191 hsfwif = nvkm_firmware_load(subdev, fwif->func->asb, "AcrASB",
192 acr, "acr/bl", "acr/ucode_asb", "ASB");
194 return PTR_ERR(hsfwif);
196 hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
197 acr, "acr/unload_bl", "acr/ucode_unload",
200 return PTR_ERR(hsfwif);
205 static const struct nvkm_acr_fwif
207 { 0, tu102_acr_load, &tu102_acr },
212 tu102_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr)
214 return nvkm_acr_new_(tu102_acr_fwif, device, index, pacr);