2 * Toppoly TD028TTEC1 panel support
4 * Copyright (C) 2008 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
7 * Neo 1973 code (jbt6k74.c):
8 * Copyright (C) 2006-2007 by OpenMoko, Inc.
9 * Author: Harald Welte <laforge@openmoko.org>
11 * Ported and adapted from Neo 1973 U-Boot by:
12 * H. Nikolaus Schaller <hns@goldelico.com>
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published by
16 * the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
23 * You should have received a copy of the GNU General Public License along with
24 * this program. If not, see <http://www.gnu.org/licenses/>.
27 #include <linux/module.h>
28 #include <linux/delay.h>
29 #include <linux/spi/spi.h>
31 #include "../dss/omapdss.h"
33 struct panel_drv_data {
34 struct omap_dss_device dssdev;
38 struct spi_device *spi_dev;
41 static const struct videomode td028ttec1_panel_vm = {
44 .pixelclock = 22153000,
52 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
55 #define JBT_COMMAND 0x000
56 #define JBT_DATA 0x100
58 static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
61 u16 tx_buf = JBT_COMMAND | reg;
63 rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
66 dev_err(&ddata->spi_dev->dev,
67 "jbt_ret_write_0 spi_write ret %d\n", rc);
72 static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
77 tx_buf[0] = JBT_COMMAND | reg;
78 tx_buf[1] = JBT_DATA | data;
79 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
82 dev_err(&ddata->spi_dev->dev,
83 "jbt_reg_write_1 spi_write ret %d\n", rc);
88 static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
93 tx_buf[0] = JBT_COMMAND | reg;
94 tx_buf[1] = JBT_DATA | (data >> 8);
95 tx_buf[2] = JBT_DATA | (data & 0xff);
97 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
101 dev_err(&ddata->spi_dev->dev,
102 "jbt_reg_write_2 spi_write ret %d\n", rc);
108 JBT_REG_SLEEP_IN = 0x10,
109 JBT_REG_SLEEP_OUT = 0x11,
111 JBT_REG_DISPLAY_OFF = 0x28,
112 JBT_REG_DISPLAY_ON = 0x29,
114 JBT_REG_RGB_FORMAT = 0x3a,
115 JBT_REG_QUAD_RATE = 0x3b,
117 JBT_REG_POWER_ON_OFF = 0xb0,
118 JBT_REG_BOOSTER_OP = 0xb1,
119 JBT_REG_BOOSTER_MODE = 0xb2,
120 JBT_REG_BOOSTER_FREQ = 0xb3,
121 JBT_REG_OPAMP_SYSCLK = 0xb4,
122 JBT_REG_VSC_VOLTAGE = 0xb5,
123 JBT_REG_VCOM_VOLTAGE = 0xb6,
124 JBT_REG_EXT_DISPL = 0xb7,
125 JBT_REG_OUTPUT_CONTROL = 0xb8,
126 JBT_REG_DCCLK_DCEV = 0xb9,
127 JBT_REG_DISPLAY_MODE1 = 0xba,
128 JBT_REG_DISPLAY_MODE2 = 0xbb,
129 JBT_REG_DISPLAY_MODE = 0xbc,
130 JBT_REG_ASW_SLEW = 0xbd,
131 JBT_REG_DUMMY_DISPLAY = 0xbe,
132 JBT_REG_DRIVE_SYSTEM = 0xbf,
134 JBT_REG_SLEEP_OUT_FR_A = 0xc0,
135 JBT_REG_SLEEP_OUT_FR_B = 0xc1,
136 JBT_REG_SLEEP_OUT_FR_C = 0xc2,
137 JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
138 JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
139 JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
140 JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
142 JBT_REG_GAMMA1_FINE_1 = 0xc7,
143 JBT_REG_GAMMA1_FINE_2 = 0xc8,
144 JBT_REG_GAMMA1_INCLINATION = 0xc9,
145 JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
147 JBT_REG_BLANK_CONTROL = 0xcf,
148 JBT_REG_BLANK_TH_TV = 0xd0,
149 JBT_REG_CKV_ON_OFF = 0xd1,
150 JBT_REG_CKV_1_2 = 0xd2,
151 JBT_REG_OEV_TIMING = 0xd3,
152 JBT_REG_ASW_TIMING_1 = 0xd4,
153 JBT_REG_ASW_TIMING_2 = 0xd5,
155 JBT_REG_HCLOCK_VGA = 0xec,
156 JBT_REG_HCLOCK_QVGA = 0xed,
159 #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
161 static int td028ttec1_panel_connect(struct omap_dss_device *src,
162 struct omap_dss_device *dst)
167 static void td028ttec1_panel_disconnect(struct omap_dss_device *src,
168 struct omap_dss_device *dst)
172 static void td028ttec1_panel_enable(struct omap_dss_device *dssdev)
174 struct panel_drv_data *ddata = to_panel_data(dssdev);
177 dev_dbg(dssdev->dev, "%s: state %d\n", __func__, dssdev->state);
179 /* three times command zero */
180 r |= jbt_ret_write_0(ddata, 0x00);
181 usleep_range(1000, 2000);
182 r |= jbt_ret_write_0(ddata, 0x00);
183 usleep_range(1000, 2000);
184 r |= jbt_ret_write_0(ddata, 0x00);
185 usleep_range(1000, 2000);
188 dev_warn(dssdev->dev, "%s: transfer error\n", __func__);
192 /* deep standby out */
193 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
195 /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
196 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
199 r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
201 /* AVDD on, XVDD on */
202 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
205 r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
208 r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
210 /* at this point we have like 50% grey */
212 /* initialize register set */
213 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
214 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
215 r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
216 r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
217 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
218 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
219 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
220 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
221 r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
222 r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
223 r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
224 r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
225 r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
227 * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
228 * to avoid red / blue flicker
230 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
231 r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
233 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
234 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
235 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
236 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
237 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
238 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
239 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
241 r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
242 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
243 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
244 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
246 r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
247 r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
248 r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
250 r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
251 r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
253 r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
254 r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
255 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
257 r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
260 dev_err(dssdev->dev, "%s: write error\n", __func__);
263 static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
265 struct panel_drv_data *ddata = to_panel_data(dssdev);
267 dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
269 jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
270 jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
271 jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
272 jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
275 static int td028ttec1_panel_get_modes(struct omap_dss_device *dssdev,
276 struct drm_connector *connector)
278 struct panel_drv_data *ddata = to_panel_data(dssdev);
280 return omapdss_display_get_modes(connector, &ddata->vm);
283 static const struct omap_dss_device_ops td028ttec1_ops = {
284 .connect = td028ttec1_panel_connect,
285 .disconnect = td028ttec1_panel_disconnect,
287 .enable = td028ttec1_panel_enable,
288 .disable = td028ttec1_panel_disable,
290 .get_modes = td028ttec1_panel_get_modes,
293 static int td028ttec1_panel_probe(struct spi_device *spi)
295 struct panel_drv_data *ddata;
296 struct omap_dss_device *dssdev;
299 dev_dbg(&spi->dev, "%s\n", __func__);
301 spi->bits_per_word = 9;
302 spi->mode = SPI_MODE_3;
306 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
310 ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
314 dev_set_drvdata(&spi->dev, ddata);
316 ddata->spi_dev = spi;
318 ddata->vm = td028ttec1_panel_vm;
320 dssdev = &ddata->dssdev;
321 dssdev->dev = &spi->dev;
322 dssdev->ops = &td028ttec1_ops;
323 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
324 dssdev->display = true;
325 dssdev->owner = THIS_MODULE;
326 dssdev->of_ports = BIT(0);
327 dssdev->ops_flags = OMAP_DSS_DEVICE_OP_MODES;
330 * Note: According to the panel documentation:
331 * SYNC needs to be driven on the FALLING edge
333 dssdev->bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_SYNC_POSEDGE
334 | DRM_BUS_FLAG_PIXDATA_NEGEDGE;
336 omapdss_display_init(dssdev);
337 omapdss_device_register(dssdev);
342 static int td028ttec1_panel_remove(struct spi_device *spi)
344 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
345 struct omap_dss_device *dssdev = &ddata->dssdev;
347 dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
349 omapdss_device_unregister(dssdev);
351 td028ttec1_panel_disable(dssdev);
356 static const struct of_device_id td028ttec1_of_match[] = {
357 { .compatible = "omapdss,tpo,td028ttec1", },
358 /* keep to not break older DTB */
359 { .compatible = "omapdss,toppoly,td028ttec1", },
363 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
365 static const struct spi_device_id td028ttec1_ids[] = {
366 { "toppoly,td028ttec1", 0 },
367 { "tpo,td028ttec1", 0},
371 MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
374 static struct spi_driver td028ttec1_spi_driver = {
375 .probe = td028ttec1_panel_probe,
376 .remove = td028ttec1_panel_remove,
377 .id_table = td028ttec1_ids,
380 .name = "panel-tpo-td028ttec1",
381 .of_match_table = td028ttec1_of_match,
382 .suppress_bind_attrs = true,
386 module_spi_driver(td028ttec1_spi_driver);
388 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
389 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
390 MODULE_LICENSE("GPL");