drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c

   1 /*
   2  * Toppoly TD028TTEC1 panel support
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
   6  *
   7  * Neo 1973 code (jbt6k74.c):
   8  * Copyright (C) 2006-2007 by OpenMoko, Inc.
   9  * Author: Harald Welte <laforge@openmoko.org>
  10  *
  11  * Ported and adapted from Neo 1973 U-Boot by:
  12  * H. Nikolaus Schaller <hns@goldelico.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of the GNU General Public License version 2 as published by
  16  * the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  21  * more details.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program.  If not, see <http://www.gnu.org/licenses/>.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/delay.h>
  29 #include <linux/spi/spi.h>
  30
  31 #include "../dss/omapdss.h"
  32
  33 struct panel_drv_data {
  34         struct omap_dss_device dssdev;
  35
  36         struct videomode vm;
  37
  38         struct spi_device *spi_dev;
  39 };
  40
  41 static const struct videomode td028ttec1_panel_vm = {
  42         .hactive        = 480,
  43         .vactive        = 640,
  44         .pixelclock     = 22153000,
  45         .hfront_porch   = 24,
  46         .hsync_len      = 8,
  47         .hback_porch    = 8,
  48         .vfront_porch   = 4,
  49         .vsync_len      = 2,
  50         .vback_porch    = 2,
  51
  52         .flags          = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
  53 };
  54
  55 #define JBT_COMMAND     0x000
  56 #define JBT_DATA        0x100
  57
  58 static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
  59 {
  60         int rc;
  61         u16 tx_buf = JBT_COMMAND | reg;
  62
  63         rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
  64                         1*sizeof(u16));
  65         if (rc != 0)
  66                 dev_err(&ddata->spi_dev->dev,
  67                         "jbt_ret_write_0 spi_write ret %d\n", rc);
  68
  69         return rc;
  70 }
  71
  72 static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
  73 {
  74         int rc;
  75         u16 tx_buf[2];
  76
  77         tx_buf[0] = JBT_COMMAND | reg;
  78         tx_buf[1] = JBT_DATA | data;
  79         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
  80                         2*sizeof(u16));
  81         if (rc != 0)
  82                 dev_err(&ddata->spi_dev->dev,
  83                         "jbt_reg_write_1 spi_write ret %d\n", rc);
  84
  85         return rc;
  86 }
  87
  88 static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
  89 {
  90         int rc;
  91         u16 tx_buf[3];
  92
  93         tx_buf[0] = JBT_COMMAND | reg;
  94         tx_buf[1] = JBT_DATA | (data >> 8);
  95         tx_buf[2] = JBT_DATA | (data & 0xff);
  96
  97         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
  98                         3*sizeof(u16));
  99
 100         if (rc != 0)
 101                 dev_err(&ddata->spi_dev->dev,
 102                         "jbt_reg_write_2 spi_write ret %d\n", rc);
 103
 104         return rc;
 105 }
 106
 107 enum jbt_register {
 108         JBT_REG_SLEEP_IN                = 0x10,
 109         JBT_REG_SLEEP_OUT               = 0x11,
 110
 111         JBT_REG_DISPLAY_OFF             = 0x28,
 112         JBT_REG_DISPLAY_ON              = 0x29,
 113
 114         JBT_REG_RGB_FORMAT              = 0x3a,
 115         JBT_REG_QUAD_RATE               = 0x3b,
 116
 117         JBT_REG_POWER_ON_OFF            = 0xb0,
 118         JBT_REG_BOOSTER_OP              = 0xb1,
 119         JBT_REG_BOOSTER_MODE            = 0xb2,
 120         JBT_REG_BOOSTER_FREQ            = 0xb3,
 121         JBT_REG_OPAMP_SYSCLK            = 0xb4,
 122         JBT_REG_VSC_VOLTAGE             = 0xb5,
 123         JBT_REG_VCOM_VOLTAGE            = 0xb6,
 124         JBT_REG_EXT_DISPL               = 0xb7,
 125         JBT_REG_OUTPUT_CONTROL          = 0xb8,
 126         JBT_REG_DCCLK_DCEV              = 0xb9,
 127         JBT_REG_DISPLAY_MODE1           = 0xba,
 128         JBT_REG_DISPLAY_MODE2           = 0xbb,
 129         JBT_REG_DISPLAY_MODE            = 0xbc,
 130         JBT_REG_ASW_SLEW                = 0xbd,
 131         JBT_REG_DUMMY_DISPLAY           = 0xbe,
 132         JBT_REG_DRIVE_SYSTEM            = 0xbf,
 133
 134         JBT_REG_SLEEP_OUT_FR_A          = 0xc0,
 135         JBT_REG_SLEEP_OUT_FR_B          = 0xc1,
 136         JBT_REG_SLEEP_OUT_FR_C          = 0xc2,
 137         JBT_REG_SLEEP_IN_LCCNT_D        = 0xc3,
 138         JBT_REG_SLEEP_IN_LCCNT_E        = 0xc4,
 139         JBT_REG_SLEEP_IN_LCCNT_F        = 0xc5,
 140         JBT_REG_SLEEP_IN_LCCNT_G        = 0xc6,
 141
 142         JBT_REG_GAMMA1_FINE_1           = 0xc7,
 143         JBT_REG_GAMMA1_FINE_2           = 0xc8,
 144         JBT_REG_GAMMA1_INCLINATION      = 0xc9,
 145         JBT_REG_GAMMA1_BLUE_OFFSET      = 0xca,
 146
 147         JBT_REG_BLANK_CONTROL           = 0xcf,
 148         JBT_REG_BLANK_TH_TV             = 0xd0,
 149         JBT_REG_CKV_ON_OFF              = 0xd1,
 150         JBT_REG_CKV_1_2                 = 0xd2,
 151         JBT_REG_OEV_TIMING              = 0xd3,
 152         JBT_REG_ASW_TIMING_1            = 0xd4,
 153         JBT_REG_ASW_TIMING_2            = 0xd5,
 154
 155         JBT_REG_HCLOCK_VGA              = 0xec,
 156         JBT_REG_HCLOCK_QVGA             = 0xed,
 157 };
 158
 159 #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
 160
 161 static int td028ttec1_panel_connect(struct omap_dss_device *src,
 162                                     struct omap_dss_device *dst)
 163 {
 164         return 0;
 165 }
 166
 167 static void td028ttec1_panel_disconnect(struct omap_dss_device *src,
 168                                         struct omap_dss_device *dst)
 169 {
 170 }
 171
 172 static void td028ttec1_panel_enable(struct omap_dss_device *dssdev)
 173 {
 174         struct panel_drv_data *ddata = to_panel_data(dssdev);
 175         int r = 0;
 176
 177         dev_dbg(dssdev->dev, "%s: state %d\n", __func__, dssdev->state);
 178
 179         /* three times command zero */
 180         r |= jbt_ret_write_0(ddata, 0x00);
 181         usleep_range(1000, 2000);
 182         r |= jbt_ret_write_0(ddata, 0x00);
 183         usleep_range(1000, 2000);
 184         r |= jbt_ret_write_0(ddata, 0x00);
 185         usleep_range(1000, 2000);
 186
 187         if (r) {
 188                 dev_warn(dssdev->dev, "%s: transfer error\n", __func__);
 189                 return;
 190         }
 191
 192         /* deep standby out */
 193         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
 194
 195         /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
 196         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
 197
 198         /* Quad mode off */
 199         r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
 200
 201         /* AVDD on, XVDD on */
 202         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
 203
 204         /* Output control */
 205         r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
 206
 207         /* Sleep mode off */
 208         r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
 209
 210         /* at this point we have like 50% grey */
 211
 212         /* initialize register set */
 213         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
 214         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
 215         r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
 216         r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
 217         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
 218         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
 219         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 220         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 221         r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
 222         r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
 223         r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
 224         r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
 225         r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
 226         /*
 227          * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
 228          * to avoid red / blue flicker
 229          */
 230         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
 231         r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
 232
 233         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
 234         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
 235         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
 236         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
 237         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
 238         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
 239         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
 240
 241         r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
 242         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
 243         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
 244         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
 245
 246         r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
 247         r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
 248         r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
 249
 250         r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
 251         r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
 252
 253         r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
 254         r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
 255         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
 256
 257         r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
 258
 259         if (r)
 260                 dev_err(dssdev->dev, "%s: write error\n", __func__);
 261 }
 262
 263 static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
 264 {
 265         struct panel_drv_data *ddata = to_panel_data(dssdev);
 266
 267         dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
 268
 269         jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
 270         jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
 271         jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
 272         jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
 273 }
 274
 275 static int td028ttec1_panel_get_modes(struct omap_dss_device *dssdev,
 276                                       struct drm_connector *connector)
 277 {
 278         struct panel_drv_data *ddata = to_panel_data(dssdev);
 279
 280         return omapdss_display_get_modes(connector, &ddata->vm);
 281 }
 282
 283 static const struct omap_dss_device_ops td028ttec1_ops = {
 284         .connect        = td028ttec1_panel_connect,
 285         .disconnect     = td028ttec1_panel_disconnect,
 286
 287         .enable         = td028ttec1_panel_enable,
 288         .disable        = td028ttec1_panel_disable,
 289
 290         .get_modes      = td028ttec1_panel_get_modes,
 291 };
 292
 293 static int td028ttec1_panel_probe(struct spi_device *spi)
 294 {
 295         struct panel_drv_data *ddata;
 296         struct omap_dss_device *dssdev;
 297         int r;
 298
 299         dev_dbg(&spi->dev, "%s\n", __func__);
 300
 301         spi->bits_per_word = 9;
 302         spi->mode = SPI_MODE_3;
 303
 304         r = spi_setup(spi);
 305         if (r < 0) {
 306                 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
 307                 return r;
 308         }
 309
 310         ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
 311         if (ddata == NULL)
 312                 return -ENOMEM;
 313
 314         dev_set_drvdata(&spi->dev, ddata);
 315
 316         ddata->spi_dev = spi;
 317
 318         ddata->vm = td028ttec1_panel_vm;
 319
 320         dssdev = &ddata->dssdev;
 321         dssdev->dev = &spi->dev;
 322         dssdev->ops = &td028ttec1_ops;
 323         dssdev->type = OMAP_DISPLAY_TYPE_DPI;
 324         dssdev->display = true;
 325         dssdev->owner = THIS_MODULE;
 326         dssdev->of_ports = BIT(0);
 327         dssdev->ops_flags = OMAP_DSS_DEVICE_OP_MODES;
 328
 329         /*
 330          * Note: According to the panel documentation:
 331          * SYNC needs to be driven on the FALLING edge
 332          */
 333         dssdev->bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_SYNC_POSEDGE
 334                           | DRM_BUS_FLAG_PIXDATA_NEGEDGE;
 335
 336         omapdss_display_init(dssdev);
 337         omapdss_device_register(dssdev);
 338
 339         return 0;
 340 }
 341
 342 static int td028ttec1_panel_remove(struct spi_device *spi)
 343 {
 344         struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
 345         struct omap_dss_device *dssdev = &ddata->dssdev;
 346
 347         dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
 348
 349         omapdss_device_unregister(dssdev);
 350
 351         td028ttec1_panel_disable(dssdev);
 352
 353         return 0;
 354 }
 355
 356 static const struct of_device_id td028ttec1_of_match[] = {
 357         { .compatible = "omapdss,tpo,td028ttec1", },
 358         /* keep to not break older DTB */
 359         { .compatible = "omapdss,toppoly,td028ttec1", },
 360         {},
 361 };
 362
 363 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
 364
 365 static const struct spi_device_id td028ttec1_ids[] = {
 366         { "toppoly,td028ttec1", 0 },
 367         { "tpo,td028ttec1", 0},
 368         { /* sentinel */ }
 369 };
 370
 371 MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
 372
 373
 374 static struct spi_driver td028ttec1_spi_driver = {
 375         .probe          = td028ttec1_panel_probe,
 376         .remove         = td028ttec1_panel_remove,
 377         .id_table       = td028ttec1_ids,
 378
 379         .driver         = {
 380                 .name   = "panel-tpo-td028ttec1",
 381                 .of_match_table = td028ttec1_of_match,
 382                 .suppress_bind_attrs = true,
 383         },
 384 };
 385
 386 module_spi_driver(td028ttec1_spi_driver);
 387
 388 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
 389 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
 390 MODULE_LICENSE("GPL");