drivers/gpu/drm/omapdrm/dss/dispc.c

   1 /*
   2  * Copyright (C) 2009 Nokia Corporation
   3  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
   4  *
   5  * Some code and ideas taken from drivers/video/omap/ driver
   6  * by Imre Deak.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #define DSS_SUBSYS_NAME "DISPC"
  22
  23 #include <linux/kernel.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/export.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29 #include <linux/jiffies.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/delay.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/sizes.h>
  37 #include <linux/mfd/syscon.h>
  38 #include <linux/regmap.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41 #include <linux/component.h>
  42 #include <linux/sys_soc.h>
  43 #include <drm/drm_fourcc.h>
  44 #include <drm/drm_blend.h>
  45
  46 #include "omapdss.h"
  47 #include "dss.h"
  48 #include "dispc.h"
  49
  50 struct dispc_device;
  51
  52 /* DISPC */
  53 #define DISPC_SZ_REGS                   SZ_4K
  54
  55 enum omap_burst_size {
  56         BURST_SIZE_X2 = 0,
  57         BURST_SIZE_X4 = 1,
  58         BURST_SIZE_X8 = 2,
  59 };
  60
  61 #define REG_GET(dispc, idx, start, end) \
  62         FLD_GET(dispc_read_reg(dispc, idx), start, end)
  63
  64 #define REG_FLD_MOD(dispc, idx, val, start, end)                        \
  65         dispc_write_reg(dispc, idx, \
  66                         FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
  67
  68 /* DISPC has feature id */
  69 enum dispc_feature_id {
  70         FEAT_LCDENABLEPOL,
  71         FEAT_LCDENABLESIGNAL,
  72         FEAT_PCKFREEENABLE,
  73         FEAT_FUNCGATED,
  74         FEAT_MGR_LCD2,
  75         FEAT_MGR_LCD3,
  76         FEAT_LINEBUFFERSPLIT,
  77         FEAT_ROWREPEATENABLE,
  78         FEAT_RESIZECONF,
  79         /* Independent core clk divider */
  80         FEAT_CORE_CLK_DIV,
  81         FEAT_HANDLE_UV_SEPARATE,
  82         FEAT_ATTR2,
  83         FEAT_CPR,
  84         FEAT_PRELOAD,
  85         FEAT_FIR_COEF_V,
  86         FEAT_ALPHA_FIXED_ZORDER,
  87         FEAT_ALPHA_FREE_ZORDER,
  88         FEAT_FIFO_MERGE,
  89         /* An unknown HW bug causing the normal FIFO thresholds not to work */
  90         FEAT_OMAP3_DSI_FIFO_BUG,
  91         FEAT_BURST_2D,
  92         FEAT_MFLAG,
  93 };
  94
  95 struct dispc_features {
  96         u8 sw_start;
  97         u8 fp_start;
  98         u8 bp_start;
  99         u16 sw_max;
 100         u16 vp_max;
 101         u16 hp_max;
 102         u8 mgr_width_start;
 103         u8 mgr_height_start;
 104         u16 mgr_width_max;
 105         u16 mgr_height_max;
 106         unsigned long max_lcd_pclk;
 107         unsigned long max_tv_pclk;
 108         unsigned int max_downscale;
 109         unsigned int max_line_width;
 110         unsigned int min_pcd;
 111         int (*calc_scaling)(struct dispc_device *dispc,
 112                 unsigned long pclk, unsigned long lclk,
 113                 const struct videomode *vm,
 114                 u16 width, u16 height, u16 out_width, u16 out_height,
 115                 u32 fourcc, bool *five_taps,
 116                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
 117                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
 118         unsigned long (*calc_core_clk) (unsigned long pclk,
 119                 u16 width, u16 height, u16 out_width, u16 out_height,
 120                 bool mem_to_mem);
 121         u8 num_fifos;
 122         const enum dispc_feature_id *features;
 123         unsigned int num_features;
 124         const struct dss_reg_field *reg_fields;
 125         const unsigned int num_reg_fields;
 126         const enum omap_overlay_caps *overlay_caps;
 127         const u32 **supported_color_modes;
 128         unsigned int num_mgrs;
 129         unsigned int num_ovls;
 130         unsigned int buffer_size_unit;
 131         unsigned int burst_size_unit;
 132
 133         /* swap GFX & WB fifos */
 134         bool gfx_fifo_workaround:1;
 135
 136         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
 137         bool no_framedone_tv:1;
 138
 139         /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
 140         bool mstandby_workaround:1;
 141
 142         bool set_max_preload:1;
 143
 144         /* PIXEL_INC is not added to the last pixel of a line */
 145         bool last_pixel_inc_missing:1;
 146
 147         /* POL_FREQ has ALIGN bit */
 148         bool supports_sync_align:1;
 149
 150         bool has_writeback:1;
 151
 152         bool supports_double_pixel:1;
 153
 154         /*
 155          * Field order for VENC is different than HDMI. We should handle this in
 156          * some intelligent manner, but as the SoCs have either HDMI or VENC,
 157          * never both, we can just use this flag for now.
 158          */
 159         bool reverse_ilace_field_order:1;
 160
 161         bool has_gamma_table:1;
 162
 163         bool has_gamma_i734_bug:1;
 164 };
 165
 166 #define DISPC_MAX_NR_FIFOS 5
 167 #define DISPC_MAX_CHANNEL_GAMMA 4
 168
 169 struct dispc_device {
 170         struct platform_device *pdev;
 171         void __iomem    *base;
 172         struct dss_device *dss;
 173
 174         struct dss_debugfs_entry *debugfs;
 175
 176         int irq;
 177         irq_handler_t user_handler;
 178         void *user_data;
 179
 180         unsigned long core_clk_rate;
 181         unsigned long tv_pclk_rate;
 182
 183         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 184         /* maps which plane is using a fifo. fifo-id -> plane-id */
 185         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 186
 187         bool            ctx_valid;
 188         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 189
 190         u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA];
 191
 192         const struct dispc_features *feat;
 193
 194         bool is_enabled;
 195
 196         struct regmap *syscon_pol;
 197         u32 syscon_pol_offset;
 198
 199         /* DISPC_CONTROL & DISPC_CONFIG lock*/
 200         spinlock_t control_lock;
 201 };
 202
 203 enum omap_color_component {
 204         /* used for all color formats for OMAP3 and earlier
 205          * and for RGB and Y color component on OMAP4
 206          */
 207         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 208         /* used for UV component for
 209          * DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12
 210          * color formats on OMAP4
 211          */
 212         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 213 };
 214
 215 enum mgr_reg_fields {
 216         DISPC_MGR_FLD_ENABLE,
 217         DISPC_MGR_FLD_STNTFT,
 218         DISPC_MGR_FLD_GO,
 219         DISPC_MGR_FLD_TFTDATALINES,
 220         DISPC_MGR_FLD_STALLMODE,
 221         DISPC_MGR_FLD_TCKENABLE,
 222         DISPC_MGR_FLD_TCKSELECTION,
 223         DISPC_MGR_FLD_CPR,
 224         DISPC_MGR_FLD_FIFOHANDCHECK,
 225         /* used to maintain a count of the above fields */
 226         DISPC_MGR_FLD_NUM,
 227 };
 228
 229 /* DISPC register field id */
 230 enum dispc_feat_reg_field {
 231         FEAT_REG_FIRHINC,
 232         FEAT_REG_FIRVINC,
 233         FEAT_REG_FIFOHIGHTHRESHOLD,
 234         FEAT_REG_FIFOLOWTHRESHOLD,
 235         FEAT_REG_FIFOSIZE,
 236         FEAT_REG_HORIZONTALACCU,
 237         FEAT_REG_VERTICALACCU,
 238 };
 239
 240 struct dispc_reg_field {
 241         u16 reg;
 242         u8 high;
 243         u8 low;
 244 };
 245
 246 struct dispc_gamma_desc {
 247         u32 len;
 248         u32 bits;
 249         u16 reg;
 250         bool has_index;
 251 };
 252
 253 static const struct {
 254         const char *name;
 255         u32 vsync_irq;
 256         u32 framedone_irq;
 257         u32 sync_lost_irq;
 258         struct dispc_gamma_desc gamma;
 259         struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
 260 } mgr_desc[] = {
 261         [OMAP_DSS_CHANNEL_LCD] = {
 262                 .name           = "LCD",
 263                 .vsync_irq      = DISPC_IRQ_VSYNC,
 264                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 265                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 266                 .gamma          = {
 267                         .len    = 256,
 268                         .bits   = 8,
 269                         .reg    = DISPC_GAMMA_TABLE0,
 270                         .has_index = true,
 271                 },
 272                 .reg_desc       = {
 273                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 274                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 275                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 276                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 277                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 278                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 279                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 280                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 281                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 282                 },
 283         },
 284         [OMAP_DSS_CHANNEL_DIGIT] = {
 285                 .name           = "DIGIT",
 286                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 287                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 288                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 289                 .gamma          = {
 290                         .len    = 1024,
 291                         .bits   = 10,
 292                         .reg    = DISPC_GAMMA_TABLE2,
 293                         .has_index = false,
 294                 },
 295                 .reg_desc       = {
 296                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 297                         [DISPC_MGR_FLD_STNTFT]          = { },
 298                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 299                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 300                         [DISPC_MGR_FLD_STALLMODE]       = { },
 301                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 302                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 303                         [DISPC_MGR_FLD_CPR]             = { },
 304                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 305                 },
 306         },
 307         [OMAP_DSS_CHANNEL_LCD2] = {
 308                 .name           = "LCD2",
 309                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 310                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 311                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 312                 .gamma          = {
 313                         .len    = 256,
 314                         .bits   = 8,
 315                         .reg    = DISPC_GAMMA_TABLE1,
 316                         .has_index = true,
 317                 },
 318                 .reg_desc       = {
 319                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 320                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 321                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 322                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 323                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 324                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 325                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 326                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 327                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 328                 },
 329         },
 330         [OMAP_DSS_CHANNEL_LCD3] = {
 331                 .name           = "LCD3",
 332                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 333                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 334                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 335                 .gamma          = {
 336                         .len    = 256,
 337                         .bits   = 8,
 338                         .reg    = DISPC_GAMMA_TABLE3,
 339                         .has_index = true,
 340                 },
 341                 .reg_desc       = {
 342                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 343                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 344                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 345                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 346                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 347                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 348                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 349                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 350                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 351                 },
 352         },
 353 };
 354
 355 static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
 356 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
 357 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
 358                                          enum omap_channel channel);
 359 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
 360                                          enum omap_channel channel);
 361
 362 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
 363                                            enum omap_plane_id plane);
 364 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
 365                                            enum omap_plane_id plane);
 366
 367 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
 368
 369 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val)
 370 {
 371         __raw_writel(val, dispc->base + idx);
 372 }
 373
 374 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx)
 375 {
 376         return __raw_readl(dispc->base + idx);
 377 }
 378
 379 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel,
 380                         enum mgr_reg_fields regfld)
 381 {
 382         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 383
 384         return REG_GET(dispc, rfld.reg, rfld.high, rfld.low);
 385 }
 386
 387 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel,
 388                           enum mgr_reg_fields regfld, int val)
 389 {
 390         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 391         const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
 392         unsigned long flags;
 393
 394         if (need_lock) {
 395                 spin_lock_irqsave(&dispc->control_lock, flags);
 396                 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low);
 397                 spin_unlock_irqrestore(&dispc->control_lock, flags);
 398         } else {
 399                 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low);
 400         }
 401 }
 402
 403 static int dispc_get_num_ovls(struct dispc_device *dispc)
 404 {
 405         return dispc->feat->num_ovls;
 406 }
 407
 408 static int dispc_get_num_mgrs(struct dispc_device *dispc)
 409 {
 410         return dispc->feat->num_mgrs;
 411 }
 412
 413 static void dispc_get_reg_field(struct dispc_device *dispc,
 414                                 enum dispc_feat_reg_field id,
 415                                 u8 *start, u8 *end)
 416 {
 417         if (id >= dispc->feat->num_reg_fields)
 418                 BUG();
 419
 420         *start = dispc->feat->reg_fields[id].start;
 421         *end = dispc->feat->reg_fields[id].end;
 422 }
 423
 424 static bool dispc_has_feature(struct dispc_device *dispc,
 425                               enum dispc_feature_id id)
 426 {
 427         unsigned int i;
 428
 429         for (i = 0; i < dispc->feat->num_features; i++) {
 430                 if (dispc->feat->features[i] == id)
 431                         return true;
 432         }
 433
 434         return false;
 435 }
 436
 437 #define SR(dispc, reg) \
 438         dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
 439 #define RR(dispc, reg) \
 440         dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
 441
 442 static void dispc_save_context(struct dispc_device *dispc)
 443 {
 444         int i, j;
 445
 446         DSSDBG("dispc_save_context\n");
 447
 448         SR(dispc, IRQENABLE);
 449         SR(dispc, CONTROL);
 450         SR(dispc, CONFIG);
 451         SR(dispc, LINE_NUMBER);
 452         if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) ||
 453                         dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
 454                 SR(dispc, GLOBAL_ALPHA);
 455         if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) {
 456                 SR(dispc, CONTROL2);
 457                 SR(dispc, CONFIG2);
 458         }
 459         if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) {
 460                 SR(dispc, CONTROL3);
 461                 SR(dispc, CONFIG3);
 462         }
 463
 464         for (i = 0; i < dispc_get_num_mgrs(dispc); i++) {
 465                 SR(dispc, DEFAULT_COLOR(i));
 466                 SR(dispc, TRANS_COLOR(i));
 467                 SR(dispc, SIZE_MGR(i));
 468                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 469                         continue;
 470                 SR(dispc, TIMING_H(i));
 471                 SR(dispc, TIMING_V(i));
 472                 SR(dispc, POL_FREQ(i));
 473                 SR(dispc, DIVISORo(i));
 474
 475                 SR(dispc, DATA_CYCLE1(i));
 476                 SR(dispc, DATA_CYCLE2(i));
 477                 SR(dispc, DATA_CYCLE3(i));
 478
 479                 if (dispc_has_feature(dispc, FEAT_CPR)) {
 480                         SR(dispc, CPR_COEF_R(i));
 481                         SR(dispc, CPR_COEF_G(i));
 482                         SR(dispc, CPR_COEF_B(i));
 483                 }
 484         }
 485
 486         for (i = 0; i < dispc_get_num_ovls(dispc); i++) {
 487                 SR(dispc, OVL_BA0(i));
 488                 SR(dispc, OVL_BA1(i));
 489                 SR(dispc, OVL_POSITION(i));
 490                 SR(dispc, OVL_SIZE(i));
 491                 SR(dispc, OVL_ATTRIBUTES(i));
 492                 SR(dispc, OVL_FIFO_THRESHOLD(i));
 493                 SR(dispc, OVL_ROW_INC(i));
 494                 SR(dispc, OVL_PIXEL_INC(i));
 495                 if (dispc_has_feature(dispc, FEAT_PRELOAD))
 496                         SR(dispc, OVL_PRELOAD(i));
 497                 if (i == OMAP_DSS_GFX) {
 498                         SR(dispc, OVL_WINDOW_SKIP(i));
 499                         SR(dispc, OVL_TABLE_BA(i));
 500                         continue;
 501                 }
 502                 SR(dispc, OVL_FIR(i));
 503                 SR(dispc, OVL_PICTURE_SIZE(i));
 504                 SR(dispc, OVL_ACCU0(i));
 505                 SR(dispc, OVL_ACCU1(i));
 506
 507                 for (j = 0; j < 8; j++)
 508                         SR(dispc, OVL_FIR_COEF_H(i, j));
 509
 510                 for (j = 0; j < 8; j++)
 511                         SR(dispc, OVL_FIR_COEF_HV(i, j));
 512
 513                 for (j = 0; j < 5; j++)
 514                         SR(dispc, OVL_CONV_COEF(i, j));
 515
 516                 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) {
 517                         for (j = 0; j < 8; j++)
 518                                 SR(dispc, OVL_FIR_COEF_V(i, j));
 519                 }
 520
 521                 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
 522                         SR(dispc, OVL_BA0_UV(i));
 523                         SR(dispc, OVL_BA1_UV(i));
 524                         SR(dispc, OVL_FIR2(i));
 525                         SR(dispc, OVL_ACCU2_0(i));
 526                         SR(dispc, OVL_ACCU2_1(i));
 527
 528                         for (j = 0; j < 8; j++)
 529                                 SR(dispc, OVL_FIR_COEF_H2(i, j));
 530
 531                         for (j = 0; j < 8; j++)
 532                                 SR(dispc, OVL_FIR_COEF_HV2(i, j));
 533
 534                         for (j = 0; j < 8; j++)
 535                                 SR(dispc, OVL_FIR_COEF_V2(i, j));
 536                 }
 537                 if (dispc_has_feature(dispc, FEAT_ATTR2))
 538                         SR(dispc, OVL_ATTRIBUTES2(i));
 539         }
 540
 541         if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV))
 542                 SR(dispc, DIVISOR);
 543
 544         dispc->ctx_valid = true;
 545
 546         DSSDBG("context saved\n");
 547 }
 548
 549 static void dispc_restore_context(struct dispc_device *dispc)
 550 {
 551         int i, j;
 552
 553         DSSDBG("dispc_restore_context\n");
 554
 555         if (!dispc->ctx_valid)
 556                 return;
 557
 558         /*RR(dispc, IRQENABLE);*/
 559         /*RR(dispc, CONTROL);*/
 560         RR(dispc, CONFIG);
 561         RR(dispc, LINE_NUMBER);
 562         if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) ||
 563                         dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
 564                 RR(dispc, GLOBAL_ALPHA);
 565         if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
 566                 RR(dispc, CONFIG2);
 567         if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
 568                 RR(dispc, CONFIG3);
 569
 570         for (i = 0; i < dispc_get_num_mgrs(dispc); i++) {
 571                 RR(dispc, DEFAULT_COLOR(i));
 572                 RR(dispc, TRANS_COLOR(i));
 573                 RR(dispc, SIZE_MGR(i));
 574                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 575                         continue;
 576                 RR(dispc, TIMING_H(i));
 577                 RR(dispc, TIMING_V(i));
 578                 RR(dispc, POL_FREQ(i));
 579                 RR(dispc, DIVISORo(i));
 580
 581                 RR(dispc, DATA_CYCLE1(i));
 582                 RR(dispc, DATA_CYCLE2(i));
 583                 RR(dispc, DATA_CYCLE3(i));
 584
 585                 if (dispc_has_feature(dispc, FEAT_CPR)) {
 586                         RR(dispc, CPR_COEF_R(i));
 587                         RR(dispc, CPR_COEF_G(i));
 588                         RR(dispc, CPR_COEF_B(i));
 589                 }
 590         }
 591
 592         for (i = 0; i < dispc_get_num_ovls(dispc); i++) {
 593                 RR(dispc, OVL_BA0(i));
 594                 RR(dispc, OVL_BA1(i));
 595                 RR(dispc, OVL_POSITION(i));
 596                 RR(dispc, OVL_SIZE(i));
 597                 RR(dispc, OVL_ATTRIBUTES(i));
 598                 RR(dispc, OVL_FIFO_THRESHOLD(i));
 599                 RR(dispc, OVL_ROW_INC(i));
 600                 RR(dispc, OVL_PIXEL_INC(i));
 601                 if (dispc_has_feature(dispc, FEAT_PRELOAD))
 602                         RR(dispc, OVL_PRELOAD(i));
 603                 if (i == OMAP_DSS_GFX) {
 604                         RR(dispc, OVL_WINDOW_SKIP(i));
 605                         RR(dispc, OVL_TABLE_BA(i));
 606                         continue;
 607                 }
 608                 RR(dispc, OVL_FIR(i));
 609                 RR(dispc, OVL_PICTURE_SIZE(i));
 610                 RR(dispc, OVL_ACCU0(i));
 611                 RR(dispc, OVL_ACCU1(i));
 612
 613                 for (j = 0; j < 8; j++)
 614                         RR(dispc, OVL_FIR_COEF_H(i, j));
 615
 616                 for (j = 0; j < 8; j++)
 617                         RR(dispc, OVL_FIR_COEF_HV(i, j));
 618
 619                 for (j = 0; j < 5; j++)
 620                         RR(dispc, OVL_CONV_COEF(i, j));
 621
 622                 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) {
 623                         for (j = 0; j < 8; j++)
 624                                 RR(dispc, OVL_FIR_COEF_V(i, j));
 625                 }
 626
 627                 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
 628                         RR(dispc, OVL_BA0_UV(i));
 629                         RR(dispc, OVL_BA1_UV(i));
 630                         RR(dispc, OVL_FIR2(i));
 631                         RR(dispc, OVL_ACCU2_0(i));
 632                         RR(dispc, OVL_ACCU2_1(i));
 633
 634                         for (j = 0; j < 8; j++)
 635                                 RR(dispc, OVL_FIR_COEF_H2(i, j));
 636
 637                         for (j = 0; j < 8; j++)
 638                                 RR(dispc, OVL_FIR_COEF_HV2(i, j));
 639
 640                         for (j = 0; j < 8; j++)
 641                                 RR(dispc, OVL_FIR_COEF_V2(i, j));
 642                 }
 643                 if (dispc_has_feature(dispc, FEAT_ATTR2))
 644                         RR(dispc, OVL_ATTRIBUTES2(i));
 645         }
 646
 647         if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV))
 648                 RR(dispc, DIVISOR);
 649
 650         /* enable last, because LCD & DIGIT enable are here */
 651         RR(dispc, CONTROL);
 652         if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
 653                 RR(dispc, CONTROL2);
 654         if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
 655                 RR(dispc, CONTROL3);
 656         /* clear spurious SYNC_LOST_DIGIT interrupts */
 657         dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT);
 658
 659         /*
 660          * enable last so IRQs won't trigger before
 661          * the context is fully restored
 662          */
 663         RR(dispc, IRQENABLE);
 664
 665         DSSDBG("context restored\n");
 666 }
 667
 668 #undef SR
 669 #undef RR
 670
 671 int dispc_runtime_get(struct dispc_device *dispc)
 672 {
 673         int r;
 674
 675         DSSDBG("dispc_runtime_get\n");
 676
 677         r = pm_runtime_get_sync(&dispc->pdev->dev);
 678         WARN_ON(r < 0);
 679         return r < 0 ? r : 0;
 680 }
 681
 682 void dispc_runtime_put(struct dispc_device *dispc)
 683 {
 684         int r;
 685
 686         DSSDBG("dispc_runtime_put\n");
 687
 688         r = pm_runtime_put_sync(&dispc->pdev->dev);
 689         WARN_ON(r < 0 && r != -ENOSYS);
 690 }
 691
 692 static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc,
 693                                    enum omap_channel channel)
 694 {
 695         return mgr_desc[channel].vsync_irq;
 696 }
 697
 698 static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc,
 699                                        enum omap_channel channel)
 700 {
 701         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv)
 702                 return 0;
 703
 704         return mgr_desc[channel].framedone_irq;
 705 }
 706
 707 static u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc,
 708                                        enum omap_channel channel)
 709 {
 710         return mgr_desc[channel].sync_lost_irq;
 711 }
 712
 713 static u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc)
 714 {
 715         return DISPC_IRQ_FRAMEDONEWB;
 716 }
 717
 718 static void dispc_mgr_enable(struct dispc_device *dispc,
 719                              enum omap_channel channel, bool enable)
 720 {
 721         mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable);
 722         /* flush posted write */
 723         mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE);
 724 }
 725
 726 static bool dispc_mgr_is_enabled(struct dispc_device *dispc,
 727                                  enum omap_channel channel)
 728 {
 729         return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE);
 730 }
 731
 732 static bool dispc_mgr_go_busy(struct dispc_device *dispc,
 733                               enum omap_channel channel)
 734 {
 735         return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1;
 736 }
 737
 738 static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel)
 739 {
 740         WARN_ON(!dispc_mgr_is_enabled(dispc, channel));
 741         WARN_ON(dispc_mgr_go_busy(dispc, channel));
 742
 743         DSSDBG("GO %s\n", mgr_desc[channel].name);
 744
 745         mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1);
 746 }
 747
 748 static bool dispc_wb_go_busy(struct dispc_device *dispc)
 749 {
 750         return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1;
 751 }
 752
 753 static void dispc_wb_go(struct dispc_device *dispc)
 754 {
 755         enum omap_plane_id plane = OMAP_DSS_WB;
 756         bool enable, go;
 757
 758         enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 759
 760         if (!enable)
 761                 return;
 762
 763         go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1;
 764         if (go) {
 765                 DSSERR("GO bit not down for WB\n");
 766                 return;
 767         }
 768
 769         REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6);
 770 }
 771
 772 static void dispc_ovl_write_firh_reg(struct dispc_device *dispc,
 773                                      enum omap_plane_id plane, int reg,
 774                                      u32 value)
 775 {
 776         dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value);
 777 }
 778
 779 static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc,
 780                                       enum omap_plane_id plane, int reg,
 781                                       u32 value)
 782 {
 783         dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 784 }
 785
 786 static void dispc_ovl_write_firv_reg(struct dispc_device *dispc,
 787                                      enum omap_plane_id plane, int reg,
 788                                      u32 value)
 789 {
 790         dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value);
 791 }
 792
 793 static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc,
 794                                       enum omap_plane_id plane, int reg,
 795                                       u32 value)
 796 {
 797         BUG_ON(plane == OMAP_DSS_GFX);
 798
 799         dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 800 }
 801
 802 static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc,
 803                                        enum omap_plane_id plane, int reg,
 804                                        u32 value)
 805 {
 806         BUG_ON(plane == OMAP_DSS_GFX);
 807
 808         dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 809 }
 810
 811 static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc,
 812                                       enum omap_plane_id plane, int reg,
 813                                       u32 value)
 814 {
 815         BUG_ON(plane == OMAP_DSS_GFX);
 816
 817         dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 818 }
 819
 820 static void dispc_ovl_set_scale_coef(struct dispc_device *dispc,
 821                                      enum omap_plane_id plane, int fir_hinc,
 822                                      int fir_vinc, int five_taps,
 823                                      enum omap_color_component color_comp)
 824 {
 825         const struct dispc_coef *h_coef, *v_coef;
 826         int i;
 827
 828         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 829         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 830
 831         if (!h_coef || !v_coef) {
 832                 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n",
 833                         __func__);
 834                 return;
 835         }
 836
 837         for (i = 0; i < 8; i++) {
 838                 u32 h, hv;
 839
 840                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 841                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 842                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 843                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 844                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 845                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 846                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 847                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 848
 849                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 850                         dispc_ovl_write_firh_reg(dispc, plane, i, h);
 851                         dispc_ovl_write_firhv_reg(dispc, plane, i, hv);
 852                 } else {
 853                         dispc_ovl_write_firh2_reg(dispc, plane, i, h);
 854                         dispc_ovl_write_firhv2_reg(dispc, plane, i, hv);
 855                 }
 856
 857         }
 858
 859         if (five_taps) {
 860                 for (i = 0; i < 8; i++) {
 861                         u32 v;
 862                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 863                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 864                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 865                                 dispc_ovl_write_firv_reg(dispc, plane, i, v);
 866                         else
 867                                 dispc_ovl_write_firv2_reg(dispc, plane, i, v);
 868                 }
 869         }
 870 }
 871
 872 struct csc_coef_yuv2rgb {
 873         int ry, rcb, rcr, gy, gcb, gcr, by, bcb, bcr;
 874         bool full_range;
 875 };
 876
 877 struct csc_coef_rgb2yuv {
 878         int yr, yg, yb, cbr, cbg, cbb, crr, crg, crb;
 879         bool full_range;
 880 };
 881
 882 static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc,
 883                                             enum omap_plane_id plane,
 884                                             const struct csc_coef_yuv2rgb *ct)
 885 {
 886 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 887
 888         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 889         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 890         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 891         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 892         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 893
 894         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 895
 896 #undef CVAL
 897 }
 898
 899 static void dispc_wb_write_color_conv_coef(struct dispc_device *dispc,
 900                                            const struct csc_coef_rgb2yuv *ct)
 901 {
 902         const enum omap_plane_id plane = OMAP_DSS_WB;
 903
 904 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 905
 906         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg,  ct->yr));
 907         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb));
 908         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg));
 909         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr));
 910         dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb));
 911
 912         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 913
 914 #undef CVAL
 915 }
 916
 917 static void dispc_setup_color_conv_coef(struct dispc_device *dispc)
 918 {
 919         int i;
 920         int num_ovl = dispc_get_num_ovls(dispc);
 921
 922         /* YUV -> RGB, ITU-R BT.601, limited range */
 923         const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_lim = {
 924                 298,    0,  409,        /* ry, rcb, rcr */
 925                 298, -100, -208,        /* gy, gcb, gcr */
 926                 298,  516,    0,        /* by, bcb, bcr */
 927                 false,                  /* limited range */
 928         };
 929
 930         /* RGB -> YUV, ITU-R BT.601, limited range */
 931         const struct csc_coef_rgb2yuv coefs_rgb2yuv_bt601_lim = {
 932                  66, 129,  25,          /* yr,   yg,  yb */
 933                 -38, -74, 112,          /* cbr, cbg, cbb */
 934                 112, -94, -18,          /* crr, crg, crb */
 935                 false,                  /* limited range */
 936         };
 937
 938         for (i = 1; i < num_ovl; i++)
 939                 dispc_ovl_write_color_conv_coef(dispc, i, &coefs_yuv2rgb_bt601_lim);
 940
 941         if (dispc->feat->has_writeback)
 942                 dispc_wb_write_color_conv_coef(dispc, &coefs_rgb2yuv_bt601_lim);
 943 }
 944
 945 static void dispc_ovl_set_ba0(struct dispc_device *dispc,
 946                               enum omap_plane_id plane, u32 paddr)
 947 {
 948         dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr);
 949 }
 950
 951 static void dispc_ovl_set_ba1(struct dispc_device *dispc,
 952                               enum omap_plane_id plane, u32 paddr)
 953 {
 954         dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr);
 955 }
 956
 957 static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc,
 958                                  enum omap_plane_id plane, u32 paddr)
 959 {
 960         dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr);
 961 }
 962
 963 static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc,
 964                                  enum omap_plane_id plane, u32 paddr)
 965 {
 966         dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr);
 967 }
 968
 969 static void dispc_ovl_set_pos(struct dispc_device *dispc,
 970                               enum omap_plane_id plane,
 971                               enum omap_overlay_caps caps, int x, int y)
 972 {
 973         u32 val;
 974
 975         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 976                 return;
 977
 978         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 979
 980         dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val);
 981 }
 982
 983 static void dispc_ovl_set_input_size(struct dispc_device *dispc,
 984                                      enum omap_plane_id plane, int width,
 985                                      int height)
 986 {
 987         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 988
 989         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 990                 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
 991         else
 992                 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
 993 }
 994
 995 static void dispc_ovl_set_output_size(struct dispc_device *dispc,
 996                                       enum omap_plane_id plane, int width,
 997                                       int height)
 998 {
 999         u32 val;
1000
1001         BUG_ON(plane == OMAP_DSS_GFX);
1002
1003         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1004
1005         if (plane == OMAP_DSS_WB)
1006                 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
1007         else
1008                 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
1009 }
1010
1011 static void dispc_ovl_set_zorder(struct dispc_device *dispc,
1012                                  enum omap_plane_id plane,
1013                                  enum omap_overlay_caps caps, u8 zorder)
1014 {
1015         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
1016                 return;
1017
1018         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
1019 }
1020
1021 static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc)
1022 {
1023         int i;
1024
1025         if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
1026                 return;
1027
1028         for (i = 0; i < dispc_get_num_ovls(dispc); i++)
1029                 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
1030 }
1031
1032 static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc,
1033                                          enum omap_plane_id plane,
1034                                          enum omap_overlay_caps caps,
1035                                          bool enable)
1036 {
1037         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
1038                 return;
1039
1040         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
1041 }
1042
1043 static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc,
1044                                          enum omap_plane_id plane,
1045                                          enum omap_overlay_caps caps,
1046                                          u8 global_alpha)
1047 {
1048         static const unsigned int shifts[] = { 0, 8, 16, 24, };
1049         int shift;
1050
1051         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
1052                 return;
1053
1054         shift = shifts[plane];
1055         REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
1056 }
1057
1058 static void dispc_ovl_set_pix_inc(struct dispc_device *dispc,
1059                                   enum omap_plane_id plane, s32 inc)
1060 {
1061         dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc);
1062 }
1063
1064 static void dispc_ovl_set_row_inc(struct dispc_device *dispc,
1065                                   enum omap_plane_id plane, s32 inc)
1066 {
1067         dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc);
1068 }
1069
1070 static void dispc_ovl_set_color_mode(struct dispc_device *dispc,
1071                                      enum omap_plane_id plane, u32 fourcc)
1072 {
1073         u32 m = 0;
1074         if (plane != OMAP_DSS_GFX) {
1075                 switch (fourcc) {
1076                 case DRM_FORMAT_NV12:
1077                         m = 0x0; break;
1078                 case DRM_FORMAT_XRGB4444:
1079                         m = 0x1; break;
1080                 case DRM_FORMAT_RGBA4444:
1081                         m = 0x2; break;
1082                 case DRM_FORMAT_RGBX4444:
1083                         m = 0x4; break;
1084                 case DRM_FORMAT_ARGB4444:
1085                         m = 0x5; break;
1086                 case DRM_FORMAT_RGB565:
1087                         m = 0x6; break;
1088                 case DRM_FORMAT_ARGB1555:
1089                         m = 0x7; break;
1090                 case DRM_FORMAT_XRGB8888:
1091                         m = 0x8; break;
1092                 case DRM_FORMAT_RGB888:
1093                         m = 0x9; break;
1094                 case DRM_FORMAT_YUYV:
1095                         m = 0xa; break;
1096                 case DRM_FORMAT_UYVY:
1097                         m = 0xb; break;
1098                 case DRM_FORMAT_ARGB8888:
1099                         m = 0xc; break;
1100                 case DRM_FORMAT_RGBA8888:
1101                         m = 0xd; break;
1102                 case DRM_FORMAT_RGBX8888:
1103                         m = 0xe; break;
1104                 case DRM_FORMAT_XRGB1555:
1105                         m = 0xf; break;
1106                 default:
1107                         BUG(); return;
1108                 }
1109         } else {
1110                 switch (fourcc) {
1111                 case DRM_FORMAT_RGBX4444:
1112                         m = 0x4; break;
1113                 case DRM_FORMAT_ARGB4444:
1114                         m = 0x5; break;
1115                 case DRM_FORMAT_RGB565:
1116                         m = 0x6; break;
1117                 case DRM_FORMAT_ARGB1555:
1118                         m = 0x7; break;
1119                 case DRM_FORMAT_XRGB8888:
1120                         m = 0x8; break;
1121                 case DRM_FORMAT_RGB888:
1122                         m = 0x9; break;
1123                 case DRM_FORMAT_XRGB4444:
1124                         m = 0xa; break;
1125                 case DRM_FORMAT_RGBA4444:
1126                         m = 0xb; break;
1127                 case DRM_FORMAT_ARGB8888:
1128                         m = 0xc; break;
1129                 case DRM_FORMAT_RGBA8888:
1130                         m = 0xd; break;
1131                 case DRM_FORMAT_RGBX8888:
1132                         m = 0xe; break;
1133                 case DRM_FORMAT_XRGB1555:
1134                         m = 0xf; break;
1135                 default:
1136                         BUG(); return;
1137                 }
1138         }
1139
1140         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
1141 }
1142
1143 static void dispc_ovl_configure_burst_type(struct dispc_device *dispc,
1144                                            enum omap_plane_id plane,
1145                                            enum omap_dss_rotation_type rotation)
1146 {
1147         if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0)
1148                 return;
1149
1150         if (rotation == OMAP_DSS_ROT_TILER)
1151                 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
1152         else
1153                 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
1154 }
1155
1156 static void dispc_ovl_set_channel_out(struct dispc_device *dispc,
1157                                       enum omap_plane_id plane,
1158                                       enum omap_channel channel)
1159 {
1160         int shift;
1161         u32 val;
1162         int chan = 0, chan2 = 0;
1163
1164         switch (plane) {
1165         case OMAP_DSS_GFX:
1166                 shift = 8;
1167                 break;
1168         case OMAP_DSS_VIDEO1:
1169         case OMAP_DSS_VIDEO2:
1170         case OMAP_DSS_VIDEO3:
1171                 shift = 16;
1172                 break;
1173         default:
1174                 BUG();
1175                 return;
1176         }
1177
1178         val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1179         if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) {
1180                 switch (channel) {
1181                 case OMAP_DSS_CHANNEL_LCD:
1182                         chan = 0;
1183                         chan2 = 0;
1184                         break;
1185                 case OMAP_DSS_CHANNEL_DIGIT:
1186                         chan = 1;
1187                         chan2 = 0;
1188                         break;
1189                 case OMAP_DSS_CHANNEL_LCD2:
1190                         chan = 0;
1191                         chan2 = 1;
1192                         break;
1193                 case OMAP_DSS_CHANNEL_LCD3:
1194                         if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) {
1195                                 chan = 0;
1196                                 chan2 = 2;
1197                         } else {
1198                                 BUG();
1199                                 return;
1200                         }
1201                         break;
1202                 case OMAP_DSS_CHANNEL_WB:
1203                         chan = 0;
1204                         chan2 = 3;
1205                         break;
1206                 default:
1207                         BUG();
1208                         return;
1209                 }
1210
1211                 val = FLD_MOD(val, chan, shift, shift);
1212                 val = FLD_MOD(val, chan2, 31, 30);
1213         } else {
1214                 val = FLD_MOD(val, channel, shift, shift);
1215         }
1216         dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1217 }
1218
1219 static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc,
1220                                                    enum omap_plane_id plane)
1221 {
1222         int shift;
1223         u32 val;
1224
1225         switch (plane) {
1226         case OMAP_DSS_GFX:
1227                 shift = 8;
1228                 break;
1229         case OMAP_DSS_VIDEO1:
1230         case OMAP_DSS_VIDEO2:
1231         case OMAP_DSS_VIDEO3:
1232                 shift = 16;
1233                 break;
1234         default:
1235                 BUG();
1236                 return 0;
1237         }
1238
1239         val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1240
1241         if (FLD_GET(val, shift, shift) == 1)
1242                 return OMAP_DSS_CHANNEL_DIGIT;
1243
1244         if (!dispc_has_feature(dispc, FEAT_MGR_LCD2))
1245                 return OMAP_DSS_CHANNEL_LCD;
1246
1247         switch (FLD_GET(val, 31, 30)) {
1248         case 0:
1249         default:
1250                 return OMAP_DSS_CHANNEL_LCD;
1251         case 1:
1252                 return OMAP_DSS_CHANNEL_LCD2;
1253         case 2:
1254                 return OMAP_DSS_CHANNEL_LCD3;
1255         case 3:
1256                 return OMAP_DSS_CHANNEL_WB;
1257         }
1258 }
1259
1260 static void dispc_ovl_set_burst_size(struct dispc_device *dispc,
1261                                      enum omap_plane_id plane,
1262                                      enum omap_burst_size burst_size)
1263 {
1264         static const unsigned int shifts[] = { 6, 14, 14, 14, 14, };
1265         int shift;
1266
1267         shift = shifts[plane];
1268         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size,
1269                     shift + 1, shift);
1270 }
1271
1272 static void dispc_configure_burst_sizes(struct dispc_device *dispc)
1273 {
1274         int i;
1275         const int burst_size = BURST_SIZE_X8;
1276
1277         /* Configure burst size always to maximum size */
1278         for (i = 0; i < dispc_get_num_ovls(dispc); ++i)
1279                 dispc_ovl_set_burst_size(dispc, i, burst_size);
1280         if (dispc->feat->has_writeback)
1281                 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size);
1282 }
1283
1284 static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc,
1285                                     enum omap_plane_id plane)
1286 {
1287         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1288         return dispc->feat->burst_size_unit * 8;
1289 }
1290
1291 static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc,
1292                                            enum omap_plane_id plane, u32 fourcc)
1293 {
1294         const u32 *modes;
1295         unsigned int i;
1296
1297         modes = dispc->feat->supported_color_modes[plane];
1298
1299         for (i = 0; modes[i]; ++i) {
1300                 if (modes[i] == fourcc)
1301                         return true;
1302         }
1303
1304         return false;
1305 }
1306
1307 static const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,
1308                                             enum omap_plane_id plane)
1309 {
1310         return dispc->feat->supported_color_modes[plane];
1311 }
1312
1313 static void dispc_mgr_enable_cpr(struct dispc_device *dispc,
1314                                  enum omap_channel channel, bool enable)
1315 {
1316         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1317                 return;
1318
1319         mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable);
1320 }
1321
1322 static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc,
1323                                    enum omap_channel channel,
1324                                    const struct omap_dss_cpr_coefs *coefs)
1325 {
1326         u32 coef_r, coef_g, coef_b;
1327
1328         if (!dss_mgr_is_lcd(channel))
1329                 return;
1330
1331         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1332                 FLD_VAL(coefs->rb, 9, 0);
1333         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1334                 FLD_VAL(coefs->gb, 9, 0);
1335         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1336                 FLD_VAL(coefs->bb, 9, 0);
1337
1338         dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r);
1339         dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g);
1340         dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b);
1341 }
1342
1343 static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc,
1344                                          enum omap_plane_id plane, bool enable)
1345 {
1346         u32 val;
1347
1348         BUG_ON(plane == OMAP_DSS_GFX);
1349
1350         val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1351         val = FLD_MOD(val, enable, 9, 9);
1352         dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1353 }
1354
1355 static void dispc_ovl_enable_replication(struct dispc_device *dispc,
1356                                          enum omap_plane_id plane,
1357                                          enum omap_overlay_caps caps,
1358                                          bool enable)
1359 {
1360         static const unsigned int shifts[] = { 5, 10, 10, 10 };
1361         int shift;
1362
1363         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1364                 return;
1365
1366         shift = shifts[plane];
1367         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1368 }
1369
1370 static void dispc_mgr_set_size(struct dispc_device *dispc,
1371                                enum omap_channel channel, u16 width, u16 height)
1372 {
1373         u32 val;
1374
1375         val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) |
1376                 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0);
1377
1378         dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val);
1379 }
1380
1381 static void dispc_init_fifos(struct dispc_device *dispc)
1382 {
1383         u32 size;
1384         int fifo;
1385         u8 start, end;
1386         u32 unit;
1387         int i;
1388
1389         unit = dispc->feat->buffer_size_unit;
1390
1391         dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end);
1392
1393         for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) {
1394                 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo),
1395                                start, end);
1396                 size *= unit;
1397                 dispc->fifo_size[fifo] = size;
1398
1399                 /*
1400                  * By default fifos are mapped directly to overlays, fifo 0 to
1401                  * ovl 0, fifo 1 to ovl 1, etc.
1402                  */
1403                 dispc->fifo_assignment[fifo] = fifo;
1404         }
1405
1406         /*
1407          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1408          * causes problems with certain use cases, like using the tiler in 2D
1409          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1410          * giving GFX plane a larger fifo. WB but should work fine with a
1411          * smaller fifo.
1412          */
1413         if (dispc->feat->gfx_fifo_workaround) {
1414                 u32 v;
1415
1416                 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER);
1417
1418                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1419                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1420                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1421                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1422
1423                 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v);
1424
1425                 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1426                 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1427         }
1428
1429         /*
1430          * Setup default fifo thresholds.
1431          */
1432         for (i = 0; i < dispc_get_num_ovls(dispc); ++i) {
1433                 u32 low, high;
1434                 const bool use_fifomerge = false;
1435                 const bool manual_update = false;
1436
1437                 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high,
1438                                                   use_fifomerge, manual_update);
1439
1440                 dispc_ovl_set_fifo_threshold(dispc, i, low, high);
1441         }
1442
1443         if (dispc->feat->has_writeback) {
1444                 u32 low, high;
1445                 const bool use_fifomerge = false;
1446                 const bool manual_update = false;
1447
1448                 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB,
1449                                                   &low, &high, use_fifomerge,
1450                                                   manual_update);
1451
1452                 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high);
1453         }
1454 }
1455
1456 static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc,
1457                                    enum omap_plane_id plane)
1458 {
1459         int fifo;
1460         u32 size = 0;
1461
1462         for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) {
1463                 if (dispc->fifo_assignment[fifo] == plane)
1464                         size += dispc->fifo_size[fifo];
1465         }
1466
1467         return size;
1468 }
1469
1470 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
1471                                   enum omap_plane_id plane,
1472                                   u32 low, u32 high)
1473 {
1474         u8 hi_start, hi_end, lo_start, lo_end;
1475         u32 unit;
1476
1477         unit = dispc->feat->buffer_size_unit;
1478
1479         WARN_ON(low % unit != 0);
1480         WARN_ON(high % unit != 0);
1481
1482         low /= unit;
1483         high /= unit;
1484
1485         dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD,
1486                             &hi_start, &hi_end);
1487         dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD,
1488                             &lo_start, &lo_end);
1489
1490         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1491                         plane,
1492                         REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1493                                 lo_start, lo_end) * unit,
1494                         REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1495                                 hi_start, hi_end) * unit,
1496                         low * unit, high * unit);
1497
1498         dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1499                         FLD_VAL(high, hi_start, hi_end) |
1500                         FLD_VAL(low, lo_start, lo_end));
1501
1502         /*
1503          * configure the preload to the pipeline's high threhold, if HT it's too
1504          * large for the preload field, set the threshold to the maximum value
1505          * that can be held by the preload register
1506          */
1507         if (dispc_has_feature(dispc, FEAT_PRELOAD) &&
1508             dispc->feat->set_max_preload && plane != OMAP_DSS_WB)
1509                 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane),
1510                                 min(high, 0xfffu));
1511 }
1512
1513 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable)
1514 {
1515         if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) {
1516                 WARN_ON(enable);
1517                 return;
1518         }
1519
1520         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1521         REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1522 }
1523
1524 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
1525                                        enum omap_plane_id plane,
1526                                        u32 *fifo_low, u32 *fifo_high,
1527                                        bool use_fifomerge, bool manual_update)
1528 {
1529         /*
1530          * All sizes are in bytes. Both the buffer and burst are made of
1531          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1532          */
1533         unsigned int buf_unit = dispc->feat->buffer_size_unit;
1534         unsigned int ovl_fifo_size, total_fifo_size, burst_size;
1535         int i;
1536
1537         burst_size = dispc_ovl_get_burst_size(dispc, plane);
1538         ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane);
1539
1540         if (use_fifomerge) {
1541                 total_fifo_size = 0;
1542                 for (i = 0; i < dispc_get_num_ovls(dispc); ++i)
1543                         total_fifo_size += dispc_ovl_get_fifo_size(dispc, i);
1544         } else {
1545                 total_fifo_size = ovl_fifo_size;
1546         }
1547
1548         /*
1549          * We use the same low threshold for both fifomerge and non-fifomerge
1550          * cases, but for fifomerge we calculate the high threshold using the
1551          * combined fifo size
1552          */
1553
1554         if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) {
1555                 *fifo_low = ovl_fifo_size - burst_size * 2;
1556                 *fifo_high = total_fifo_size - burst_size;
1557         } else if (plane == OMAP_DSS_WB) {
1558                 /*
1559                  * Most optimal configuration for writeback is to push out data
1560                  * to the interconnect the moment writeback pushes enough pixels
1561                  * in the FIFO to form a burst
1562                  */
1563                 *fifo_low = 0;
1564                 *fifo_high = burst_size;
1565         } else {
1566                 *fifo_low = ovl_fifo_size - burst_size;
1567                 *fifo_high = total_fifo_size - buf_unit;
1568         }
1569 }
1570
1571 static void dispc_ovl_set_mflag(struct dispc_device *dispc,
1572                                 enum omap_plane_id plane, bool enable)
1573 {
1574         int bit;
1575
1576         if (plane == OMAP_DSS_GFX)
1577                 bit = 14;
1578         else
1579                 bit = 23;
1580
1581         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1582 }
1583
1584 static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc,
1585                                           enum omap_plane_id plane,
1586                                           int low, int high)
1587 {
1588         dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane),
1589                 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1590 }
1591
1592 static void dispc_init_mflag(struct dispc_device *dispc)
1593 {
1594         int i;
1595
1596         /*
1597          * HACK: NV12 color format and MFLAG seem to have problems working
1598          * together: using two displays, and having an NV12 overlay on one of
1599          * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1600          * Changing MFLAG thresholds and PRELOAD to certain values seem to
1601          * remove the errors, but there doesn't seem to be a clear logic on
1602          * which values work and which not.
1603          *
1604          * As a work-around, set force MFLAG to always on.
1605          */
1606         dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1607                 (1 << 0) |      /* MFLAG_CTRL = force always on */
1608                 (0 << 2));      /* MFLAG_START = disable */
1609
1610         for (i = 0; i < dispc_get_num_ovls(dispc); ++i) {
1611                 u32 size = dispc_ovl_get_fifo_size(dispc, i);
1612                 u32 unit = dispc->feat->buffer_size_unit;
1613                 u32 low, high;
1614
1615                 dispc_ovl_set_mflag(dispc, i, true);
1616
1617                 /*
1618                  * Simulation team suggests below thesholds:
1619                  * HT = fifosize * 5 / 8;
1620                  * LT = fifosize * 4 / 8;
1621                  */
1622
1623                 low = size * 4 / 8 / unit;
1624                 high = size * 5 / 8 / unit;
1625
1626                 dispc_ovl_set_mflag_threshold(dispc, i, low, high);
1627         }
1628
1629         if (dispc->feat->has_writeback) {
1630                 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB);
1631                 u32 unit = dispc->feat->buffer_size_unit;
1632                 u32 low, high;
1633
1634                 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true);
1635
1636                 /*
1637                  * Simulation team suggests below thesholds:
1638                  * HT = fifosize * 5 / 8;
1639                  * LT = fifosize * 4 / 8;
1640                  */
1641
1642                 low = size * 4 / 8 / unit;
1643                 high = size * 5 / 8 / unit;
1644
1645                 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high);
1646         }
1647 }
1648
1649 static void dispc_ovl_set_fir(struct dispc_device *dispc,
1650                               enum omap_plane_id plane,
1651                               int hinc, int vinc,
1652                               enum omap_color_component color_comp)
1653 {
1654         u32 val;
1655
1656         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1657                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1658
1659                 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC,
1660                                     &hinc_start, &hinc_end);
1661                 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC,
1662                                     &vinc_start, &vinc_end);
1663                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1664                                 FLD_VAL(hinc, hinc_start, hinc_end);
1665
1666                 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val);
1667         } else {
1668                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1669                 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val);
1670         }
1671 }
1672
1673 static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc,
1674                                     enum omap_plane_id plane, int haccu,
1675                                     int vaccu)
1676 {
1677         u32 val;
1678         u8 hor_start, hor_end, vert_start, vert_end;
1679
1680         dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU,
1681                             &hor_start, &hor_end);
1682         dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU,
1683                             &vert_start, &vert_end);
1684
1685         val = FLD_VAL(vaccu, vert_start, vert_end) |
1686                         FLD_VAL(haccu, hor_start, hor_end);
1687
1688         dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val);
1689 }
1690
1691 static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc,
1692                                     enum omap_plane_id plane, int haccu,
1693                                     int vaccu)
1694 {
1695         u32 val;
1696         u8 hor_start, hor_end, vert_start, vert_end;
1697
1698         dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU,
1699                             &hor_start, &hor_end);
1700         dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU,
1701                             &vert_start, &vert_end);
1702
1703         val = FLD_VAL(vaccu, vert_start, vert_end) |
1704                         FLD_VAL(haccu, hor_start, hor_end);
1705
1706         dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val);
1707 }
1708
1709 static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc,
1710                                       enum omap_plane_id plane, int haccu,
1711                                       int vaccu)
1712 {
1713         u32 val;
1714
1715         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1716         dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val);
1717 }
1718
1719 static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc,
1720                                       enum omap_plane_id plane, int haccu,
1721                                       int vaccu)
1722 {
1723         u32 val;
1724
1725         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1726         dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val);
1727 }
1728
1729 static void dispc_ovl_set_scale_param(struct dispc_device *dispc,
1730                                       enum omap_plane_id plane,
1731                                       u16 orig_width, u16 orig_height,
1732                                       u16 out_width, u16 out_height,
1733                                       bool five_taps, u8 rotation,
1734                                       enum omap_color_component color_comp)
1735 {
1736         int fir_hinc, fir_vinc;
1737
1738         fir_hinc = 1024 * orig_width / out_width;
1739         fir_vinc = 1024 * orig_height / out_height;
1740
1741         dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps,
1742                                  color_comp);
1743         dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp);
1744 }
1745
1746 static void dispc_ovl_set_accu_uv(struct dispc_device *dispc,
1747                                   enum omap_plane_id plane,
1748                                   u16 orig_width, u16 orig_height,
1749                                   u16 out_width, u16 out_height,
1750                                   bool ilace, u32 fourcc, u8 rotation)
1751 {
1752         int h_accu2_0, h_accu2_1;
1753         int v_accu2_0, v_accu2_1;
1754         int chroma_hinc, chroma_vinc;
1755         int idx;
1756
1757         struct accu {
1758                 s8 h0_m, h0_n;
1759                 s8 h1_m, h1_n;
1760                 s8 v0_m, v0_n;
1761                 s8 v1_m, v1_n;
1762         };
1763
1764         const struct accu *accu_table;
1765         const struct accu *accu_val;
1766
1767         static const struct accu accu_nv12[4] = {
1768                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1769                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1770                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1771                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1772         };
1773
1774         static const struct accu accu_nv12_ilace[4] = {
1775                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1776                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1777                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1778                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1779         };
1780
1781         static const struct accu accu_yuv[4] = {
1782                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1783                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1784                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1785                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1786         };
1787
1788         /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */
1789         switch (rotation & DRM_MODE_ROTATE_MASK) {
1790         default:
1791         case DRM_MODE_ROTATE_0:
1792                 idx = 0;
1793                 break;
1794         case DRM_MODE_ROTATE_90:
1795                 idx = 3;
1796                 break;
1797         case DRM_MODE_ROTATE_180:
1798                 idx = 2;
1799                 break;
1800         case DRM_MODE_ROTATE_270:
1801                 idx = 1;
1802                 break;
1803         }
1804
1805         switch (fourcc) {
1806         case DRM_FORMAT_NV12:
1807                 if (ilace)
1808                         accu_table = accu_nv12_ilace;
1809                 else
1810                         accu_table = accu_nv12;
1811                 break;
1812         case DRM_FORMAT_YUYV:
1813         case DRM_FORMAT_UYVY:
1814                 accu_table = accu_yuv;
1815                 break;
1816         default:
1817                 BUG();
1818                 return;
1819         }
1820
1821         accu_val = &accu_table[idx];
1822
1823         chroma_hinc = 1024 * orig_width / out_width;
1824         chroma_vinc = 1024 * orig_height / out_height;
1825
1826         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1827         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1828         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1829         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1830
1831         dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0);
1832         dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1);
1833 }
1834
1835 static void dispc_ovl_set_scaling_common(struct dispc_device *dispc,
1836                                          enum omap_plane_id plane,
1837                                          u16 orig_width, u16 orig_height,
1838                                          u16 out_width, u16 out_height,
1839                                          bool ilace, bool five_taps,
1840                                          bool fieldmode, u32 fourcc,
1841                                          u8 rotation)
1842 {
1843         int accu0 = 0;
1844         int accu1 = 0;
1845         u32 l;
1846
1847         dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1848                                   out_width, out_height, five_taps,
1849                                   rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1850         l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1851
1852         /* RESIZEENABLE and VERTICALTAPS */
1853         l &= ~((0x3 << 5) | (0x1 << 21));
1854         l |= (orig_width != out_width) ? (1 << 5) : 0;
1855         l |= (orig_height != out_height) ? (1 << 6) : 0;
1856         l |= five_taps ? (1 << 21) : 0;
1857
1858         /* VRESIZECONF and HRESIZECONF */
1859         if (dispc_has_feature(dispc, FEAT_RESIZECONF)) {
1860                 l &= ~(0x3 << 7);
1861                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1862                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1863         }
1864
1865         /* LINEBUFFERSPLIT */
1866         if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) {
1867                 l &= ~(0x1 << 22);
1868                 l |= five_taps ? (1 << 22) : 0;
1869         }
1870
1871         dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
1872
1873         /*
1874          * field 0 = even field = bottom field
1875          * field 1 = odd field = top field
1876          */
1877         if (ilace && !fieldmode) {
1878                 accu1 = 0;
1879                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1880                 if (accu0 >= 1024/2) {
1881                         accu1 = 1024/2;
1882                         accu0 -= accu1;
1883                 }
1884         }
1885
1886         dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0);
1887         dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1);
1888 }
1889
1890 static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc,
1891                                      enum omap_plane_id plane,
1892                                      u16 orig_width, u16 orig_height,
1893                                      u16 out_width, u16 out_height,
1894                                      bool ilace, bool five_taps,
1895                                      bool fieldmode, u32 fourcc,
1896                                      u8 rotation)
1897 {
1898         int scale_x = out_width != orig_width;
1899         int scale_y = out_height != orig_height;
1900         bool chroma_upscale = plane != OMAP_DSS_WB;
1901         const struct drm_format_info *info;
1902
1903         info = drm_format_info(fourcc);
1904
1905         if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE))
1906                 return;
1907
1908         if (!info->is_yuv) {
1909                 /* reset chroma resampling for RGB formats  */
1910                 if (plane != OMAP_DSS_WB)
1911                         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1912                                     0, 8, 8);
1913                 return;
1914         }
1915
1916         dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width,
1917                               out_height, ilace, fourcc, rotation);
1918
1919         switch (fourcc) {
1920         case DRM_FORMAT_NV12:
1921                 if (chroma_upscale) {
1922                         /* UV is subsampled by 2 horizontally and vertically */
1923                         orig_height >>= 1;
1924                         orig_width >>= 1;
1925                 } else {
1926                         /* UV is downsampled by 2 horizontally and vertically */
1927                         orig_height <<= 1;
1928                         orig_width <<= 1;
1929                 }
1930
1931                 break;
1932         case DRM_FORMAT_YUYV:
1933         case DRM_FORMAT_UYVY:
1934                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1935                 if (!drm_rotation_90_or_270(rotation)) {
1936                         if (chroma_upscale)
1937                                 /* UV is subsampled by 2 horizontally */
1938                                 orig_width >>= 1;
1939                         else
1940                                 /* UV is downsampled by 2 horizontally */
1941                                 orig_width <<= 1;
1942                 }
1943
1944                 /* must use FIR for YUV422 if rotated */
1945                 if ((rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0)
1946                         scale_x = scale_y = true;
1947
1948                 break;
1949         default:
1950                 BUG();
1951                 return;
1952         }
1953
1954         if (out_width != orig_width)
1955                 scale_x = true;
1956         if (out_height != orig_height)
1957                 scale_y = true;
1958
1959         dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1960                                   out_width, out_height, five_taps,
1961                                   rotation, DISPC_COLOR_COMPONENT_UV);
1962
1963         if (plane != OMAP_DSS_WB)
1964                 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1965                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1966
1967         /* set H scaling */
1968         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1969         /* set V scaling */
1970         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1971 }
1972
1973 static void dispc_ovl_set_scaling(struct dispc_device *dispc,
1974                                   enum omap_plane_id plane,
1975                                   u16 orig_width, u16 orig_height,
1976                                   u16 out_width, u16 out_height,
1977                                   bool ilace, bool five_taps,
1978                                   bool fieldmode, u32 fourcc,
1979                                   u8 rotation)
1980 {
1981         BUG_ON(plane == OMAP_DSS_GFX);
1982
1983         dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height,
1984                                      out_width, out_height, ilace, five_taps,
1985                                      fieldmode, fourcc, rotation);
1986
1987         dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height,
1988                                  out_width, out_height, ilace, five_taps,
1989                                  fieldmode, fourcc, rotation);
1990 }
1991
1992 static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc,
1993                                          enum omap_plane_id plane, u8 rotation,
1994                                          enum omap_dss_rotation_type rotation_type,
1995                                          u32 fourcc)
1996 {
1997         bool row_repeat = false;
1998         int vidrot = 0;
1999
2000         /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */
2001         if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) {
2002
2003                 if (rotation & DRM_MODE_REFLECT_X) {
2004                         switch (rotation & DRM_MODE_ROTATE_MASK) {
2005                         case DRM_MODE_ROTATE_0:
2006                                 vidrot = 2;
2007                                 break;
2008                         case DRM_MODE_ROTATE_90:
2009                                 vidrot = 1;
2010                                 break;
2011                         case DRM_MODE_ROTATE_180:
2012                                 vidrot = 0;
2013                                 break;
2014                         case DRM_MODE_ROTATE_270:
2015                                 vidrot = 3;
2016                                 break;
2017                         }
2018                 } else {
2019                         switch (rotation & DRM_MODE_ROTATE_MASK) {
2020                         case DRM_MODE_ROTATE_0:
2021                                 vidrot = 0;
2022                                 break;
2023                         case DRM_MODE_ROTATE_90:
2024                                 vidrot = 3;
2025                                 break;
2026                         case DRM_MODE_ROTATE_180:
2027                                 vidrot = 2;
2028                                 break;
2029                         case DRM_MODE_ROTATE_270:
2030                                 vidrot = 1;
2031                                 break;
2032                         }
2033                 }
2034
2035                 if (drm_rotation_90_or_270(rotation))
2036                         row_repeat = true;
2037                 else
2038                         row_repeat = false;
2039         }
2040
2041         /*
2042          * OMAP4/5 Errata i631:
2043          * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
2044          * rows beyond the framebuffer, which may cause OCP error.
2045          */
2046         if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER)
2047                 vidrot = 1;
2048
2049         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
2050         if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE))
2051                 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
2052                         row_repeat ? 1 : 0, 18, 18);
2053
2054         if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) {
2055                 bool doublestride =
2056                         fourcc == DRM_FORMAT_NV12 &&
2057                         rotation_type == OMAP_DSS_ROT_TILER &&
2058                         !drm_rotation_90_or_270(rotation);
2059
2060                 /* DOUBLESTRIDE */
2061                 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
2062                             doublestride, 22, 22);
2063         }
2064 }
2065
2066 static int color_mode_to_bpp(u32 fourcc)
2067 {
2068         switch (fourcc) {
2069         case DRM_FORMAT_NV12:
2070                 return 8;
2071         case DRM_FORMAT_RGBX4444:
2072         case DRM_FORMAT_RGB565:
2073         case DRM_FORMAT_ARGB4444:
2074         case DRM_FORMAT_YUYV:
2075         case DRM_FORMAT_UYVY:
2076         case DRM_FORMAT_RGBA4444:
2077         case DRM_FORMAT_XRGB4444:
2078         case DRM_FORMAT_ARGB1555:
2079         case DRM_FORMAT_XRGB1555:
2080                 return 16;
2081         case DRM_FORMAT_RGB888:
2082                 return 24;
2083         case DRM_FORMAT_XRGB8888:
2084         case DRM_FORMAT_ARGB8888:
2085         case DRM_FORMAT_RGBA8888:
2086         case DRM_FORMAT_RGBX8888:
2087                 return 32;
2088         default:
2089                 BUG();
2090                 return 0;
2091         }
2092 }
2093
2094 static s32 pixinc(int pixels, u8 ps)
2095 {
2096         if (pixels == 1)
2097                 return 1;
2098         else if (pixels > 1)
2099                 return 1 + (pixels - 1) * ps;
2100         else if (pixels < 0)
2101                 return 1 - (-pixels + 1) * ps;
2102         else
2103                 BUG();
2104                 return 0;
2105 }
2106
2107 static void calc_offset(u16 screen_width, u16 width,
2108                 u32 fourcc, bool fieldmode, unsigned int field_offset,
2109                 unsigned int *offset0, unsigned int *offset1,
2110                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim,
2111                 enum omap_dss_rotation_type rotation_type, u8 rotation)
2112 {
2113         u8 ps;
2114
2115         ps = color_mode_to_bpp(fourcc) / 8;
2116
2117         DSSDBG("scrw %d, width %d\n", screen_width, width);
2118
2119         if (rotation_type == OMAP_DSS_ROT_TILER &&
2120             (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) &&
2121             drm_rotation_90_or_270(rotation)) {
2122                 /*
2123                  * HACK: ROW_INC needs to be calculated with TILER units.
2124                  * We get such 'screen_width' that multiplying it with the
2125                  * YUV422 pixel size gives the correct TILER container width.
2126                  * However, 'width' is in pixels and multiplying it with YUV422
2127                  * pixel size gives incorrect result. We thus multiply it here
2128                  * with 2 to match the 32 bit TILER unit size.
2129                  */
2130                 width *= 2;
2131         }
2132
2133         /*
2134          * field 0 = even field = bottom field
2135          * field 1 = odd field = top field
2136          */
2137         *offset0 = field_offset * screen_width * ps;
2138         *offset1 = 0;
2139
2140         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2141                         (fieldmode ? screen_width : 0), ps);
2142         if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY)
2143                 *pix_inc = pixinc(x_predecim, 2 * ps);
2144         else
2145                 *pix_inc = pixinc(x_predecim, ps);
2146 }
2147
2148 /*
2149  * This function is used to avoid synclosts in OMAP3, because of some
2150  * undocumented horizontal position and timing related limitations.
2151  */
2152 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2153                 const struct videomode *vm, u16 pos_x,
2154                 u16 width, u16 height, u16 out_width, u16 out_height,
2155                 bool five_taps)
2156 {
2157         const int ds = DIV_ROUND_UP(height, out_height);
2158         unsigned long nonactive;
2159         static const u8 limits[3] = { 8, 10, 20 };
2160         u64 val, blank;
2161         int i;
2162
2163         nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len +
2164                     vm->hback_porch - out_width;
2165
2166         i = 0;
2167         if (out_height < height)
2168                 i++;
2169         if (out_width < width)
2170                 i++;
2171         blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) *
2172                         lclk, pclk);
2173         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2174         if (blank <= limits[i])
2175                 return -EINVAL;
2176
2177         /* FIXME add checks for 3-tap filter once the limitations are known */
2178         if (!five_taps)
2179                 return 0;
2180
2181         /*
2182          * Pixel data should be prepared before visible display point starts.
2183          * So, atleast DS-2 lines must have already been fetched by DISPC
2184          * during nonactive - pos_x period.
2185          */
2186         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2187         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2188                 val, max(0, ds - 2) * width);
2189         if (val < max(0, ds - 2) * width)
2190                 return -EINVAL;
2191
2192         /*
2193          * All lines need to be refilled during the nonactive period of which
2194          * only one line can be loaded during the active period. So, atleast
2195          * DS - 1 lines should be loaded during nonactive period.
2196          */
2197         val =  div_u64((u64)nonactive * lclk, pclk);
2198         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2199                 val, max(0, ds - 1) * width);
2200         if (val < max(0, ds - 1) * width)
2201                 return -EINVAL;
2202
2203         return 0;
2204 }
2205
2206 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2207                 const struct videomode *vm, u16 width,
2208                 u16 height, u16 out_width, u16 out_height,
2209                 u32 fourcc)
2210 {
2211         u32 core_clk = 0;
2212         u64 tmp;
2213
2214         if (height <= out_height && width <= out_width)
2215                 return (unsigned long) pclk;
2216
2217         if (height > out_height) {
2218                 unsigned int ppl = vm->hactive;
2219
2220                 tmp = (u64)pclk * height * out_width;
2221                 do_div(tmp, 2 * out_height * ppl);
2222                 core_clk = tmp;
2223
2224                 if (height > 2 * out_height) {
2225                         if (ppl == out_width)
2226                                 return 0;
2227
2228                         tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2229                         do_div(tmp, 2 * out_height * (ppl - out_width));
2230                         core_clk = max_t(u32, core_clk, tmp);
2231                 }
2232         }
2233
2234         if (width > out_width) {
2235                 tmp = (u64)pclk * width;
2236                 do_div(tmp, out_width);
2237                 core_clk = max_t(u32, core_clk, tmp);
2238
2239                 if (fourcc == DRM_FORMAT_XRGB8888)
2240                         core_clk <<= 1;
2241         }
2242
2243         return core_clk;
2244 }
2245
2246 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2247                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2248 {
2249         if (height > out_height && width > out_width)
2250                 return pclk * 4;
2251         else
2252                 return pclk * 2;
2253 }
2254
2255 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2256                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2257 {
2258         unsigned int hf, vf;
2259
2260         /*
2261          * FIXME how to determine the 'A' factor
2262          * for the no downscaling case ?
2263          */
2264
2265         if (width > 3 * out_width)
2266                 hf = 4;
2267         else if (width > 2 * out_width)
2268                 hf = 3;
2269         else if (width > out_width)
2270                 hf = 2;
2271         else
2272                 hf = 1;
2273         if (height > out_height)
2274                 vf = 2;
2275         else
2276                 vf = 1;
2277
2278         return pclk * vf * hf;
2279 }
2280
2281 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2282                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2283 {
2284         /*
2285          * If the overlay/writeback is in mem to mem mode, there are no
2286          * downscaling limitations with respect to pixel clock, return 1 as
2287          * required core clock to represent that we have sufficient enough
2288          * core clock to do maximum downscaling
2289          */
2290         if (mem_to_mem)
2291                 return 1;
2292
2293         if (width > out_width)
2294                 return DIV_ROUND_UP(pclk, out_width) * width;
2295         else
2296                 return pclk;
2297 }
2298
2299 static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc,
2300                                        unsigned long pclk, unsigned long lclk,
2301                                        const struct videomode *vm,
2302                                        u16 width, u16 height,
2303                                        u16 out_width, u16 out_height,
2304                                        u32 fourcc, bool *five_taps,
2305                                        int *x_predecim, int *y_predecim,
2306                                        int *decim_x, int *decim_y,
2307                                        u16 pos_x, unsigned long *core_clk,
2308                                        bool mem_to_mem)
2309 {
2310         int error;
2311         u16 in_width, in_height;
2312         int min_factor = min(*decim_x, *decim_y);
2313         const int maxsinglelinewidth = dispc->feat->max_line_width;
2314
2315         *five_taps = false;
2316
2317         do {
2318                 in_height = height / *decim_y;
2319                 in_width = width / *decim_x;
2320                 *core_clk = dispc->feat->calc_core_clk(pclk, in_width,
2321                                 in_height, out_width, out_height, mem_to_mem);
2322                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2323                         *core_clk > dispc_core_clk_rate(dispc));
2324                 if (error) {
2325                         if (*decim_x == *decim_y) {
2326                                 *decim_x = min_factor;
2327                                 ++*decim_y;
2328                         } else {
2329                                 swap(*decim_x, *decim_y);
2330                                 if (*decim_x < *decim_y)
2331                                         ++*decim_x;
2332                         }
2333                 }
2334         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2335
2336         if (error) {
2337                 DSSERR("failed to find scaling settings\n");
2338                 return -EINVAL;
2339         }
2340
2341         if (in_width > maxsinglelinewidth) {
2342                 DSSERR("Cannot scale max input width exceeded\n");
2343                 return -EINVAL;
2344         }
2345         return 0;
2346 }
2347
2348 static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc,
2349                                        unsigned long pclk, unsigned long lclk,
2350                                        const struct videomode *vm,
2351                                        u16 width, u16 height,
2352                                        u16 out_width, u16 out_height,
2353                                        u32 fourcc, bool *five_taps,
2354                                        int *x_predecim, int *y_predecim,
2355                                        int *decim_x, int *decim_y,
2356                                        u16 pos_x, unsigned long *core_clk,
2357                                        bool mem_to_mem)
2358 {
2359         int error;
2360         u16 in_width, in_height;
2361         const int maxsinglelinewidth = dispc->feat->max_line_width;
2362
2363         do {
2364                 in_height = height / *decim_y;
2365                 in_width = width / *decim_x;
2366                 *five_taps = in_height > out_height;
2367
2368                 if (in_width > maxsinglelinewidth)
2369                         if (in_height > out_height &&
2370                                                 in_height < out_height * 2)
2371                                 *five_taps = false;
2372 again:
2373                 if (*five_taps)
2374                         *core_clk = calc_core_clk_five_taps(pclk, vm,
2375                                                 in_width, in_height, out_width,
2376                                                 out_height, fourcc);
2377                 else
2378                         *core_clk = dispc->feat->calc_core_clk(pclk, in_width,
2379                                         in_height, out_width, out_height,
2380                                         mem_to_mem);
2381
2382                 error = check_horiz_timing_omap3(pclk, lclk, vm,
2383                                 pos_x, in_width, in_height, out_width,
2384                                 out_height, *five_taps);
2385                 if (error && *five_taps) {
2386                         *five_taps = false;
2387                         goto again;
2388                 }
2389
2390                 error = (error || in_width > maxsinglelinewidth * 2 ||
2391                         (in_width > maxsinglelinewidth && *five_taps) ||
2392                         !*core_clk || *core_clk > dispc_core_clk_rate(dispc));
2393
2394                 if (!error) {
2395                         /* verify that we're inside the limits of scaler */
2396                         if (in_width / 4 > out_width)
2397                                         error = 1;
2398
2399                         if (*five_taps) {
2400                                 if (in_height / 4 > out_height)
2401                                         error = 1;
2402                         } else {
2403                                 if (in_height / 2 > out_height)
2404                                         error = 1;
2405                         }
2406                 }
2407
2408                 if (error)
2409                         ++*decim_y;
2410         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2411
2412         if (error) {
2413                 DSSERR("failed to find scaling settings\n");
2414                 return -EINVAL;
2415         }
2416
2417         if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width,
2418                                 in_height, out_width, out_height, *five_taps)) {
2419                         DSSERR("horizontal timing too tight\n");
2420                         return -EINVAL;
2421         }
2422
2423         if (in_width > (maxsinglelinewidth * 2)) {
2424                 DSSERR("Cannot setup scaling\n");
2425                 DSSERR("width exceeds maximum width possible\n");
2426                 return -EINVAL;
2427         }
2428
2429         if (in_width > maxsinglelinewidth && *five_taps) {
2430                 DSSERR("cannot setup scaling with five taps\n");
2431                 return -EINVAL;
2432         }
2433         return 0;
2434 }
2435
2436 static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc,
2437                                        unsigned long pclk, unsigned long lclk,
2438                                        const struct videomode *vm,
2439                                        u16 width, u16 height,
2440                                        u16 out_width, u16 out_height,
2441                                        u32 fourcc, bool *five_taps,
2442                                        int *x_predecim, int *y_predecim,
2443                                        int *decim_x, int *decim_y,
2444                                        u16 pos_x, unsigned long *core_clk,
2445                                        bool mem_to_mem)
2446 {
2447         u16 in_width, in_width_max;
2448         int decim_x_min = *decim_x;
2449         u16 in_height = height / *decim_y;
2450         const int maxsinglelinewidth = dispc->feat->max_line_width;
2451         const int maxdownscale = dispc->feat->max_downscale;
2452
2453         if (mem_to_mem) {
2454                 in_width_max = out_width * maxdownscale;
2455         } else {
2456                 in_width_max = dispc_core_clk_rate(dispc)
2457                              / DIV_ROUND_UP(pclk, out_width);
2458         }
2459
2460         *decim_x = DIV_ROUND_UP(width, in_width_max);
2461
2462         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2463         if (*decim_x > *x_predecim)
2464                 return -EINVAL;
2465
2466         do {
2467                 in_width = width / *decim_x;
2468         } while (*decim_x <= *x_predecim &&
2469                         in_width > maxsinglelinewidth && ++*decim_x);
2470
2471         if (in_width > maxsinglelinewidth) {
2472                 DSSERR("Cannot scale width exceeds max line width\n");
2473                 return -EINVAL;
2474         }
2475
2476         if (*decim_x > 4 && fourcc != DRM_FORMAT_NV12) {
2477                 /*
2478                  * Let's disable all scaling that requires horizontal
2479                  * decimation with higher factor than 4, until we have
2480                  * better estimates of what we can and can not
2481                  * do. However, NV12 color format appears to work Ok
2482                  * with all decimation factors.
2483                  *
2484                  * When decimating horizontally by more that 4 the dss
2485                  * is not able to fetch the data in burst mode. When
2486                  * this happens it is hard to tell if there enough
2487                  * bandwidth. Despite what theory says this appears to
2488                  * be true also for 16-bit color formats.
2489                  */
2490                 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)\n", *decim_x);
2491
2492                 return -EINVAL;
2493         }
2494
2495         *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height,
2496                                 out_width, out_height, mem_to_mem);
2497         return 0;
2498 }
2499
2500 #define DIV_FRAC(dividend, divisor) \
2501         ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2502
2503 static int dispc_ovl_calc_scaling(struct dispc_device *dispc,
2504                                   enum omap_plane_id plane,
2505                                   unsigned long pclk, unsigned long lclk,
2506                                   enum omap_overlay_caps caps,
2507                                   const struct videomode *vm,
2508                                   u16 width, u16 height,
2509                                   u16 out_width, u16 out_height,
2510                                   u32 fourcc, bool *five_taps,
2511                                   int *x_predecim, int *y_predecim, u16 pos_x,
2512                                   enum omap_dss_rotation_type rotation_type,
2513                                   bool mem_to_mem)
2514 {
2515         int maxhdownscale = dispc->feat->max_downscale;
2516         int maxvdownscale = dispc->feat->max_downscale;
2517         const int max_decim_limit = 16;
2518         unsigned long core_clk = 0;
2519         int decim_x, decim_y, ret;
2520
2521         if (width == out_width && height == out_height)
2522                 return 0;
2523
2524         if (plane == OMAP_DSS_WB) {
2525                 switch (fourcc) {
2526                 case DRM_FORMAT_NV12:
2527                         maxhdownscale = maxvdownscale = 2;
2528                         break;
2529                 case DRM_FORMAT_YUYV:
2530                 case DRM_FORMAT_UYVY:
2531                         maxhdownscale = 2;
2532                         maxvdownscale = 4;
2533                         break;
2534                 default:
2535                         break;
2536                 }
2537         }
2538         if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) {
2539                 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2540                 return -EINVAL;
2541         }
2542
2543         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2544                 return -EINVAL;
2545
2546         if (mem_to_mem) {
2547                 *x_predecim = *y_predecim = 1;
2548         } else {
2549                 *x_predecim = max_decim_limit;
2550                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2551                                 dispc_has_feature(dispc, FEAT_BURST_2D)) ?
2552                                 2 : max_decim_limit;
2553         }
2554
2555         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxhdownscale);
2556         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxvdownscale);
2557
2558         if (decim_x > *x_predecim || out_width > width * 8)
2559                 return -EINVAL;
2560
2561         if (decim_y > *y_predecim || out_height > height * 8)
2562                 return -EINVAL;
2563
2564         ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height,
2565                                         out_width, out_height, fourcc,
2566                                         five_taps, x_predecim, y_predecim,
2567                                         &decim_x, &decim_y, pos_x, &core_clk,
2568                                         mem_to_mem);
2569         if (ret)
2570                 return ret;
2571
2572         DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2573                 width, height,
2574                 out_width, out_height,
2575                 out_width / width, DIV_FRAC(out_width, width),
2576                 out_height / height, DIV_FRAC(out_height, height),
2577
2578                 decim_x, decim_y,
2579                 width / decim_x, height / decim_y,
2580                 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2581                 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2582
2583                 *five_taps ? 5 : 3,
2584                 core_clk, dispc_core_clk_rate(dispc));
2585
2586         if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) {
2587                 DSSERR("failed to set up scaling, "
2588                         "required core clk rate = %lu Hz, "
2589                         "current core clk rate = %lu Hz\n",
2590                         core_clk, dispc_core_clk_rate(dispc));
2591                 return -EINVAL;
2592         }
2593
2594         *x_predecim = decim_x;
2595         *y_predecim = decim_y;
2596         return 0;
2597 }
2598
2599 static int dispc_ovl_setup_common(struct dispc_device *dispc,
2600                                   enum omap_plane_id plane,
2601                                   enum omap_overlay_caps caps,
2602                                   u32 paddr, u32 p_uv_addr,
2603                                   u16 screen_width, int pos_x, int pos_y,
2604                                   u16 width, u16 height,
2605                                   u16 out_width, u16 out_height,
2606                                   u32 fourcc, u8 rotation, u8 zorder,
2607                                   u8 pre_mult_alpha, u8 global_alpha,
2608                                   enum omap_dss_rotation_type rotation_type,
2609                                   bool replication, const struct videomode *vm,
2610                                   bool mem_to_mem)
2611 {
2612         bool five_taps = true;
2613         bool fieldmode = false;
2614         int r, cconv = 0;
2615         unsigned int offset0, offset1;
2616         s32 row_inc;
2617         s32 pix_inc;
2618         u16 frame_width;
2619         unsigned int field_offset = 0;
2620         u16 in_height = height;
2621         u16 in_width = width;
2622         int x_predecim = 1, y_predecim = 1;
2623         bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED);
2624         unsigned long pclk = dispc_plane_pclk_rate(dispc, plane);
2625         unsigned long lclk = dispc_plane_lclk_rate(dispc, plane);
2626         const struct drm_format_info *info;
2627
2628         info = drm_format_info(fourcc);
2629
2630         /* when setting up WB, dispc_plane_pclk_rate() returns 0 */
2631         if (plane == OMAP_DSS_WB)
2632                 pclk = vm->pixelclock;
2633
2634         if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2635                 return -EINVAL;
2636
2637         if (info->is_yuv && (in_width & 1)) {
2638                 DSSERR("input width %d is not even for YUV format\n", in_width);
2639                 return -EINVAL;
2640         }
2641
2642         out_width = out_width == 0 ? width : out_width;
2643         out_height = out_height == 0 ? height : out_height;
2644
2645         if (plane != OMAP_DSS_WB) {
2646                 if (ilace && height == out_height)
2647                         fieldmode = true;
2648
2649                 if (ilace) {
2650                         if (fieldmode)
2651                                 in_height /= 2;
2652                         pos_y /= 2;
2653                         out_height /= 2;
2654
2655                         DSSDBG("adjusting for ilace: height %d, pos_y %d, out_height %d\n",
2656                                 in_height, pos_y, out_height);
2657                 }
2658         }
2659
2660         if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc))
2661                 return -EINVAL;
2662
2663         r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width,
2664                                    in_height, out_width, out_height, fourcc,
2665                                    &five_taps, &x_predecim, &y_predecim, pos_x,
2666                                    rotation_type, mem_to_mem);
2667         if (r)
2668                 return r;
2669
2670         in_width = in_width / x_predecim;
2671         in_height = in_height / y_predecim;
2672
2673         if (x_predecim > 1 || y_predecim > 1)
2674                 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2675                         x_predecim, y_predecim, in_width, in_height);
2676
2677         if (info->is_yuv && (in_width & 1)) {
2678                 DSSDBG("predecimated input width is not even for YUV format\n");
2679                 DSSDBG("adjusting input width %d -> %d\n",
2680                         in_width, in_width & ~1);
2681
2682                 in_width &= ~1;
2683         }
2684
2685         if (info->is_yuv)
2686                 cconv = 1;
2687
2688         if (ilace && !fieldmode) {
2689                 /*
2690                  * when downscaling the bottom field may have to start several
2691                  * source lines below the top field. Unfortunately ACCUI
2692                  * registers will only hold the fractional part of the offset
2693                  * so the integer part must be added to the base address of the
2694                  * bottom field.
2695                  */
2696                 if (!in_height || in_height == out_height)
2697                         field_offset = 0;
2698                 else
2699                         field_offset = in_height / out_height / 2;
2700         }
2701
2702         /* Fields are independent but interleaved in memory. */
2703         if (fieldmode)
2704                 field_offset = 1;
2705
2706         offset0 = 0;
2707         offset1 = 0;
2708         row_inc = 0;
2709         pix_inc = 0;
2710
2711         if (plane == OMAP_DSS_WB)
2712                 frame_width = out_width;
2713         else
2714                 frame_width = in_width;
2715
2716         calc_offset(screen_width, frame_width,
2717                         fourcc, fieldmode, field_offset,
2718                         &offset0, &offset1, &row_inc, &pix_inc,
2719                         x_predecim, y_predecim,
2720                         rotation_type, rotation);
2721
2722         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2723                         offset0, offset1, row_inc, pix_inc);
2724
2725         dispc_ovl_set_color_mode(dispc, plane, fourcc);
2726
2727         dispc_ovl_configure_burst_type(dispc, plane, rotation_type);
2728
2729         if (dispc->feat->reverse_ilace_field_order)
2730                 swap(offset0, offset1);
2731
2732         dispc_ovl_set_ba0(dispc, plane, paddr + offset0);
2733         dispc_ovl_set_ba1(dispc, plane, paddr + offset1);
2734
2735         if (fourcc == DRM_FORMAT_NV12) {
2736                 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0);
2737                 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1);
2738         }
2739
2740         if (dispc->feat->last_pixel_inc_missing)
2741                 row_inc += pix_inc - 1;
2742
2743         dispc_ovl_set_row_inc(dispc, plane, row_inc);
2744         dispc_ovl_set_pix_inc(dispc, plane, pix_inc);
2745
2746         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2747                         in_height, out_width, out_height);
2748
2749         dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y);
2750
2751         dispc_ovl_set_input_size(dispc, plane, in_width, in_height);
2752
2753         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2754                 dispc_ovl_set_scaling(dispc, plane, in_width, in_height,
2755                                       out_width, out_height, ilace, five_taps,
2756                                       fieldmode, fourcc, rotation);
2757                 dispc_ovl_set_output_size(dispc, plane, out_width, out_height);
2758                 dispc_ovl_set_vid_color_conv(dispc, plane, cconv);
2759         }
2760
2761         dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type,
2762                                      fourcc);
2763
2764         dispc_ovl_set_zorder(dispc, plane, caps, zorder);
2765         dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha);
2766         dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha);
2767
2768         dispc_ovl_enable_replication(dispc, plane, caps, replication);
2769
2770         return 0;
2771 }
2772
2773 static int dispc_ovl_setup(struct dispc_device *dispc,
2774                            enum omap_plane_id plane,
2775                            const struct omap_overlay_info *oi,
2776                            const struct videomode *vm, bool mem_to_mem,
2777                            enum omap_channel channel)
2778 {
2779         int r;
2780         enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane];
2781         const bool replication = true;
2782
2783         DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2784                 " %dx%d, cmode %x, rot %d, chan %d repl %d\n",
2785                 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2786                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2787                 oi->fourcc, oi->rotation, channel, replication);
2788
2789         dispc_ovl_set_channel_out(dispc, plane, channel);
2790
2791         r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr,
2792                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2793                 oi->out_width, oi->out_height, oi->fourcc, oi->rotation,
2794                 oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2795                 oi->rotation_type, replication, vm, mem_to_mem);
2796
2797         return r;
2798 }
2799
2800 static int dispc_wb_setup(struct dispc_device *dispc,
2801                    const struct omap_dss_writeback_info *wi,
2802                    bool mem_to_mem, const struct videomode *vm,
2803                    enum dss_writeback_channel channel_in)
2804 {
2805         int r;
2806         u32 l;
2807         enum omap_plane_id plane = OMAP_DSS_WB;
2808         const int pos_x = 0, pos_y = 0;
2809         const u8 zorder = 0, global_alpha = 0;
2810         const bool replication = true;
2811         bool truncation;
2812         int in_width = vm->hactive;
2813         int in_height = vm->vactive;
2814         enum omap_overlay_caps caps =
2815                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2816
2817         if (vm->flags & DISPLAY_FLAGS_INTERLACED)
2818                 in_height /= 2;
2819
2820         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2821                 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width,
2822                 in_height, wi->width, wi->height, wi->fourcc, wi->rotation);
2823
2824         r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr,
2825                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2826                 wi->height, wi->fourcc, wi->rotation, zorder,
2827                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2828                 replication, vm, mem_to_mem);
2829         if (r)
2830                 return r;
2831
2832         switch (wi->fourcc) {
2833         case DRM_FORMAT_RGB565:
2834         case DRM_FORMAT_RGB888:
2835         case DRM_FORMAT_ARGB4444:
2836         case DRM_FORMAT_RGBA4444:
2837         case DRM_FORMAT_RGBX4444:
2838         case DRM_FORMAT_ARGB1555:
2839         case DRM_FORMAT_XRGB1555:
2840         case DRM_FORMAT_XRGB4444:
2841                 truncation = true;
2842                 break;
2843         default:
2844                 truncation = false;
2845                 break;
2846         }
2847
2848         /* setup extra DISPC_WB_ATTRIBUTES */
2849         l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
2850         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2851         l = FLD_MOD(l, channel_in, 18, 16);     /* CHANNELIN */
2852         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2853         if (mem_to_mem)
2854                 l = FLD_MOD(l, 1, 26, 24);      /* CAPTUREMODE */
2855         else
2856                 l = FLD_MOD(l, 0, 26, 24);      /* CAPTUREMODE */
2857         dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
2858
2859         if (mem_to_mem) {
2860                 /* WBDELAYCOUNT */
2861                 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2862         } else {
2863                 u32 wbdelay;
2864
2865                 if (channel_in == DSS_WB_TV_MGR)
2866                         wbdelay = vm->vsync_len + vm->vback_porch;
2867                 else
2868                         wbdelay = vm->vfront_porch + vm->vsync_len +
2869                                 vm->vback_porch;
2870
2871                 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
2872                         wbdelay /= 2;
2873
2874                 wbdelay = min(wbdelay, 255u);
2875
2876                 /* WBDELAYCOUNT */
2877                 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2878         }
2879
2880         return 0;
2881 }
2882
2883 static bool dispc_has_writeback(struct dispc_device *dispc)
2884 {
2885         return dispc->feat->has_writeback;
2886 }
2887
2888 static int dispc_ovl_enable(struct dispc_device *dispc,
2889                             enum omap_plane_id plane, bool enable)
2890 {
2891         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2892
2893         REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2894
2895         return 0;
2896 }
2897
2898 static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc,
2899                                              bool act_high)
2900 {
2901         if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL))
2902                 return;
2903
2904         REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2905 }
2906
2907 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable)
2908 {
2909         if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL))
2910                 return;
2911
2912         REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2913 }
2914
2915 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable)
2916 {
2917         if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE))
2918                 return;
2919
2920         REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2921 }
2922
2923 static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc,
2924                                            enum omap_channel channel,
2925                                            bool enable)
2926 {
2927         mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2928 }
2929
2930
2931 static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc,
2932                                        enum omap_channel channel)
2933 {
2934         mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1);
2935 }
2936
2937 static void dispc_set_loadmode(struct dispc_device *dispc,
2938                                enum omap_dss_load_mode mode)
2939 {
2940         REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1);
2941 }
2942
2943
2944 static void dispc_mgr_set_default_color(struct dispc_device *dispc,
2945                                         enum omap_channel channel, u32 color)
2946 {
2947         dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color);
2948 }
2949
2950 static void dispc_mgr_set_trans_key(struct dispc_device *dispc,
2951                                     enum omap_channel ch,
2952                                     enum omap_dss_trans_key_type type,
2953                                     u32 trans_key)
2954 {
2955         mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type);
2956
2957         dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key);
2958 }
2959
2960 static void dispc_mgr_enable_trans_key(struct dispc_device *dispc,
2961                                        enum omap_channel ch, bool enable)
2962 {
2963         mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable);
2964 }
2965
2966 static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc,
2967                                                 enum omap_channel ch,
2968                                                 bool enable)
2969 {
2970         if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER))
2971                 return;
2972
2973         if (ch == OMAP_DSS_CHANNEL_LCD)
2974                 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18);
2975         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2976                 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19);
2977 }
2978
2979 static void dispc_mgr_setup(struct dispc_device *dispc,
2980                             enum omap_channel channel,
2981                             const struct omap_overlay_manager_info *info)
2982 {
2983         dispc_mgr_set_default_color(dispc, channel, info->default_color);
2984         dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type,
2985                                 info->trans_key);
2986         dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled);
2987         dispc_mgr_enable_alpha_fixed_zorder(dispc, channel,
2988                         info->partial_alpha_enabled);
2989         if (dispc_has_feature(dispc, FEAT_CPR)) {
2990                 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable);
2991                 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs);
2992         }
2993 }
2994
2995 static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc,
2996                                          enum omap_channel channel,
2997                                          u8 data_lines)
2998 {
2999         int code;
3000
3001         switch (data_lines) {
3002         case 12:
3003                 code = 0;
3004                 break;
3005         case 16:
3006                 code = 1;
3007                 break;
3008         case 18:
3009                 code = 2;
3010                 break;
3011         case 24:
3012                 code = 3;
3013                 break;
3014         default:
3015                 BUG();
3016                 return;
3017         }
3018
3019         mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code);
3020 }
3021
3022 static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc,
3023                                       enum dss_io_pad_mode mode)
3024 {
3025         u32 l;
3026         int gpout0, gpout1;
3027
3028         switch (mode) {
3029         case DSS_IO_PAD_MODE_RESET:
3030                 gpout0 = 0;
3031                 gpout1 = 0;
3032                 break;
3033         case DSS_IO_PAD_MODE_RFBI:
3034                 gpout0 = 1;
3035                 gpout1 = 0;
3036                 break;
3037         case DSS_IO_PAD_MODE_BYPASS:
3038                 gpout0 = 1;
3039                 gpout1 = 1;
3040                 break;
3041         default:
3042                 BUG();
3043                 return;
3044         }
3045
3046         l = dispc_read_reg(dispc, DISPC_CONTROL);
3047         l = FLD_MOD(l, gpout0, 15, 15);
3048         l = FLD_MOD(l, gpout1, 16, 16);
3049         dispc_write_reg(dispc, DISPC_CONTROL, l);
3050 }
3051
3052 static void dispc_mgr_enable_stallmode(struct dispc_device *dispc,
3053                                        enum omap_channel channel, bool enable)
3054 {
3055         mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable);
3056 }
3057
3058 static void dispc_mgr_set_lcd_config(struct dispc_device *dispc,
3059                                      enum omap_channel channel,
3060                                      const struct dss_lcd_mgr_config *config)
3061 {
3062         dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode);
3063
3064         dispc_mgr_enable_stallmode(dispc, channel, config->stallmode);
3065         dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck);
3066
3067         dispc_mgr_set_clock_div(dispc, channel, &config->clock_info);
3068
3069         dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width);
3070
3071         dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity);
3072
3073         dispc_mgr_set_lcd_type_tft(dispc, channel);
3074 }
3075
3076 static bool _dispc_mgr_size_ok(struct dispc_device *dispc,
3077                                u16 width, u16 height)
3078 {
3079         return width <= dispc->feat->mgr_width_max &&
3080                 height <= dispc->feat->mgr_height_max;
3081 }
3082
3083 static bool _dispc_lcd_timings_ok(struct dispc_device *dispc,
3084                                   int hsync_len, int hfp, int hbp,
3085                                   int vsw, int vfp, int vbp)
3086 {
3087         if (hsync_len < 1 || hsync_len > dispc->feat->sw_max ||
3088             hfp < 1 || hfp > dispc->feat->hp_max ||
3089             hbp < 1 || hbp > dispc->feat->hp_max ||
3090             vsw < 1 || vsw > dispc->feat->sw_max ||
3091             vfp < 0 || vfp > dispc->feat->vp_max ||
3092             vbp < 0 || vbp > dispc->feat->vp_max)
3093                 return false;
3094         return true;
3095 }
3096
3097 static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc,
3098                                enum omap_channel channel,
3099                                unsigned long pclk)
3100 {
3101         if (dss_mgr_is_lcd(channel))
3102                 return pclk <= dispc->feat->max_lcd_pclk;
3103         else
3104                 return pclk <= dispc->feat->max_tv_pclk;
3105 }
3106
3107 static int dispc_mgr_check_timings(struct dispc_device *dispc,
3108                                    enum omap_channel channel,
3109                                    const struct videomode *vm)
3110 {
3111         if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive))
3112                 return MODE_BAD;
3113
3114         if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock))
3115                 return MODE_BAD;
3116
3117         if (dss_mgr_is_lcd(channel)) {
3118                 /* TODO: OMAP4+ supports interlace for LCD outputs */
3119                 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
3120                         return MODE_BAD;
3121
3122                 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len,
3123                                 vm->hfront_porch, vm->hback_porch,
3124                                 vm->vsync_len, vm->vfront_porch,
3125                                 vm->vback_porch))
3126                         return MODE_BAD;
3127         }
3128
3129         return MODE_OK;
3130 }
3131
3132 static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc,
3133                                        enum omap_channel channel,
3134                                        const struct videomode *vm)
3135 {
3136         u32 timing_h, timing_v, l;
3137         bool onoff, rf, ipc, vs, hs, de;
3138
3139         timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) |
3140                    FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) |
3141                    FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20);
3142         timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) |
3143                    FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) |
3144                    FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20);
3145
3146         dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h);
3147         dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v);
3148
3149         if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
3150                 vs = false;
3151         else
3152                 vs = true;
3153
3154         if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
3155                 hs = false;
3156         else
3157                 hs = true;
3158
3159         if (vm->flags & DISPLAY_FLAGS_DE_HIGH)
3160                 de = false;
3161         else
3162                 de = true;
3163
3164         if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
3165                 ipc = false;
3166         else
3167                 ipc = true;
3168
3169         /* always use the 'rf' setting */
3170         onoff = true;
3171
3172         if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE)
3173                 rf = true;
3174         else
3175                 rf = false;
3176
3177         l = FLD_VAL(onoff, 17, 17) |
3178                 FLD_VAL(rf, 16, 16) |
3179                 FLD_VAL(de, 15, 15) |
3180                 FLD_VAL(ipc, 14, 14) |
3181                 FLD_VAL(hs, 13, 13) |
3182                 FLD_VAL(vs, 12, 12);
3183
3184         /* always set ALIGN bit when available */
3185         if (dispc->feat->supports_sync_align)
3186                 l |= (1 << 18);
3187
3188         dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l);
3189
3190         if (dispc->syscon_pol) {
3191                 const int shifts[] = {
3192                         [OMAP_DSS_CHANNEL_LCD] = 0,
3193                         [OMAP_DSS_CHANNEL_LCD2] = 1,
3194                         [OMAP_DSS_CHANNEL_LCD3] = 2,
3195                 };
3196
3197                 u32 mask, val;
3198
3199                 mask = (1 << 0) | (1 << 3) | (1 << 6);
3200                 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3201
3202                 mask <<= 16 + shifts[channel];
3203                 val <<= 16 + shifts[channel];
3204
3205                 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset,
3206                                    mask, val);
3207         }
3208 }
3209
3210 static int vm_flag_to_int(enum display_flags flags, enum display_flags high,
3211         enum display_flags low)
3212 {
3213         if (flags & high)
3214                 return 1;
3215         if (flags & low)
3216                 return -1;
3217         return 0;
3218 }
3219
3220 /* change name to mode? */
3221 static void dispc_mgr_set_timings(struct dispc_device *dispc,
3222                                   enum omap_channel channel,
3223                                   const struct videomode *vm)
3224 {
3225         unsigned int xtot, ytot;
3226         unsigned long ht, vt;
3227         struct videomode t = *vm;
3228
3229         DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
3230
3231         if (dispc_mgr_check_timings(dispc, channel, &t)) {
3232                 BUG();
3233                 return;
3234         }
3235
3236         if (dss_mgr_is_lcd(channel)) {
3237                 _dispc_mgr_set_lcd_timings(dispc, channel, &t);
3238
3239                 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
3240                 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;
3241
3242                 ht = vm->pixelclock / xtot;
3243                 vt = vm->pixelclock / xtot / ytot;
3244
3245                 DSSDBG("pck %lu\n", vm->pixelclock);
3246                 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3247                         t.hsync_len, t.hfront_porch, t.hback_porch,
3248                         t.vsync_len, t.vfront_porch, t.vback_porch);
3249                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3250                         vm_flag_to_int(t.flags, DISPLAY_FLAGS_VSYNC_HIGH, DISPLAY_FLAGS_VSYNC_LOW),
3251                         vm_flag_to_int(t.flags, DISPLAY_FLAGS_HSYNC_HIGH, DISPLAY_FLAGS_HSYNC_LOW),
3252                         vm_flag_to_int(t.flags, DISPLAY_FLAGS_PIXDATA_POSEDGE, DISPLAY_FLAGS_PIXDATA_NEGEDGE),
3253                         vm_flag_to_int(t.flags, DISPLAY_FLAGS_DE_HIGH, DISPLAY_FLAGS_DE_LOW),
3254                         vm_flag_to_int(t.flags, DISPLAY_FLAGS_SYNC_POSEDGE, DISPLAY_FLAGS_SYNC_NEGEDGE));
3255
3256                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3257         } else {
3258                 if (t.flags & DISPLAY_FLAGS_INTERLACED)
3259                         t.vactive /= 2;
3260
3261                 if (dispc->feat->supports_double_pixel)
3262                         REG_FLD_MOD(dispc, DISPC_CONTROL,
3263                                     !!(t.flags & DISPLAY_FLAGS_DOUBLECLK),
3264                                     19, 17);
3265         }
3266
3267         dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive);
3268 }
3269
3270 static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc,
3271                                       enum omap_channel channel, u16 lck_div,
3272                                       u16 pck_div)
3273 {
3274         BUG_ON(lck_div < 1);
3275         BUG_ON(pck_div < 1);
3276
3277         dispc_write_reg(dispc, DISPC_DIVISORo(channel),
3278                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3279
3280         if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) &&
3281                         channel == OMAP_DSS_CHANNEL_LCD)
3282                 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div;
3283 }
3284
3285 static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc,
3286                                       enum omap_channel channel, int *lck_div,
3287                                       int *pck_div)
3288 {
3289         u32 l;
3290         l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));
3291         *lck_div = FLD_GET(l, 23, 16);
3292         *pck_div = FLD_GET(l, 7, 0);
3293 }
3294
3295 static unsigned long dispc_fclk_rate(struct dispc_device *dispc)
3296 {
3297         unsigned long r;
3298         enum dss_clk_source src;
3299
3300         src = dss_get_dispc_clk_source(dispc->dss);
3301
3302         if (src == DSS_CLK_SRC_FCK) {
3303                 r = dss_get_dispc_clk_rate(dispc->dss);
3304         } else {
3305                 struct dss_pll *pll;
3306                 unsigned int clkout_idx;
3307
3308                 pll = dss_pll_find_by_src(dispc->dss, src);
3309                 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3310
3311                 r = pll->cinfo.clkout[clkout_idx];
3312         }
3313
3314         return r;
3315 }
3316
3317 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
3318                                          enum omap_channel channel)
3319 {
3320         int lcd;
3321         unsigned long r;
3322         enum dss_clk_source src;
3323
3324         /* for TV, LCLK rate is the FCLK rate */
3325         if (!dss_mgr_is_lcd(channel))
3326                 return dispc_fclk_rate(dispc);
3327
3328         src = dss_get_lcd_clk_source(dispc->dss, channel);
3329
3330         if (src == DSS_CLK_SRC_FCK) {
3331                 r = dss_get_dispc_clk_rate(dispc->dss);
3332         } else {
3333                 struct dss_pll *pll;
3334                 unsigned int clkout_idx;
3335
3336                 pll = dss_pll_find_by_src(dispc->dss, src);
3337                 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3338
3339                 r = pll->cinfo.clkout[clkout_idx];
3340         }
3341
3342         lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16);
3343
3344         return r / lcd;
3345 }
3346
3347 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
3348                                          enum omap_channel channel)
3349 {
3350         unsigned long r;
3351
3352         if (dss_mgr_is_lcd(channel)) {
3353                 int pcd;
3354                 u32 l;
3355
3356                 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));
3357
3358                 pcd = FLD_GET(l, 7, 0);
3359
3360                 r = dispc_mgr_lclk_rate(dispc, channel);
3361
3362                 return r / pcd;
3363         } else {
3364                 return dispc->tv_pclk_rate;
3365         }
3366 }
3367
3368 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk)
3369 {
3370         dispc->tv_pclk_rate = pclk;
3371 }
3372
3373 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc)
3374 {
3375         return dispc->core_clk_rate;
3376 }
3377
3378 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
3379                                            enum omap_plane_id plane)
3380 {
3381         enum omap_channel channel;
3382
3383         if (plane == OMAP_DSS_WB)
3384                 return 0;
3385
3386         channel = dispc_ovl_get_channel_out(dispc, plane);
3387
3388         return dispc_mgr_pclk_rate(dispc, channel);
3389 }
3390
3391 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
3392                                            enum omap_plane_id plane)
3393 {
3394         enum omap_channel channel;
3395
3396         if (plane == OMAP_DSS_WB)
3397                 return 0;
3398
3399         channel = dispc_ovl_get_channel_out(dispc, plane);
3400
3401         return dispc_mgr_lclk_rate(dispc, channel);
3402 }
3403
3404 static void dispc_dump_clocks_channel(struct dispc_device *dispc,
3405                                       struct seq_file *s,
3406                                       enum omap_channel channel)
3407 {
3408         int lcd, pcd;
3409         enum dss_clk_source lcd_clk_src;
3410
3411         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3412
3413         lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel);
3414
3415         seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
3416                 dss_get_clk_source_name(lcd_clk_src));
3417
3418         dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd);
3419
3420         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3421                 dispc_mgr_lclk_rate(dispc, channel), lcd);
3422         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3423                 dispc_mgr_pclk_rate(dispc, channel), pcd);
3424 }
3425
3426 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s)
3427 {
3428         enum dss_clk_source dispc_clk_src;
3429         int lcd;
3430         u32 l;
3431
3432         if (dispc_runtime_get(dispc))
3433                 return;
3434
3435         seq_printf(s, "- DISPC -\n");
3436
3437         dispc_clk_src = dss_get_dispc_clk_source(dispc->dss);
3438         seq_printf(s, "dispc fclk source = %s\n",
3439                         dss_get_clk_source_name(dispc_clk_src));
3440
3441         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc));
3442
3443         if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) {
3444                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3445                 l = dispc_read_reg(dispc, DISPC_DIVISOR);
3446                 lcd = FLD_GET(l, 23, 16);
3447
3448                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3449                                 (dispc_fclk_rate(dispc)/lcd), lcd);
3450         }
3451
3452         dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD);
3453
3454         if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
3455                 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2);
3456         if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
3457                 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3);
3458
3459         dispc_runtime_put(dispc);
3460 }
3461
3462 static int dispc_dump_regs(struct seq_file *s, void *p)
3463 {
3464         struct dispc_device *dispc = s->private;
3465         int i, j;
3466         const char *mgr_names[] = {
3467                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3468                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3469                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3470                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3471         };
3472         const char *ovl_names[] = {
3473                 [OMAP_DSS_GFX]          = "GFX",
3474                 [OMAP_DSS_VIDEO1]       = "VID1",
3475                 [OMAP_DSS_VIDEO2]       = "VID2",
3476                 [OMAP_DSS_VIDEO3]       = "VID3",
3477                 [OMAP_DSS_WB]           = "WB",
3478         };
3479         const char **p_names;
3480
3481 #define DUMPREG(dispc, r) \
3482         seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r))
3483
3484         if (dispc_runtime_get(dispc))
3485                 return 0;
3486
3487         /* DISPC common registers */
3488         DUMPREG(dispc, DISPC_REVISION);
3489         DUMPREG(dispc, DISPC_SYSCONFIG);
3490         DUMPREG(dispc, DISPC_SYSSTATUS);
3491         DUMPREG(dispc, DISPC_IRQSTATUS);
3492         DUMPREG(dispc, DISPC_IRQENABLE);
3493         DUMPREG(dispc, DISPC_CONTROL);
3494         DUMPREG(dispc, DISPC_CONFIG);
3495         DUMPREG(dispc, DISPC_CAPABLE);
3496         DUMPREG(dispc, DISPC_LINE_STATUS);
3497         DUMPREG(dispc, DISPC_LINE_NUMBER);
3498         if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) ||
3499                         dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
3500                 DUMPREG(dispc, DISPC_GLOBAL_ALPHA);
3501         if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) {
3502                 DUMPREG(dispc, DISPC_CONTROL2);
3503                 DUMPREG(dispc, DISPC_CONFIG2);
3504         }
3505         if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) {
3506                 DUMPREG(dispc, DISPC_CONTROL3);
3507                 DUMPREG(dispc, DISPC_CONFIG3);
3508         }
3509         if (dispc_has_feature(dispc, FEAT_MFLAG))
3510                 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3511
3512 #undef DUMPREG
3513
3514 #define DISPC_REG(i, name) name(i)
3515 #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3516         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3517         dispc_read_reg(dispc, DISPC_REG(i, r)))
3518
3519         p_names = mgr_names;
3520
3521         /* DISPC channel specific registers */
3522         for (i = 0; i < dispc_get_num_mgrs(dispc); i++) {
3523                 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR);
3524                 DUMPREG(dispc, i, DISPC_TRANS_COLOR);
3525                 DUMPREG(dispc, i, DISPC_SIZE_MGR);
3526
3527                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3528                         continue;
3529
3530                 DUMPREG(dispc, i, DISPC_TIMING_H);
3531                 DUMPREG(dispc, i, DISPC_TIMING_V);
3532                 DUMPREG(dispc, i, DISPC_POL_FREQ);
3533                 DUMPREG(dispc, i, DISPC_DIVISORo);
3534
3535                 DUMPREG(dispc, i, DISPC_DATA_CYCLE1);
3536                 DUMPREG(dispc, i, DISPC_DATA_CYCLE2);
3537                 DUMPREG(dispc, i, DISPC_DATA_CYCLE3);
3538
3539                 if (dispc_has_feature(dispc, FEAT_CPR)) {
3540                         DUMPREG(dispc, i, DISPC_CPR_COEF_R);
3541                         DUMPREG(dispc, i, DISPC_CPR_COEF_G);
3542                         DUMPREG(dispc, i, DISPC_CPR_COEF_B);
3543                 }
3544         }
3545
3546         p_names = ovl_names;
3547
3548         for (i = 0; i < dispc_get_num_ovls(dispc); i++) {
3549                 DUMPREG(dispc, i, DISPC_OVL_BA0);
3550                 DUMPREG(dispc, i, DISPC_OVL_BA1);
3551                 DUMPREG(dispc, i, DISPC_OVL_POSITION);
3552                 DUMPREG(dispc, i, DISPC_OVL_SIZE);
3553                 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES);
3554                 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD);
3555                 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS);
3556                 DUMPREG(dispc, i, DISPC_OVL_ROW_INC);
3557                 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC);
3558
3559                 if (dispc_has_feature(dispc, FEAT_PRELOAD))
3560                         DUMPREG(dispc, i, DISPC_OVL_PRELOAD);
3561                 if (dispc_has_feature(dispc, FEAT_MFLAG))
3562                         DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD);
3563
3564                 if (i == OMAP_DSS_GFX) {
3565                         DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP);
3566                         DUMPREG(dispc, i, DISPC_OVL_TABLE_BA);
3567                         continue;
3568                 }
3569
3570                 DUMPREG(dispc, i, DISPC_OVL_FIR);
3571                 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE);
3572                 DUMPREG(dispc, i, DISPC_OVL_ACCU0);
3573                 DUMPREG(dispc, i, DISPC_OVL_ACCU1);
3574                 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
3575                         DUMPREG(dispc, i, DISPC_OVL_BA0_UV);
3576                         DUMPREG(dispc, i, DISPC_OVL_BA1_UV);
3577                         DUMPREG(dispc, i, DISPC_OVL_FIR2);
3578                         DUMPREG(dispc, i, DISPC_OVL_ACCU2_0);
3579                         DUMPREG(dispc, i, DISPC_OVL_ACCU2_1);
3580                 }
3581                 if (dispc_has_feature(dispc, FEAT_ATTR2))
3582                         DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2);
3583         }
3584
3585         if (dispc->feat->has_writeback) {
3586                 i = OMAP_DSS_WB;
3587                 DUMPREG(dispc, i, DISPC_OVL_BA0);
3588                 DUMPREG(dispc, i, DISPC_OVL_BA1);
3589                 DUMPREG(dispc, i, DISPC_OVL_SIZE);
3590                 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES);
3591                 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD);
3592                 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS);
3593                 DUMPREG(dispc, i, DISPC_OVL_ROW_INC);
3594                 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC);
3595
3596                 if (dispc_has_feature(dispc, FEAT_MFLAG))
3597                         DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD);
3598
3599                 DUMPREG(dispc, i, DISPC_OVL_FIR);
3600                 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE);
3601                 DUMPREG(dispc, i, DISPC_OVL_ACCU0);
3602                 DUMPREG(dispc, i, DISPC_OVL_ACCU1);
3603                 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
3604                         DUMPREG(dispc, i, DISPC_OVL_BA0_UV);
3605                         DUMPREG(dispc, i, DISPC_OVL_BA1_UV);
3606                         DUMPREG(dispc, i, DISPC_OVL_FIR2);
3607                         DUMPREG(dispc, i, DISPC_OVL_ACCU2_0);
3608                         DUMPREG(dispc, i, DISPC_OVL_ACCU2_1);
3609                 }
3610                 if (dispc_has_feature(dispc, FEAT_ATTR2))
3611                         DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2);
3612         }
3613
3614 #undef DISPC_REG
3615 #undef DUMPREG
3616
3617 #define DISPC_REG(plane, name, i) name(plane, i)
3618 #define DUMPREG(dispc, plane, name, i) \
3619         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3620         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3621         dispc_read_reg(dispc, DISPC_REG(plane, name, i)))
3622
3623         /* Video pipeline coefficient registers */
3624
3625         /* start from OMAP_DSS_VIDEO1 */
3626         for (i = 1; i < dispc_get_num_ovls(dispc); i++) {
3627                 for (j = 0; j < 8; j++)
3628                         DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j);
3629
3630                 for (j = 0; j < 8; j++)
3631                         DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j);
3632
3633                 for (j = 0; j < 5; j++)
3634                         DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j);
3635
3636                 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) {
3637                         for (j = 0; j < 8; j++)
3638                                 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j);
3639                 }
3640
3641                 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
3642                         for (j = 0; j < 8; j++)
3643                                 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j);
3644
3645                         for (j = 0; j < 8; j++)
3646                                 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j);
3647
3648                         for (j = 0; j < 8; j++)
3649                                 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j);
3650                 }
3651         }
3652
3653         dispc_runtime_put(dispc);
3654
3655 #undef DISPC_REG
3656 #undef DUMPREG
3657
3658         return 0;
3659 }
3660
3661 /* calculate clock rates using dividers in cinfo */
3662 int dispc_calc_clock_rates(struct dispc_device *dispc,
3663                            unsigned long dispc_fclk_rate,
3664                            struct dispc_clock_info *cinfo)
3665 {
3666         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3667                 return -EINVAL;
3668         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3669                 return -EINVAL;
3670
3671         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3672         cinfo->pck = cinfo->lck / cinfo->pck_div;
3673
3674         return 0;
3675 }
3676
3677 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
3678                     unsigned long pck_min, unsigned long pck_max,
3679                     dispc_div_calc_func func, void *data)
3680 {
3681         int lckd, lckd_start, lckd_stop;
3682         int pckd, pckd_start, pckd_stop;
3683         unsigned long pck, lck;
3684         unsigned long lck_max;
3685         unsigned long pckd_hw_min, pckd_hw_max;
3686         unsigned int min_fck_per_pck;
3687         unsigned long fck;
3688
3689 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3690         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3691 #else
3692         min_fck_per_pck = 0;
3693 #endif
3694
3695         pckd_hw_min = dispc->feat->min_pcd;
3696         pckd_hw_max = 255;
3697
3698         lck_max = dss_get_max_fck_rate(dispc->dss);
3699
3700         pck_min = pck_min ? pck_min : 1;
3701         pck_max = pck_max ? pck_max : ULONG_MAX;
3702
3703         lckd_start = max(DIV_ROUND_UP(dispc_freq, lck_max), 1ul);
3704         lckd_stop = min(dispc_freq / pck_min, 255ul);
3705
3706         for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3707                 lck = dispc_freq / lckd;
3708
3709                 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3710                 pckd_stop = min(lck / pck_min, pckd_hw_max);
3711
3712                 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3713                         pck = lck / pckd;
3714
3715                         /*
3716                          * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3717                          * clock, which means we're configuring DISPC fclk here
3718                          * also. Thus we need to use the calculated lck. For
3719                          * OMAP4+ the DISPC fclk is a separate clock.
3720                          */
3721                         if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV))
3722                                 fck = dispc_core_clk_rate(dispc);
3723                         else
3724                                 fck = lck;
3725
3726                         if (fck < pck * min_fck_per_pck)
3727                                 continue;
3728
3729                         if (func(lckd, pckd, lck, pck, data))
3730                                 return true;
3731                 }
3732         }
3733
3734         return false;
3735 }
3736
3737 void dispc_mgr_set_clock_div(struct dispc_device *dispc,
3738                              enum omap_channel channel,
3739                              const struct dispc_clock_info *cinfo)
3740 {
3741         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3742         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3743
3744         dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div,
3745                                   cinfo->pck_div);
3746 }
3747
3748 int dispc_mgr_get_clock_div(struct dispc_device *dispc,
3749                             enum omap_channel channel,
3750                             struct dispc_clock_info *cinfo)
3751 {
3752         unsigned long fck;
3753
3754         fck = dispc_fclk_rate(dispc);
3755
3756         cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16);
3757         cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0);
3758
3759         cinfo->lck = fck / cinfo->lck_div;
3760         cinfo->pck = cinfo->lck / cinfo->pck_div;
3761
3762         return 0;
3763 }
3764
3765 static u32 dispc_read_irqstatus(struct dispc_device *dispc)
3766 {
3767         return dispc_read_reg(dispc, DISPC_IRQSTATUS);
3768 }
3769
3770 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask)
3771 {
3772         dispc_write_reg(dispc, DISPC_IRQSTATUS, mask);
3773 }
3774
3775 static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask)
3776 {
3777         u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE);
3778
3779         /* clear the irqstatus for newly enabled irqs */
3780         dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask);
3781
3782         dispc_write_reg(dispc, DISPC_IRQENABLE, mask);
3783
3784         /* flush posted write */
3785         dispc_read_reg(dispc, DISPC_IRQENABLE);
3786 }
3787
3788 void dispc_enable_sidle(struct dispc_device *dispc)
3789 {
3790         /* SIDLEMODE: smart idle */
3791         REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3);
3792 }
3793
3794 void dispc_disable_sidle(struct dispc_device *dispc)
3795 {
3796         REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3);   /* SIDLEMODE: no idle */
3797 }
3798
3799 static u32 dispc_mgr_gamma_size(struct dispc_device *dispc,
3800                                 enum omap_channel channel)
3801 {
3802         const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3803
3804         if (!dispc->feat->has_gamma_table)
3805                 return 0;
3806
3807         return gdesc->len;
3808 }
3809
3810 static void dispc_mgr_write_gamma_table(struct dispc_device *dispc,
3811                                         enum omap_channel channel)
3812 {
3813         const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3814         u32 *table = dispc->gamma_table[channel];
3815         unsigned int i;
3816
3817         DSSDBG("%s: channel %d\n", __func__, channel);
3818
3819         for (i = 0; i < gdesc->len; ++i) {
3820                 u32 v = table[i];
3821
3822                 if (gdesc->has_index)
3823                         v |= i << 24;
3824                 else if (i == 0)
3825                         v |= 1 << 31;
3826
3827                 dispc_write_reg(dispc, gdesc->reg, v);
3828         }
3829 }
3830
3831 static void dispc_restore_gamma_tables(struct dispc_device *dispc)
3832 {
3833         DSSDBG("%s()\n", __func__);
3834
3835         if (!dispc->feat->has_gamma_table)
3836                 return;
3837
3838         dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD);
3839
3840         dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT);
3841
3842         if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
3843                 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2);
3844
3845         if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
3846                 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3);
3847 }
3848
3849 static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = {
3850         { .red = 0, .green = 0, .blue = 0, },
3851         { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
3852 };
3853
3854 static void dispc_mgr_set_gamma(struct dispc_device *dispc,
3855                                 enum omap_channel channel,
3856                                 const struct drm_color_lut *lut,
3857                                 unsigned int length)
3858 {
3859         const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3860         u32 *table = dispc->gamma_table[channel];
3861         uint i;
3862
3863         DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3864                channel, length, gdesc->len);
3865
3866         if (!dispc->feat->has_gamma_table)
3867                 return;
3868
3869         if (lut == NULL || length < 2) {
3870                 lut = dispc_mgr_gamma_default_lut;
3871                 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut);
3872         }
3873
3874         for (i = 0; i < length - 1; ++i) {
3875                 uint first = i * (gdesc->len - 1) / (length - 1);
3876                 uint last = (i + 1) * (gdesc->len - 1) / (length - 1);
3877                 uint w = last - first;
3878                 u16 r, g, b;
3879                 uint j;
3880
3881                 if (w == 0)
3882                         continue;
3883
3884                 for (j = 0; j <= w; j++) {
3885                         r = (lut[i].red * (w - j) + lut[i+1].red * j) / w;
3886                         g = (lut[i].green * (w - j) + lut[i+1].green * j) / w;
3887                         b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w;
3888
3889                         r >>= 16 - gdesc->bits;
3890                         g >>= 16 - gdesc->bits;
3891                         b >>= 16 - gdesc->bits;
3892
3893                         table[first + j] = (r << (gdesc->bits * 2)) |
3894                                 (g << gdesc->bits) | b;
3895                 }
3896         }
3897
3898         if (dispc->is_enabled)
3899                 dispc_mgr_write_gamma_table(dispc, channel);
3900 }
3901
3902 static int dispc_init_gamma_tables(struct dispc_device *dispc)
3903 {
3904         int channel;
3905
3906         if (!dispc->feat->has_gamma_table)
3907                 return 0;
3908
3909         for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) {
3910                 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3911                 u32 *gt;
3912
3913                 if (channel == OMAP_DSS_CHANNEL_LCD2 &&
3914                     !dispc_has_feature(dispc, FEAT_MGR_LCD2))
3915                         continue;
3916
3917                 if (channel == OMAP_DSS_CHANNEL_LCD3 &&
3918                     !dispc_has_feature(dispc, FEAT_MGR_LCD3))
3919                         continue;
3920
3921                 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len,
3922                                         sizeof(u32), GFP_KERNEL);
3923                 if (!gt)
3924                         return -ENOMEM;
3925
3926                 dispc->gamma_table[channel] = gt;
3927
3928                 dispc_mgr_set_gamma(dispc, channel, NULL, 0);
3929         }
3930         return 0;
3931 }
3932
3933 static void _omap_dispc_initial_config(struct dispc_device *dispc)
3934 {
3935         u32 l;
3936
3937         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3938         if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) {
3939                 l = dispc_read_reg(dispc, DISPC_DIVISOR);
3940                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3941                 l = FLD_MOD(l, 1, 0, 0);
3942                 l = FLD_MOD(l, 1, 23, 16);
3943                 dispc_write_reg(dispc, DISPC_DIVISOR, l);
3944
3945                 dispc->core_clk_rate = dispc_fclk_rate(dispc);
3946         }
3947
3948         /* Use gamma table mode, instead of palette mode */
3949         if (dispc->feat->has_gamma_table)
3950                 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3);
3951
3952         /* For older DSS versions (FEAT_FUNCGATED) this enables
3953          * func-clock auto-gating. For newer versions
3954          * (dispc->feat->has_gamma_table) this enables tv-out gamma tables.
3955          */
3956         if (dispc_has_feature(dispc, FEAT_FUNCGATED) ||
3957             dispc->feat->has_gamma_table)
3958                 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9);
3959
3960         dispc_setup_color_conv_coef(dispc);
3961
3962         dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY);
3963
3964         dispc_init_fifos(dispc);
3965
3966         dispc_configure_burst_sizes(dispc);
3967
3968         dispc_ovl_enable_zorder_planes(dispc);
3969
3970         if (dispc->feat->mstandby_workaround)
3971                 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0);
3972
3973         if (dispc_has_feature(dispc, FEAT_MFLAG))
3974                 dispc_init_mflag(dispc);
3975 }
3976
3977 static const enum dispc_feature_id omap2_dispc_features_list[] = {
3978         FEAT_LCDENABLEPOL,
3979         FEAT_LCDENABLESIGNAL,
3980         FEAT_PCKFREEENABLE,
3981         FEAT_FUNCGATED,
3982         FEAT_ROWREPEATENABLE,
3983         FEAT_RESIZECONF,
3984 };
3985
3986 static const enum dispc_feature_id omap3_dispc_features_list[] = {
3987         FEAT_LCDENABLEPOL,
3988         FEAT_LCDENABLESIGNAL,
3989         FEAT_PCKFREEENABLE,
3990         FEAT_FUNCGATED,
3991         FEAT_LINEBUFFERSPLIT,
3992         FEAT_ROWREPEATENABLE,
3993         FEAT_RESIZECONF,
3994         FEAT_CPR,
3995         FEAT_PRELOAD,
3996         FEAT_FIR_COEF_V,
3997         FEAT_ALPHA_FIXED_ZORDER,
3998         FEAT_FIFO_MERGE,
3999         FEAT_OMAP3_DSI_FIFO_BUG,
4000 };
4001
4002 static const enum dispc_feature_id am43xx_dispc_features_list[] = {
4003         FEAT_LCDENABLEPOL,
4004         FEAT_LCDENABLESIGNAL,
4005         FEAT_PCKFREEENABLE,
4006         FEAT_FUNCGATED,
4007         FEAT_LINEBUFFERSPLIT,
4008         FEAT_ROWREPEATENABLE,
4009         FEAT_RESIZECONF,
4010         FEAT_CPR,
4011         FEAT_PRELOAD,
4012         FEAT_FIR_COEF_V,
4013         FEAT_ALPHA_FIXED_ZORDER,
4014         FEAT_FIFO_MERGE,
4015 };
4016
4017 static const enum dispc_feature_id omap4_dispc_features_list[] = {
4018         FEAT_MGR_LCD2,
4019         FEAT_CORE_CLK_DIV,
4020         FEAT_HANDLE_UV_SEPARATE,
4021         FEAT_ATTR2,
4022         FEAT_CPR,
4023         FEAT_PRELOAD,
4024         FEAT_FIR_COEF_V,
4025         FEAT_ALPHA_FREE_ZORDER,
4026         FEAT_FIFO_MERGE,
4027         FEAT_BURST_2D,
4028 };
4029
4030 static const enum dispc_feature_id omap5_dispc_features_list[] = {
4031         FEAT_MGR_LCD2,
4032         FEAT_MGR_LCD3,
4033         FEAT_CORE_CLK_DIV,
4034         FEAT_HANDLE_UV_SEPARATE,
4035         FEAT_ATTR2,
4036         FEAT_CPR,
4037         FEAT_PRELOAD,
4038         FEAT_FIR_COEF_V,
4039         FEAT_ALPHA_FREE_ZORDER,
4040         FEAT_FIFO_MERGE,
4041         FEAT_BURST_2D,
4042         FEAT_MFLAG,
4043 };
4044
4045 static const struct dss_reg_field omap2_dispc_reg_fields[] = {
4046         [FEAT_REG_FIRHINC]                      = { 11, 0 },
4047         [FEAT_REG_FIRVINC]                      = { 27, 16 },
4048         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 8, 0 },
4049         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 24, 16 },
4050         [FEAT_REG_FIFOSIZE]                     = { 8, 0 },
4051         [FEAT_REG_HORIZONTALACCU]               = { 9, 0 },
4052         [FEAT_REG_VERTICALACCU]                 = { 25, 16 },
4053 };
4054
4055 static const struct dss_reg_field omap3_dispc_reg_fields[] = {
4056         [FEAT_REG_FIRHINC]                      = { 12, 0 },
4057         [FEAT_REG_FIRVINC]                      = { 28, 16 },
4058         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 11, 0 },
4059         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 27, 16 },
4060         [FEAT_REG_FIFOSIZE]                     = { 10, 0 },
4061         [FEAT_REG_HORIZONTALACCU]               = { 9, 0 },
4062         [FEAT_REG_VERTICALACCU]                 = { 25, 16 },
4063 };
4064
4065 static const struct dss_reg_field omap4_dispc_reg_fields[] = {
4066         [FEAT_REG_FIRHINC]                      = { 12, 0 },
4067         [FEAT_REG_FIRVINC]                      = { 28, 16 },
4068         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 15, 0 },
4069         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 31, 16 },
4070         [FEAT_REG_FIFOSIZE]                     = { 15, 0 },
4071         [FEAT_REG_HORIZONTALACCU]               = { 10, 0 },
4072         [FEAT_REG_VERTICALACCU]                 = { 26, 16 },
4073 };
4074
4075 static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = {
4076         /* OMAP_DSS_GFX */
4077         OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4078
4079         /* OMAP_DSS_VIDEO1 */
4080         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
4081                 OMAP_DSS_OVL_CAP_REPLICATION,
4082
4083         /* OMAP_DSS_VIDEO2 */
4084         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
4085                 OMAP_DSS_OVL_CAP_REPLICATION,
4086 };
4087
4088 static const enum omap_overlay_caps omap3430_dispc_overlay_caps[] = {
4089         /* OMAP_DSS_GFX */
4090         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS |
4091                 OMAP_DSS_OVL_CAP_REPLICATION,
4092
4093         /* OMAP_DSS_VIDEO1 */
4094         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
4095                 OMAP_DSS_OVL_CAP_REPLICATION,
4096
4097         /* OMAP_DSS_VIDEO2 */
4098         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4099                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4100 };
4101
4102 static const enum omap_overlay_caps omap3630_dispc_overlay_caps[] = {
4103         /* OMAP_DSS_GFX */
4104         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
4105                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4106
4107         /* OMAP_DSS_VIDEO1 */
4108         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
4109                 OMAP_DSS_OVL_CAP_REPLICATION,
4110
4111         /* OMAP_DSS_VIDEO2 */
4112         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4113                 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS |
4114                 OMAP_DSS_OVL_CAP_REPLICATION,
4115 };
4116
4117 static const enum omap_overlay_caps omap4_dispc_overlay_caps[] = {
4118         /* OMAP_DSS_GFX */
4119         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
4120                 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS |
4121                 OMAP_DSS_OVL_CAP_REPLICATION,
4122
4123         /* OMAP_DSS_VIDEO1 */
4124         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4125                 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
4126                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4127
4128         /* OMAP_DSS_VIDEO2 */
4129         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4130                 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
4131                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4132
4133         /* OMAP_DSS_VIDEO3 */
4134         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
4135                 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
4136                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
4137 };
4138
4139 #define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 }
4140
4141 static const u32 *omap2_dispc_supported_color_modes[] = {
4142
4143         /* OMAP_DSS_GFX */
4144         COLOR_ARRAY(
4145         DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565,
4146         DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888),
4147
4148         /* OMAP_DSS_VIDEO1 */
4149         COLOR_ARRAY(
4150         DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4151         DRM_FORMAT_RGB888, DRM_FORMAT_YUYV,
4152         DRM_FORMAT_UYVY),
4153
4154         /* OMAP_DSS_VIDEO2 */
4155         COLOR_ARRAY(
4156         DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4157         DRM_FORMAT_RGB888, DRM_FORMAT_YUYV,
4158         DRM_FORMAT_UYVY),
4159 };
4160
4161 static const u32 *omap3_dispc_supported_color_modes[] = {
4162         /* OMAP_DSS_GFX */
4163         COLOR_ARRAY(
4164         DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444,
4165         DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4166         DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888,
4167         DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888),
4168
4169         /* OMAP_DSS_VIDEO1 */
4170         COLOR_ARRAY(
4171         DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888,
4172         DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565,
4173         DRM_FORMAT_YUYV, DRM_FORMAT_UYVY),
4174
4175         /* OMAP_DSS_VIDEO2 */
4176         COLOR_ARRAY(
4177         DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444,
4178         DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4179         DRM_FORMAT_RGB888, DRM_FORMAT_YUYV,
4180         DRM_FORMAT_UYVY, DRM_FORMAT_ARGB8888,
4181         DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888),
4182 };
4183
4184 static const u32 *omap4_dispc_supported_color_modes[] = {
4185         /* OMAP_DSS_GFX */
4186         COLOR_ARRAY(
4187         DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444,
4188         DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
4189         DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888,
4190         DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888,
4191         DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB4444,
4192         DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB1555),
4193
4194         /* OMAP_DSS_VIDEO1 */
4195         COLOR_ARRAY(
4196         DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4197         DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4198         DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4199         DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4200         DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4201         DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4202         DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4203         DRM_FORMAT_RGBX8888),
4204
4205        /* OMAP_DSS_VIDEO2 */
4206         COLOR_ARRAY(
4207         DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4208         DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4209         DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4210         DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4211         DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4212         DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4213         DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4214         DRM_FORMAT_RGBX8888),
4215
4216         /* OMAP_DSS_VIDEO3 */
4217         COLOR_ARRAY(
4218         DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4219         DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4220         DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4221         DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4222         DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4223         DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4224         DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4225         DRM_FORMAT_RGBX8888),
4226
4227         /* OMAP_DSS_WB */
4228         COLOR_ARRAY(
4229         DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4230         DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4231         DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4232         DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4233         DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4234         DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4235         DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4236         DRM_FORMAT_RGBX8888),
4237 };
4238
4239 static const struct dispc_features omap24xx_dispc_feats = {
4240         .sw_start               =       5,
4241         .fp_start               =       15,
4242         .bp_start               =       27,
4243         .sw_max                 =       64,
4244         .vp_max                 =       255,
4245         .hp_max                 =       256,
4246         .mgr_width_start        =       10,
4247         .mgr_height_start       =       26,
4248         .mgr_width_max          =       2048,
4249         .mgr_height_max         =       2048,
4250         .max_lcd_pclk           =       66500000,
4251         .max_downscale          =       2,
4252         /*
4253          * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler
4254          * cannot scale an image width larger than 768.
4255          */
4256         .max_line_width         =       768,
4257         .min_pcd                =       2,
4258         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
4259         .calc_core_clk          =       calc_core_clk_24xx,
4260         .num_fifos              =       3,
4261         .features               =       omap2_dispc_features_list,
4262         .num_features           =       ARRAY_SIZE(omap2_dispc_features_list),
4263         .reg_fields             =       omap2_dispc_reg_fields,
4264         .num_reg_fields         =       ARRAY_SIZE(omap2_dispc_reg_fields),
4265         .overlay_caps           =       omap2_dispc_overlay_caps,
4266         .supported_color_modes  =       omap2_dispc_supported_color_modes,
4267         .num_mgrs               =       2,
4268         .num_ovls               =       3,
4269         .buffer_size_unit       =       1,
4270         .burst_size_unit        =       8,
4271         .no_framedone_tv        =       true,
4272         .set_max_preload        =       false,
4273         .last_pixel_inc_missing =       true,
4274 };
4275
4276 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
4277         .sw_start               =       5,
4278         .fp_start               =       15,
4279         .bp_start               =       27,
4280         .sw_max                 =       64,
4281         .vp_max                 =       255,
4282         .hp_max                 =       256,
4283         .mgr_width_start        =       10,
4284         .mgr_height_start       =       26,
4285         .mgr_width_max          =       2048,
4286         .mgr_height_max         =       2048,
4287         .max_lcd_pclk           =       173000000,
4288         .max_tv_pclk            =       59000000,
4289         .max_downscale          =       4,
4290         .max_line_width         =       1024,
4291         .min_pcd                =       1,
4292         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
4293         .calc_core_clk          =       calc_core_clk_34xx,
4294         .num_fifos              =       3,
4295         .features               =       omap3_dispc_features_list,
4296         .num_features           =       ARRAY_SIZE(omap3_dispc_features_list),
4297         .reg_fields             =       omap3_dispc_reg_fields,
4298         .num_reg_fields         =       ARRAY_SIZE(omap3_dispc_reg_fields),
4299         .overlay_caps           =       omap3430_dispc_overlay_caps,
4300         .supported_color_modes  =       omap3_dispc_supported_color_modes,
4301         .num_mgrs               =       2,
4302         .num_ovls               =       3,
4303         .buffer_size_unit       =       1,
4304         .burst_size_unit        =       8,
4305         .no_framedone_tv        =       true,
4306         .set_max_preload        =       false,
4307         .last_pixel_inc_missing =       true,
4308 };
4309
4310 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
4311         .sw_start               =       7,
4312         .fp_start               =       19,
4313         .bp_start               =       31,
4314         .sw_max                 =       256,
4315         .vp_max                 =       4095,
4316         .hp_max                 =       4096,
4317         .mgr_width_start        =       10,
4318         .mgr_height_start       =       26,
4319         .mgr_width_max          =       2048,
4320         .mgr_height_max         =       2048,
4321         .max_lcd_pclk           =       173000000,
4322         .max_tv_pclk            =       59000000,
4323         .max_downscale          =       4,
4324         .max_line_width         =       1024,
4325         .min_pcd                =       1,
4326         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
4327         .calc_core_clk          =       calc_core_clk_34xx,
4328         .num_fifos              =       3,
4329         .features               =       omap3_dispc_features_list,
4330         .num_features           =       ARRAY_SIZE(omap3_dispc_features_list),
4331         .reg_fields             =       omap3_dispc_reg_fields,
4332         .num_reg_fields         =       ARRAY_SIZE(omap3_dispc_reg_fields),
4333         .overlay_caps           =       omap3430_dispc_overlay_caps,
4334         .supported_color_modes  =       omap3_dispc_supported_color_modes,
4335         .num_mgrs               =       2,
4336         .num_ovls               =       3,
4337         .buffer_size_unit       =       1,
4338         .burst_size_unit        =       8,
4339         .no_framedone_tv        =       true,
4340         .set_max_preload        =       false,
4341         .last_pixel_inc_missing =       true,
4342 };
4343
4344 static const struct dispc_features omap36xx_dispc_feats = {
4345         .sw_start               =       7,
4346         .fp_start               =       19,
4347         .bp_start               =       31,
4348         .sw_max                 =       256,
4349         .vp_max                 =       4095,
4350         .hp_max                 =       4096,
4351         .mgr_width_start        =       10,
4352         .mgr_height_start       =       26,
4353         .mgr_width_max          =       2048,
4354         .mgr_height_max         =       2048,
4355         .max_lcd_pclk           =       173000000,
4356         .max_tv_pclk            =       59000000,
4357         .max_downscale          =       4,
4358         .max_line_width         =       1024,
4359         .min_pcd                =       1,
4360         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
4361         .calc_core_clk          =       calc_core_clk_34xx,
4362         .num_fifos              =       3,
4363         .features               =       omap3_dispc_features_list,
4364         .num_features           =       ARRAY_SIZE(omap3_dispc_features_list),
4365         .reg_fields             =       omap3_dispc_reg_fields,
4366         .num_reg_fields         =       ARRAY_SIZE(omap3_dispc_reg_fields),
4367         .overlay_caps           =       omap3630_dispc_overlay_caps,
4368         .supported_color_modes  =       omap3_dispc_supported_color_modes,
4369         .num_mgrs               =       2,
4370         .num_ovls               =       3,
4371         .buffer_size_unit       =       1,
4372         .burst_size_unit        =       8,
4373         .no_framedone_tv        =       true,
4374         .set_max_preload        =       false,
4375         .last_pixel_inc_missing =       true,
4376 };
4377
4378 static const struct dispc_features am43xx_dispc_feats = {
4379         .sw_start               =       7,
4380         .fp_start               =       19,
4381         .bp_start               =       31,
4382         .sw_max                 =       256,
4383         .vp_max                 =       4095,
4384         .hp_max                 =       4096,
4385         .mgr_width_start        =       10,
4386         .mgr_height_start       =       26,
4387         .mgr_width_max          =       2048,
4388         .mgr_height_max         =       2048,
4389         .max_lcd_pclk           =       173000000,
4390         .max_tv_pclk            =       59000000,
4391         .max_downscale          =       4,
4392         .max_line_width         =       1024,
4393         .min_pcd                =       1,
4394         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
4395         .calc_core_clk          =       calc_core_clk_34xx,
4396         .num_fifos              =       3,
4397         .features               =       am43xx_dispc_features_list,
4398         .num_features           =       ARRAY_SIZE(am43xx_dispc_features_list),
4399         .reg_fields             =       omap3_dispc_reg_fields,
4400         .num_reg_fields         =       ARRAY_SIZE(omap3_dispc_reg_fields),
4401         .overlay_caps           =       omap3430_dispc_overlay_caps,
4402         .supported_color_modes  =       omap3_dispc_supported_color_modes,
4403         .num_mgrs               =       1,
4404         .num_ovls               =       3,
4405         .buffer_size_unit       =       1,
4406         .burst_size_unit        =       8,
4407         .no_framedone_tv        =       true,
4408         .set_max_preload        =       false,
4409         .last_pixel_inc_missing =       true,
4410 };
4411
4412 static const struct dispc_features omap44xx_dispc_feats = {
4413         .sw_start               =       7,
4414         .fp_start               =       19,
4415         .bp_start               =       31,
4416         .sw_max                 =       256,
4417         .vp_max                 =       4095,
4418         .hp_max                 =       4096,
4419         .mgr_width_start        =       10,
4420         .mgr_height_start       =       26,
4421         .mgr_width_max          =       2048,
4422         .mgr_height_max         =       2048,
4423         .max_lcd_pclk           =       170000000,
4424         .max_tv_pclk            =       185625000,
4425         .max_downscale          =       4,
4426         .max_line_width         =       2048,
4427         .min_pcd                =       1,
4428         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
4429         .calc_core_clk          =       calc_core_clk_44xx,
4430         .num_fifos              =       5,
4431         .features               =       omap4_dispc_features_list,
4432         .num_features           =       ARRAY_SIZE(omap4_dispc_features_list),
4433         .reg_fields             =       omap4_dispc_reg_fields,
4434         .num_reg_fields         =       ARRAY_SIZE(omap4_dispc_reg_fields),
4435         .overlay_caps           =       omap4_dispc_overlay_caps,
4436         .supported_color_modes  =       omap4_dispc_supported_color_modes,
4437         .num_mgrs               =       3,
4438         .num_ovls               =       4,
4439         .buffer_size_unit       =       16,
4440         .burst_size_unit        =       16,
4441         .gfx_fifo_workaround    =       true,
4442         .set_max_preload        =       true,
4443         .supports_sync_align    =       true,
4444         .has_writeback          =       true,
4445         .supports_double_pixel  =       true,
4446         .reverse_ilace_field_order =    true,
4447         .has_gamma_table        =       true,
4448         .has_gamma_i734_bug     =       true,
4449 };
4450
4451 static const struct dispc_features omap54xx_dispc_feats = {
4452         .sw_start               =       7,
4453         .fp_start               =       19,
4454         .bp_start               =       31,
4455         .sw_max                 =       256,
4456         .vp_max                 =       4095,
4457         .hp_max                 =       4096,
4458         .mgr_width_start        =       11,
4459         .mgr_height_start       =       27,
4460         .mgr_width_max          =       4096,
4461         .mgr_height_max         =       4096,
4462         .max_lcd_pclk           =       170000000,
4463         .max_tv_pclk            =       186000000,
4464         .max_downscale          =       4,
4465         .max_line_width         =       2048,
4466         .min_pcd                =       1,
4467         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
4468         .calc_core_clk          =       calc_core_clk_44xx,
4469         .num_fifos              =       5,
4470         .features               =       omap5_dispc_features_list,
4471         .num_features           =       ARRAY_SIZE(omap5_dispc_features_list),
4472         .reg_fields             =       omap4_dispc_reg_fields,
4473         .num_reg_fields         =       ARRAY_SIZE(omap4_dispc_reg_fields),
4474         .overlay_caps           =       omap4_dispc_overlay_caps,
4475         .supported_color_modes  =       omap4_dispc_supported_color_modes,
4476         .num_mgrs               =       4,
4477         .num_ovls               =       4,
4478         .buffer_size_unit       =       16,
4479         .burst_size_unit        =       16,
4480         .gfx_fifo_workaround    =       true,
4481         .mstandby_workaround    =       true,
4482         .set_max_preload        =       true,
4483         .supports_sync_align    =       true,
4484         .has_writeback          =       true,
4485         .supports_double_pixel  =       true,
4486         .reverse_ilace_field_order =    true,
4487         .has_gamma_table        =       true,
4488         .has_gamma_i734_bug     =       true,
4489 };
4490
4491 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4492 {
4493         struct dispc_device *dispc = arg;
4494
4495         if (!dispc->is_enabled)
4496                 return IRQ_NONE;
4497
4498         return dispc->user_handler(irq, dispc->user_data);
4499 }
4500
4501 static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler,
4502                              void *dev_id)
4503 {
4504         int r;
4505
4506         if (dispc->user_handler != NULL)
4507                 return -EBUSY;
4508
4509         dispc->user_handler = handler;
4510         dispc->user_data = dev_id;
4511
4512         /* ensure the dispc_irq_handler sees the values above */
4513         smp_wmb();
4514
4515         r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler,
4516                              IRQF_SHARED, "OMAP DISPC", dispc);
4517         if (r) {
4518                 dispc->user_handler = NULL;
4519                 dispc->user_data = NULL;
4520         }
4521
4522         return r;
4523 }
4524
4525 static void dispc_free_irq(struct dispc_device *dispc, void *dev_id)
4526 {
4527         devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc);
4528
4529         dispc->user_handler = NULL;
4530         dispc->user_data = NULL;
4531 }
4532
4533 static u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc)
4534 {
4535         u32 limit = 0;
4536
4537         /* Optional maximum memory bandwidth */
4538         of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth",
4539                              &limit);
4540
4541         return limit;
4542 }
4543
4544 /*
4545  * Workaround for errata i734 in DSS dispc
4546  *  - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
4547  *
4548  * For gamma tables to work on LCD1 the GFX plane has to be used at
4549  * least once after DSS HW has come out of reset. The workaround
4550  * sets up a minimal LCD setup with GFX plane and waits for one
4551  * vertical sync irq before disabling the setup and continuing with
4552  * the context restore. The physical outputs are gated during the
4553  * operation. This workaround requires that gamma table's LOADMODE
4554  * is set to 0x2 in DISPC_CONTROL1 register.
4555  *
4556  * For details see:
4557  * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata
4558  * Literature Number: SWPZ037E
4559  * Or some other relevant errata document for the DSS IP version.
4560  */
4561
4562 static const struct dispc_errata_i734_data {
4563         struct videomode vm;
4564         struct omap_overlay_info ovli;
4565         struct omap_overlay_manager_info mgri;
4566         struct dss_lcd_mgr_config lcd_conf;
4567 } i734 = {
4568         .vm = {
4569                 .hactive = 8, .vactive = 1,
4570                 .pixelclock = 16000000,
4571                 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
4572                 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1,
4573
4574                 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4575                          DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
4576                          DISPLAY_FLAGS_PIXDATA_POSEDGE,
4577         },
4578         .ovli = {
4579                 .screen_width = 1,
4580                 .width = 1, .height = 1,
4581                 .fourcc = DRM_FORMAT_XRGB8888,
4582                 .rotation = DRM_MODE_ROTATE_0,
4583                 .rotation_type = OMAP_DSS_ROT_NONE,
4584                 .pos_x = 0, .pos_y = 0,
4585                 .out_width = 0, .out_height = 0,
4586                 .global_alpha = 0xff,
4587                 .pre_mult_alpha = 0,
4588                 .zorder = 0,
4589         },
4590         .mgri = {
4591                 .default_color = 0,
4592                 .trans_enabled = false,
4593                 .partial_alpha_enabled = false,
4594                 .cpr_enable = false,
4595         },
4596         .lcd_conf = {
4597                 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS,
4598                 .stallmode = false,
4599                 .fifohandcheck = false,
4600                 .clock_info = {
4601                         .lck_div = 1,
4602                         .pck_div = 2,
4603                 },
4604                 .video_port_width = 24,
4605                 .lcden_sig_polarity = 0,
4606         },
4607 };
4608
4609 static struct i734_buf {
4610         size_t size;
4611         dma_addr_t paddr;
4612         void *vaddr;
4613 } i734_buf;
4614
4615 static int dispc_errata_i734_wa_init(struct dispc_device *dispc)
4616 {
4617         if (!dispc->feat->has_gamma_i734_bug)
4618                 return 0;
4619
4620         i734_buf.size = i734.ovli.width * i734.ovli.height *
4621                 color_mode_to_bpp(i734.ovli.fourcc) / 8;
4622
4623         i734_buf.vaddr = dma_alloc_writecombine(&dispc->pdev->dev,
4624                                                 i734_buf.size, &i734_buf.paddr,
4625                                                 GFP_KERNEL);
4626         if (!i734_buf.vaddr) {
4627                 dev_err(&dispc->pdev->dev, "%s: dma_alloc_writecombine failed\n",
4628                         __func__);
4629                 return -ENOMEM;
4630         }
4631
4632         return 0;
4633 }
4634
4635 static void dispc_errata_i734_wa_fini(struct dispc_device *dispc)
4636 {
4637         if (!dispc->feat->has_gamma_i734_bug)
4638                 return;
4639
4640         dma_free_writecombine(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr,
4641                               i734_buf.paddr);
4642 }
4643
4644 static void dispc_errata_i734_wa(struct dispc_device *dispc)
4645 {
4646         u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc,
4647                                                         OMAP_DSS_CHANNEL_LCD);
4648         struct omap_overlay_info ovli;
4649         struct dss_lcd_mgr_config lcd_conf;
4650         u32 gatestate;
4651         unsigned int count;
4652
4653         if (!dispc->feat->has_gamma_i734_bug)
4654                 return;
4655
4656         gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4);
4657
4658         ovli = i734.ovli;
4659         ovli.paddr = i734_buf.paddr;
4660         lcd_conf = i734.lcd_conf;
4661
4662         /* Gate all LCD1 outputs */
4663         REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4);
4664
4665         /* Setup and enable GFX plane */
4666         dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false,
4667                         OMAP_DSS_CHANNEL_LCD);
4668         dispc_ovl_enable(dispc, OMAP_DSS_GFX, true);
4669
4670         /* Set up and enable display manager for LCD1 */
4671         dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri);
4672         dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss),
4673                                &lcd_conf.clock_info);
4674         dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf);
4675         dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm);
4676
4677         dispc_clear_irqstatus(dispc, framedone_irq);
4678
4679         /* Enable and shut the channel to produce just one frame */
4680         dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true);
4681         dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false);
4682
4683         /* Busy wait for framedone. We can't fiddle with irq handlers
4684          * in PM resume. Typically the loop runs less than 5 times and
4685          * waits less than a micro second.
4686          */
4687         count = 0;
4688         while (!(dispc_read_irqstatus(dispc) & framedone_irq)) {
4689                 if (count++ > 10000) {
4690                         dev_err(&dispc->pdev->dev, "%s: framedone timeout\n",
4691                                 __func__);
4692                         break;
4693                 }
4694         }
4695         dispc_ovl_enable(dispc, OMAP_DSS_GFX, false);
4696
4697         /* Clear all irq bits before continuing */
4698         dispc_clear_irqstatus(dispc, 0xffffffff);
4699
4700         /* Restore the original state to LCD1 output gates */
4701         REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4);
4702 }
4703
4704 static const struct dispc_ops dispc_ops = {
4705         .read_irqstatus = dispc_read_irqstatus,
4706         .clear_irqstatus = dispc_clear_irqstatus,
4707         .write_irqenable = dispc_write_irqenable,
4708
4709         .request_irq = dispc_request_irq,
4710         .free_irq = dispc_free_irq,
4711
4712         .runtime_get = dispc_runtime_get,
4713         .runtime_put = dispc_runtime_put,
4714
4715         .get_num_ovls = dispc_get_num_ovls,
4716         .get_num_mgrs = dispc_get_num_mgrs,
4717
4718         .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit,
4719
4720         .mgr_enable = dispc_mgr_enable,
4721         .mgr_is_enabled = dispc_mgr_is_enabled,
4722         .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq,
4723         .mgr_get_framedone_irq = dispc_mgr_get_framedone_irq,
4724         .mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq,
4725         .mgr_go_busy = dispc_mgr_go_busy,
4726         .mgr_go = dispc_mgr_go,
4727         .mgr_set_lcd_config = dispc_mgr_set_lcd_config,
4728         .mgr_check_timings = dispc_mgr_check_timings,
4729         .mgr_set_timings = dispc_mgr_set_timings,
4730         .mgr_setup = dispc_mgr_setup,
4731         .mgr_gamma_size = dispc_mgr_gamma_size,
4732         .mgr_set_gamma = dispc_mgr_set_gamma,
4733
4734         .ovl_enable = dispc_ovl_enable,
4735         .ovl_setup = dispc_ovl_setup,
4736         .ovl_get_color_modes = dispc_ovl_get_color_modes,
4737
4738         .wb_get_framedone_irq = dispc_wb_get_framedone_irq,
4739         .wb_setup = dispc_wb_setup,
4740         .has_writeback = dispc_has_writeback,
4741         .wb_go_busy = dispc_wb_go_busy,
4742         .wb_go = dispc_wb_go,
4743 };
4744
4745 /* DISPC HW IP initialisation */
4746 static const struct of_device_id dispc_of_match[] = {
4747         { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats },
4748         { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats },
4749         { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats },
4750         { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats },
4751         { .compatible = "ti,dra7-dispc",  .data = &omap54xx_dispc_feats },
4752         {},
4753 };
4754
4755 static const struct soc_device_attribute dispc_soc_devices[] = {
4756         { .machine = "OMAP3[45]*",
4757           .revision = "ES[12].?",       .data = &omap34xx_rev1_0_dispc_feats },
4758         { .machine = "OMAP3[45]*",      .data = &omap34xx_rev3_0_dispc_feats },
4759         { .machine = "AM35*",           .data = &omap34xx_rev3_0_dispc_feats },
4760         { .machine = "AM43*",           .data = &am43xx_dispc_feats },
4761         { /* sentinel */ }
4762 };
4763
4764 static int dispc_bind(struct device *dev, struct device *master, void *data)
4765 {
4766         struct platform_device *pdev = to_platform_device(dev);
4767         const struct soc_device_attribute *soc;
4768         struct dss_device *dss = dss_get_device(master);
4769         struct dispc_device *dispc;
4770         u32 rev;
4771         int r = 0;
4772         struct resource *dispc_mem;
4773         struct device_node *np = pdev->dev.of_node;
4774
4775         dispc = kzalloc(sizeof(*dispc), GFP_KERNEL);
4776         if (!dispc)
4777                 return -ENOMEM;
4778
4779         dispc->pdev = pdev;
4780         platform_set_drvdata(pdev, dispc);
4781         dispc->dss = dss;
4782
4783         spin_lock_init(&dispc->control_lock);
4784
4785         /*
4786          * The OMAP3-based models can't be told apart using the compatible
4787          * string, use SoC device matching.
4788          */
4789         soc = soc_device_match(dispc_soc_devices);
4790         if (soc)
4791                 dispc->feat = soc->data;
4792         else
4793                 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data;
4794
4795         r = dispc_errata_i734_wa_init(dispc);
4796         if (r)
4797                 goto err_free;
4798
4799         dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0);
4800         dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem);
4801         if (IS_ERR(dispc->base)) {
4802                 r = PTR_ERR(dispc->base);
4803                 goto err_free;
4804         }
4805
4806         dispc->irq = platform_get_irq(dispc->pdev, 0);
4807         if (dispc->irq < 0) {
4808                 DSSERR("platform_get_irq failed\n");
4809                 r = -ENODEV;
4810                 goto err_free;
4811         }
4812
4813         if (np && of_property_read_bool(np, "syscon-pol")) {
4814                 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4815                 if (IS_ERR(dispc->syscon_pol)) {
4816                         dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4817                         r = PTR_ERR(dispc->syscon_pol);
4818                         goto err_free;
4819                 }
4820
4821                 if (of_property_read_u32_index(np, "syscon-pol", 1,
4822                                 &dispc->syscon_pol_offset)) {
4823                         dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4824                         r = -EINVAL;
4825                         goto err_free;
4826                 }
4827         }
4828
4829         r = dispc_init_gamma_tables(dispc);
4830         if (r)
4831                 goto err_free;
4832
4833         pm_runtime_enable(&pdev->dev);
4834
4835         r = dispc_runtime_get(dispc);
4836         if (r)
4837                 goto err_runtime_get;
4838
4839         _omap_dispc_initial_config(dispc);
4840
4841         rev = dispc_read_reg(dispc, DISPC_REVISION);
4842         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4843                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4844
4845         dispc_runtime_put(dispc);
4846
4847         dss->dispc = dispc;
4848         dss->dispc_ops = &dispc_ops;
4849
4850         dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs,
4851                                                  dispc);
4852
4853         return 0;
4854
4855 err_runtime_get:
4856         pm_runtime_disable(&pdev->dev);
4857 err_free:
4858         kfree(dispc);
4859         return r;
4860 }
4861
4862 static void dispc_unbind(struct device *dev, struct device *master, void *data)
4863 {
4864         struct dispc_device *dispc = dev_get_drvdata(dev);
4865         struct dss_device *dss = dispc->dss;
4866
4867         dss_debugfs_remove_file(dispc->debugfs);
4868
4869         dss->dispc = NULL;
4870         dss->dispc_ops = NULL;
4871
4872         pm_runtime_disable(dev);
4873
4874         dispc_errata_i734_wa_fini(dispc);
4875
4876         kfree(dispc);
4877 }
4878
4879 static const struct component_ops dispc_component_ops = {
4880         .bind   = dispc_bind,
4881         .unbind = dispc_unbind,
4882 };
4883
4884 static int dispc_probe(struct platform_device *pdev)
4885 {
4886         return component_add(&pdev->dev, &dispc_component_ops);
4887 }
4888
4889 static int dispc_remove(struct platform_device *pdev)
4890 {
4891         component_del(&pdev->dev, &dispc_component_ops);
4892         return 0;
4893 }
4894
4895 static int dispc_runtime_suspend(struct device *dev)
4896 {
4897         struct dispc_device *dispc = dev_get_drvdata(dev);
4898
4899         dispc->is_enabled = false;
4900         /* ensure the dispc_irq_handler sees the is_enabled value */
4901         smp_wmb();
4902         /* wait for current handler to finish before turning the DISPC off */
4903         synchronize_irq(dispc->irq);
4904
4905         dispc_save_context(dispc);
4906
4907         return 0;
4908 }
4909
4910 static int dispc_runtime_resume(struct device *dev)
4911 {
4912         struct dispc_device *dispc = dev_get_drvdata(dev);
4913
4914         /*
4915          * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4916          * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4917          * _omap_dispc_initial_config(). We can thus use it to detect if
4918          * we have lost register context.
4919          */
4920         if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4921                 _omap_dispc_initial_config(dispc);
4922
4923                 dispc_errata_i734_wa(dispc);
4924
4925                 dispc_restore_context(dispc);
4926
4927                 dispc_restore_gamma_tables(dispc);
4928         }
4929
4930         dispc->is_enabled = true;
4931         /* ensure the dispc_irq_handler sees the is_enabled value */
4932         smp_wmb();
4933
4934         return 0;
4935 }
4936
4937 static const struct dev_pm_ops dispc_pm_ops = {
4938         .runtime_suspend = dispc_runtime_suspend,
4939         .runtime_resume = dispc_runtime_resume,
4940 };
4941
4942 struct platform_driver omap_dispchw_driver = {
4943         .probe          = dispc_probe,
4944         .remove         = dispc_remove,
4945         .driver         = {
4946                 .name   = "omapdss_dispc",
4947                 .pm     = &dispc_pm_ops,
4948                 .of_match_table = dispc_of_match,
4949                 .suppress_bind_attrs = true,
4950         },
4951 };