2 * linux/drivers/video/omap2/dss/dss.h
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <linux/interrupt.h>
30 #define MAX_DSS_LCD_MANAGERS 3
37 #ifdef DSS_SUBSYS_NAME
38 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
40 #define pr_fmt(fmt) fmt
43 #define DSSDBG(format, ...) \
44 pr_debug(format, ## __VA_ARGS__)
46 #ifdef DSS_SUBSYS_NAME
47 #define DSSERR(format, ...) \
48 pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
50 #define DSSERR(format, ...) \
51 pr_err("omapdss error: " format, ##__VA_ARGS__)
54 #ifdef DSS_SUBSYS_NAME
55 #define DSSINFO(format, ...) \
56 pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
58 #define DSSINFO(format, ...) \
59 pr_info("omapdss: " format, ## __VA_ARGS__)
62 #ifdef DSS_SUBSYS_NAME
63 #define DSSWARN(format, ...) \
64 pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
66 #define DSSWARN(format, ...) \
67 pr_warn("omapdss: " format, ##__VA_ARGS__)
70 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
71 number. For example 7:0 */
72 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
73 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
74 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
75 #define FLD_MOD(orig, val, start, end) \
76 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
86 enum dss_io_pad_mode {
87 DSS_IO_PAD_MODE_RESET,
89 DSS_IO_PAD_MODE_BYPASS,
92 enum dss_hdmi_venc_clk_source_select {
97 enum dss_dsi_content_type {
99 DSS_DSI_CONTENT_GENERIC,
102 enum dss_writeback_channel {
113 enum dss_clk_source {
124 DSS_CLK_SRC_HDMI_PLL,
137 #define DSS_PLL_MAX_HSDIVS 4
145 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
146 * Type-B PLLs: clkout[0] refers to m2.
148 struct dss_pll_clock_info {
149 /* rates that we get with dividers below */
151 unsigned long clkdco;
152 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
158 u16 mX[DSS_PLL_MAX_HSDIVS];
163 int (*enable)(struct dss_pll *pll);
164 void (*disable)(struct dss_pll *pll);
165 int (*set_config)(struct dss_pll *pll,
166 const struct dss_pll_clock_info *cinfo);
170 enum dss_pll_type type;
177 unsigned long fint_min, fint_max;
178 unsigned long clkdco_min, clkdco_low, clkdco_max;
182 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
195 struct regulator *regulator;
199 const struct dss_pll_hw *hw;
201 const struct dss_pll_ops *ops;
203 struct dss_pll_clock_info cinfo;
206 /* Defines a generic omap register field */
207 struct dss_reg_field {
211 struct dispc_clock_info {
212 /* rates that we get with dividers below */
221 struct dss_lcd_mgr_config {
222 enum dss_io_pad_mode io_pad_mode;
227 struct dispc_clock_info clock_info;
229 int video_port_width;
231 int lcden_sig_polarity;
235 struct platform_device;
238 static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
240 /* To be implemented when the OMAP platform will provide this feature */
244 static inline bool dss_mgr_is_lcd(enum omap_channel id)
246 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
247 id == OMAP_DSS_CHANNEL_LCD3)
254 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
255 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
257 static inline int dss_debugfs_create_file(const char *name,
258 void (*write)(struct seq_file *))
262 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */
264 int dss_init_platform_driver(void) __init;
265 void dss_uninit_platform_driver(void);
267 int dss_runtime_get(void);
268 void dss_runtime_put(void);
270 unsigned long dss_get_dispc_clk_rate(void);
271 unsigned long dss_get_max_fck_rate(void);
272 enum omap_dss_output_id dss_get_supported_outputs(enum omap_channel channel);
273 int dss_dpi_select_source(int port, enum omap_channel channel);
274 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
275 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
276 const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
277 void dss_dump_clocks(struct seq_file *s);
280 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
281 struct regulator *regulator);
282 void dss_video_pll_uninit(struct dss_pll *pll);
284 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
286 void dss_sdi_init(int datapairs);
287 int dss_sdi_enable(void);
288 void dss_sdi_disable(void);
290 void dss_select_dsi_clk_source(int dsi_module,
291 enum dss_clk_source clk_src);
292 void dss_select_lcd_clk_source(enum omap_channel channel,
293 enum dss_clk_source clk_src);
294 enum dss_clk_source dss_get_dispc_clk_source(void);
295 enum dss_clk_source dss_get_dsi_clk_source(int dsi_module);
296 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
298 void dss_set_venc_output(enum omap_dss_venc_type type);
299 void dss_set_dac_pwrdn_bgz(bool enable);
301 int dss_set_fck_rate(unsigned long rate);
303 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
304 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
305 dss_div_calc_func func, void *data);
308 #ifdef CONFIG_OMAP2_DSS_SDI
309 int sdi_init_port(struct platform_device *pdev, struct device_node *port);
310 void sdi_uninit_port(struct device_node *port);
312 static inline int sdi_init_port(struct platform_device *pdev,
313 struct device_node *port)
317 static inline void sdi_uninit_port(struct device_node *port)
324 #ifdef CONFIG_OMAP2_DSS_DSI
327 struct file_operations;
329 int dsi_init_platform_driver(void) __init;
330 void dsi_uninit_platform_driver(void);
332 void dsi_dump_clocks(struct seq_file *s);
334 void dsi_irq_handler(void);
339 #ifdef CONFIG_OMAP2_DSS_DPI
340 int dpi_init_port(struct platform_device *pdev, struct device_node *port,
341 enum dss_model dss_model);
342 void dpi_uninit_port(struct device_node *port);
344 static inline int dpi_init_port(struct platform_device *pdev,
345 struct device_node *port, enum dss_model dss_model)
349 static inline void dpi_uninit_port(struct device_node *port)
355 int dispc_init_platform_driver(void) __init;
356 void dispc_uninit_platform_driver(void);
357 void dispc_dump_clocks(struct seq_file *s);
359 int dispc_runtime_get(void);
360 void dispc_runtime_put(void);
362 void dispc_enable_sidle(void);
363 void dispc_disable_sidle(void);
365 void dispc_lcd_enable_signal(bool enable);
366 void dispc_pck_free_enable(bool enable);
367 void dispc_enable_fifomerge(bool enable);
368 void dispc_enable_gamma_table(bool enable);
370 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
371 unsigned long pck, void *data);
372 bool dispc_div_calc(unsigned long dispc,
373 unsigned long pck_min, unsigned long pck_max,
374 dispc_div_calc_func func, void *data);
376 bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm);
377 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
378 struct dispc_clock_info *cinfo);
381 void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
383 void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
384 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
387 void dispc_mgr_set_clock_div(enum omap_channel channel,
388 const struct dispc_clock_info *cinfo);
389 int dispc_mgr_get_clock_div(enum omap_channel channel,
390 struct dispc_clock_info *cinfo);
391 void dispc_set_tv_pclk(unsigned long pclk);
393 u32 dispc_wb_get_framedone_irq(void);
394 bool dispc_wb_go_busy(void);
395 void dispc_wb_go(void);
396 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
397 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
398 bool mem_to_mem, const struct videomode *vm);
401 int venc_init_platform_driver(void) __init;
402 void venc_uninit_platform_driver(void);
405 int hdmi4_init_platform_driver(void) __init;
406 void hdmi4_uninit_platform_driver(void);
408 int hdmi5_init_platform_driver(void) __init;
409 void hdmi5_uninit_platform_driver(void);
412 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
413 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
416 for (b = 0; b < 32; ++b) {
417 if (irqstatus & (1 << b))
424 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
425 unsigned long clkdco, void *data);
426 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
429 int dss_pll_register(struct dss_pll *pll);
430 void dss_pll_unregister(struct dss_pll *pll);
431 struct dss_pll *dss_pll_find(const char *name);
432 struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src);
433 unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
434 int dss_pll_enable(struct dss_pll *pll);
435 void dss_pll_disable(struct dss_pll *pll);
436 int dss_pll_set_config(struct dss_pll *pll,
437 const struct dss_pll_clock_info *cinfo);
439 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
440 unsigned long out_min, unsigned long out_max,
441 dss_hsdiv_calc_func func, void *data);
442 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
443 unsigned long pll_min, unsigned long pll_max,
444 dss_pll_calc_func func, void *data);
446 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
447 unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
449 int dss_pll_write_config_type_a(struct dss_pll *pll,
450 const struct dss_pll_clock_info *cinfo);
451 int dss_pll_write_config_type_b(struct dss_pll *pll,
452 const struct dss_pll_clock_info *cinfo);
453 int dss_pll_wait_reset_done(struct dss_pll *pll);