drivers/gpu/drm/omapdrm/dss/omapdss.h

   1 /*
   2  * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
   3  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __OMAP_DRM_DSS_H
  19 #define __OMAP_DRM_DSS_H
  20
  21 #include <linux/list.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <video/videomode.h>
  25 #include <linux/platform_data/omapdss.h>
  26 #include <uapi/drm/drm_mode.h>
  27 #include <drm/drm_crtc.h>
  28
  29 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
  30 #define DISPC_IRQ_VSYNC                 (1 << 1)
  31 #define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  32 #define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  33 #define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  34 #define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  35 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  36 #define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  37 #define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  38 #define DISPC_IRQ_OCP_ERR               (1 << 9)
  39 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  40 #define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  41 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  42 #define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  43 #define DISPC_IRQ_SYNC_LOST             (1 << 14)
  44 #define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  45 #define DISPC_IRQ_WAKEUP                (1 << 16)
  46 #define DISPC_IRQ_SYNC_LOST2            (1 << 17)
  47 #define DISPC_IRQ_VSYNC2                (1 << 18)
  48 #define DISPC_IRQ_VID3_END_WIN          (1 << 19)
  49 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW   (1 << 20)
  50 #define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
  51 #define DISPC_IRQ_FRAMEDONE2            (1 << 22)
  52 #define DISPC_IRQ_FRAMEDONEWB           (1 << 23)
  53 #define DISPC_IRQ_FRAMEDONETV           (1 << 24)
  54 #define DISPC_IRQ_WBBUFFEROVERFLOW      (1 << 25)
  55 #define DISPC_IRQ_WBUNCOMPLETEERROR     (1 << 26)
  56 #define DISPC_IRQ_SYNC_LOST3            (1 << 27)
  57 #define DISPC_IRQ_VSYNC3                (1 << 28)
  58 #define DISPC_IRQ_ACBIAS_COUNT_STAT3    (1 << 29)
  59 #define DISPC_IRQ_FRAMEDONE3            (1 << 30)
  60
  61 struct dss_device;
  62 struct omap_drm_private;
  63 struct omap_dss_device;
  64 struct dispc_device;
  65 struct dss_device;
  66 struct dss_lcd_mgr_config;
  67 struct snd_aes_iec958;
  68 struct snd_cea_861_aud_if;
  69 struct hdmi_avi_infoframe;
  70 struct drm_connector;
  71
  72 enum omap_display_type {
  73         OMAP_DISPLAY_TYPE_NONE          = 0,
  74         OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  75         OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  76         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  77         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  78         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  79         OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
  80         OMAP_DISPLAY_TYPE_DVI           = 1 << 6,
  81 };
  82
  83 enum omap_plane_id {
  84         OMAP_DSS_GFX    = 0,
  85         OMAP_DSS_VIDEO1 = 1,
  86         OMAP_DSS_VIDEO2 = 2,
  87         OMAP_DSS_VIDEO3 = 3,
  88         OMAP_DSS_WB     = 4,
  89 };
  90
  91 enum omap_channel {
  92         OMAP_DSS_CHANNEL_LCD    = 0,
  93         OMAP_DSS_CHANNEL_DIGIT  = 1,
  94         OMAP_DSS_CHANNEL_LCD2   = 2,
  95         OMAP_DSS_CHANNEL_LCD3   = 3,
  96         OMAP_DSS_CHANNEL_WB     = 4,
  97 };
  98
  99 enum omap_color_mode {
 100         _UNUSED_,
 101 };
 102
 103 enum omap_dss_load_mode {
 104         OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
 105         OMAP_DSS_LOAD_CLUT_ONLY         = 1,
 106         OMAP_DSS_LOAD_FRAME_ONLY        = 2,
 107         OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
 108 };
 109
 110 enum omap_dss_trans_key_type {
 111         OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 112         OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 113 };
 114
 115 enum omap_dss_signal_level {
 116         OMAPDSS_SIG_ACTIVE_LOW,
 117         OMAPDSS_SIG_ACTIVE_HIGH,
 118 };
 119
 120 enum omap_dss_signal_edge {
 121         OMAPDSS_DRIVE_SIG_FALLING_EDGE,
 122         OMAPDSS_DRIVE_SIG_RISING_EDGE,
 123 };
 124
 125 enum omap_dss_venc_type {
 126         OMAP_DSS_VENC_TYPE_COMPOSITE,
 127         OMAP_DSS_VENC_TYPE_SVIDEO,
 128 };
 129
 130 enum omap_dss_dsi_pixel_format {
 131         OMAP_DSS_DSI_FMT_RGB888,
 132         OMAP_DSS_DSI_FMT_RGB666,
 133         OMAP_DSS_DSI_FMT_RGB666_PACKED,
 134         OMAP_DSS_DSI_FMT_RGB565,
 135 };
 136
 137 enum omap_dss_dsi_mode {
 138         OMAP_DSS_DSI_CMD_MODE = 0,
 139         OMAP_DSS_DSI_VIDEO_MODE,
 140 };
 141
 142 enum omap_display_caps {
 143         OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
 144         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
 145 };
 146
 147 enum omap_dss_display_state {
 148         OMAP_DSS_DISPLAY_DISABLED = 0,
 149         OMAP_DSS_DISPLAY_ACTIVE,
 150 };
 151
 152 enum omap_dss_rotation_type {
 153         OMAP_DSS_ROT_NONE       = 0,
 154         OMAP_DSS_ROT_TILER      = 1 << 0,
 155 };
 156
 157 enum omap_overlay_caps {
 158         OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 159         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
 160         OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
 161         OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
 162         OMAP_DSS_OVL_CAP_POS = 1 << 4,
 163         OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
 164 };
 165
 166 enum omap_dss_output_id {
 167         OMAP_DSS_OUTPUT_DPI     = 1 << 0,
 168         OMAP_DSS_OUTPUT_DBI     = 1 << 1,
 169         OMAP_DSS_OUTPUT_SDI     = 1 << 2,
 170         OMAP_DSS_OUTPUT_DSI1    = 1 << 3,
 171         OMAP_DSS_OUTPUT_DSI2    = 1 << 4,
 172         OMAP_DSS_OUTPUT_VENC    = 1 << 5,
 173         OMAP_DSS_OUTPUT_HDMI    = 1 << 6,
 174 };
 175
 176 /* DSI */
 177
 178 enum omap_dss_dsi_trans_mode {
 179         /* Sync Pulses: both sync start and end packets sent */
 180         OMAP_DSS_DSI_PULSE_MODE,
 181         /* Sync Events: only sync start packets sent */
 182         OMAP_DSS_DSI_EVENT_MODE,
 183         /* Burst: only sync start packets sent, pixels are time compressed */
 184         OMAP_DSS_DSI_BURST_MODE,
 185 };
 186
 187 struct omap_dss_dsi_videomode_timings {
 188         unsigned long hsclk;
 189
 190         unsigned int ndl;
 191         unsigned int bitspp;
 192
 193         /* pixels */
 194         u16 hact;
 195         /* lines */
 196         u16 vact;
 197
 198         /* DSI video mode blanking data */
 199         /* Unit: byte clock cycles */
 200         u16 hss;
 201         u16 hsa;
 202         u16 hse;
 203         u16 hfp;
 204         u16 hbp;
 205         /* Unit: line clocks */
 206         u16 vsa;
 207         u16 vfp;
 208         u16 vbp;
 209
 210         /* DSI blanking modes */
 211         int blanking_mode;
 212         int hsa_blanking_mode;
 213         int hbp_blanking_mode;
 214         int hfp_blanking_mode;
 215
 216         enum omap_dss_dsi_trans_mode trans_mode;
 217
 218         bool ddr_clk_always_on;
 219         int window_sync;
 220 };
 221
 222 struct omap_dss_dsi_config {
 223         enum omap_dss_dsi_mode mode;
 224         enum omap_dss_dsi_pixel_format pixel_format;
 225         const struct videomode *vm;
 226
 227         unsigned long hs_clk_min, hs_clk_max;
 228         unsigned long lp_clk_min, lp_clk_max;
 229
 230         bool ddr_clk_always_on;
 231         enum omap_dss_dsi_trans_mode trans_mode;
 232 };
 233
 234 struct omap_dss_cpr_coefs {
 235         s16 rr, rg, rb;
 236         s16 gr, gg, gb;
 237         s16 br, bg, bb;
 238 };
 239
 240 struct omap_overlay_info {
 241         dma_addr_t paddr;
 242         dma_addr_t p_uv_addr;  /* for NV12 format */
 243         u16 screen_width;
 244         u16 width;
 245         u16 height;
 246         u32 fourcc;
 247         u8 rotation;
 248         enum omap_dss_rotation_type rotation_type;
 249
 250         u16 pos_x;
 251         u16 pos_y;
 252         u16 out_width;  /* if 0, out_width == width */
 253         u16 out_height; /* if 0, out_height == height */
 254         u8 global_alpha;
 255         u8 pre_mult_alpha;
 256         u8 zorder;
 257 };
 258
 259 struct omap_overlay_manager_info {
 260         u32 default_color;
 261
 262         enum omap_dss_trans_key_type trans_key_type;
 263         u32 trans_key;
 264         bool trans_enabled;
 265
 266         bool partial_alpha_enabled;
 267
 268         bool cpr_enable;
 269         struct omap_dss_cpr_coefs cpr_coefs;
 270 };
 271
 272 /* 22 pins means 1 clk lane and 10 data lanes */
 273 #define OMAP_DSS_MAX_DSI_PINS 22
 274
 275 struct omap_dsi_pin_config {
 276         int num_pins;
 277         /*
 278          * pin numbers in the following order:
 279          * clk+, clk-
 280          * data1+, data1-
 281          * data2+, data2-
 282          * ...
 283          */
 284         int pins[OMAP_DSS_MAX_DSI_PINS];
 285 };
 286
 287 struct omap_dss_writeback_info {
 288         u32 paddr;
 289         u32 p_uv_addr;
 290         u16 buf_width;
 291         u16 width;
 292         u16 height;
 293         u32 fourcc;
 294         u8 rotation;
 295         enum omap_dss_rotation_type rotation_type;
 296         u8 pre_mult_alpha;
 297 };
 298
 299 struct omapdss_hdmi_ops {
 300         void (*lost_hotplug)(struct omap_dss_device *dssdev);
 301         int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
 302         int (*set_infoframe)(struct omap_dss_device *dssdev,
 303                 const struct hdmi_avi_infoframe *avi);
 304 };
 305
 306 struct omapdss_dsi_ops {
 307         void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
 308                         bool enter_ulps);
 309
 310         /* bus configuration */
 311         int (*set_config)(struct omap_dss_device *dssdev,
 312                         const struct omap_dss_dsi_config *cfg);
 313         int (*configure_pins)(struct omap_dss_device *dssdev,
 314                         const struct omap_dsi_pin_config *pin_cfg);
 315
 316         void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
 317                         bool enable);
 318         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 319
 320         int (*update)(struct omap_dss_device *dssdev, int channel,
 321                         void (*callback)(int, void *), void *data);
 322
 323         void (*bus_lock)(struct omap_dss_device *dssdev);
 324         void (*bus_unlock)(struct omap_dss_device *dssdev);
 325
 326         int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
 327         void (*disable_video_output)(struct omap_dss_device *dssdev,
 328                         int channel);
 329
 330         int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
 331         int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
 332                         int vc_id);
 333         void (*release_vc)(struct omap_dss_device *dssdev, int channel);
 334
 335         /* data transfer */
 336         int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
 337                         u8 *data, int len);
 338         int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
 339                         u8 *data, int len);
 340         int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 341                         u8 *data, int len);
 342
 343         int (*gen_write)(struct omap_dss_device *dssdev, int channel,
 344                         u8 *data, int len);
 345         int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
 346                         u8 *data, int len);
 347         int (*gen_read)(struct omap_dss_device *dssdev, int channel,
 348                         u8 *reqdata, int reqlen,
 349                         u8 *data, int len);
 350
 351         int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
 352
 353         int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
 354                         int channel, u16 plen);
 355 };
 356
 357 struct omap_dss_device_ops {
 358         int (*connect)(struct omap_dss_device *dssdev,
 359                         struct omap_dss_device *dst);
 360         void (*disconnect)(struct omap_dss_device *dssdev,
 361                         struct omap_dss_device *dst);
 362
 363         void (*pre_enable)(struct omap_dss_device *dssdev);
 364         void (*enable)(struct omap_dss_device *dssdev);
 365         void (*disable)(struct omap_dss_device *dssdev);
 366         void (*post_disable)(struct omap_dss_device *dssdev);
 367
 368         int (*check_timings)(struct omap_dss_device *dssdev,
 369                              struct drm_display_mode *mode);
 370         void (*set_timings)(struct omap_dss_device *dssdev,
 371                             const struct drm_display_mode *mode);
 372
 373         bool (*detect)(struct omap_dss_device *dssdev);
 374
 375         void (*register_hpd_cb)(struct omap_dss_device *dssdev,
 376                                 void (*cb)(void *cb_data,
 377                                           enum drm_connector_status status),
 378                                 void *cb_data);
 379         void (*unregister_hpd_cb)(struct omap_dss_device *dssdev);
 380
 381         int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
 382
 383         int (*get_modes)(struct omap_dss_device *dssdev,
 384                          struct drm_connector *connector);
 385
 386         union {
 387                 const struct omapdss_hdmi_ops hdmi;
 388                 const struct omapdss_dsi_ops dsi;
 389         };
 390 };
 391
 392 /**
 393  * enum omap_dss_device_ops_flag - Indicates which device ops are supported
 394  * @OMAP_DSS_DEVICE_OP_DETECT: The device supports output connection detection
 395  * @OMAP_DSS_DEVICE_OP_HPD: The device supports all hot-plug-related operations
 396  * @OMAP_DSS_DEVICE_OP_EDID: The device supports reading EDID
 397  * @OMAP_DSS_DEVICE_OP_MODES: The device supports reading modes
 398  */
 399 enum omap_dss_device_ops_flag {
 400         OMAP_DSS_DEVICE_OP_DETECT = BIT(0),
 401         OMAP_DSS_DEVICE_OP_HPD = BIT(1),
 402         OMAP_DSS_DEVICE_OP_EDID = BIT(2),
 403         OMAP_DSS_DEVICE_OP_MODES = BIT(3),
 404 };
 405
 406 struct omap_dss_device {
 407         struct device *dev;
 408
 409         struct module *owner;
 410
 411         struct dss_device *dss;
 412         struct omap_dss_device *next;
 413         struct drm_bridge *bridge;
 414
 415         struct list_head list;
 416
 417         /*
 418          * DSS type that this device generates (for DSS internal devices) or
 419          * requires (for external encoders, connectors and panels). Must be a
 420          * non-zero (different than OMAP_DISPLAY_TYPE_NONE) value.
 421          */
 422         enum omap_display_type type;
 423
 424         /*
 425          * True if the device is a display (panel or connector) at the end of
 426          * the pipeline, false otherwise.
 427          */
 428         bool display;
 429
 430         const char *name;
 431
 432         const struct omap_dss_driver *driver;
 433         const struct omap_dss_device_ops *ops;
 434         unsigned long ops_flags;
 435         u32 bus_flags;
 436
 437         enum omap_display_caps caps;
 438
 439         enum omap_dss_display_state state;
 440
 441         /* OMAP DSS output specific fields */
 442
 443         /* DISPC channel for this output */
 444         enum omap_channel dispc_channel;
 445
 446         /* output instance */
 447         enum omap_dss_output_id id;
 448
 449         /* bitmask of port numbers in DT */
 450         unsigned int of_ports;
 451 };
 452
 453 struct omap_dss_driver {
 454         int (*update)(struct omap_dss_device *dssdev,
 455                                u16 x, u16 y, u16 w, u16 h);
 456         int (*sync)(struct omap_dss_device *dssdev);
 457
 458         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 459         int (*get_te)(struct omap_dss_device *dssdev);
 460
 461         int (*memory_read)(struct omap_dss_device *dssdev,
 462                         void *buf, size_t size,
 463                         u16 x, u16 y, u16 w, u16 h);
 464 };
 465
 466 struct dss_device *omapdss_get_dss(void);
 467 void omapdss_set_dss(struct dss_device *dss);
 468 static inline bool omapdss_is_initialized(void)
 469 {
 470         return !!omapdss_get_dss();
 471 }
 472
 473 void omapdss_display_init(struct omap_dss_device *dssdev);
 474 struct omap_dss_device *omapdss_display_get(struct omap_dss_device *output);
 475 int omapdss_display_get_modes(struct drm_connector *connector,
 476                               const struct videomode *vm);
 477
 478 void omapdss_device_register(struct omap_dss_device *dssdev);
 479 void omapdss_device_unregister(struct omap_dss_device *dssdev);
 480 struct omap_dss_device *omapdss_device_get(struct omap_dss_device *dssdev);
 481 void omapdss_device_put(struct omap_dss_device *dssdev);
 482 struct omap_dss_device *omapdss_find_device_by_node(struct device_node *node);
 483 int omapdss_device_connect(struct dss_device *dss,
 484                            struct omap_dss_device *src,
 485                            struct omap_dss_device *dst);
 486 void omapdss_device_disconnect(struct omap_dss_device *src,
 487                                struct omap_dss_device *dst);
 488 void omapdss_device_pre_enable(struct omap_dss_device *dssdev);
 489 void omapdss_device_enable(struct omap_dss_device *dssdev);
 490 void omapdss_device_disable(struct omap_dss_device *dssdev);
 491 void omapdss_device_post_disable(struct omap_dss_device *dssdev);
 492
 493 int omap_dss_get_num_overlay_managers(void);
 494
 495 int omap_dss_get_num_overlays(void);
 496
 497 #define for_each_dss_output(d) \
 498         while ((d = omapdss_device_next_output(d)) != NULL)
 499 struct omap_dss_device *omapdss_device_next_output(struct omap_dss_device *from);
 500 int omapdss_device_init_output(struct omap_dss_device *out);
 501 void omapdss_device_cleanup_output(struct omap_dss_device *out);
 502
 503 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 504 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 505 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 506
 507 int omapdss_compat_init(void);
 508 void omapdss_compat_uninit(void);
 509
 510 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
 511 {
 512         return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
 513 }
 514
 515 struct omap_dss_device *
 516 omapdss_of_find_connected_device(struct device_node *node, unsigned int port);
 517
 518 enum dss_writeback_channel {
 519         DSS_WB_LCD1_MGR =       0,
 520         DSS_WB_LCD2_MGR =       1,
 521         DSS_WB_TV_MGR =         2,
 522         DSS_WB_OVL0 =           3,
 523         DSS_WB_OVL1 =           4,
 524         DSS_WB_OVL2 =           5,
 525         DSS_WB_OVL3 =           6,
 526         DSS_WB_LCD3_MGR =       7,
 527 };
 528
 529 struct dss_mgr_ops {
 530         void (*start_update)(struct omap_drm_private *priv,
 531                              enum omap_channel channel);
 532         int (*enable)(struct omap_drm_private *priv,
 533                       enum omap_channel channel);
 534         void (*disable)(struct omap_drm_private *priv,
 535                         enum omap_channel channel);
 536         void (*set_timings)(struct omap_drm_private *priv,
 537                             enum omap_channel channel,
 538                             const struct videomode *vm);
 539         void (*set_lcd_config)(struct omap_drm_private *priv,
 540                                enum omap_channel channel,
 541                                const struct dss_lcd_mgr_config *config);
 542         int (*register_framedone_handler)(struct omap_drm_private *priv,
 543                         enum omap_channel channel,
 544                         void (*handler)(void *), void *data);
 545         void (*unregister_framedone_handler)(struct omap_drm_private *priv,
 546                         enum omap_channel channel,
 547                         void (*handler)(void *), void *data);
 548 };
 549
 550 int dss_install_mgr_ops(struct dss_device *dss,
 551                         const struct dss_mgr_ops *mgr_ops,
 552                         struct omap_drm_private *priv);
 553 void dss_uninstall_mgr_ops(struct dss_device *dss);
 554
 555 void dss_mgr_set_timings(struct omap_dss_device *dssdev,
 556                 const struct videomode *vm);
 557 void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev,
 558                 const struct dss_lcd_mgr_config *config);
 559 int dss_mgr_enable(struct omap_dss_device *dssdev);
 560 void dss_mgr_disable(struct omap_dss_device *dssdev);
 561 void dss_mgr_start_update(struct omap_dss_device *dssdev);
 562 int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev,
 563                 void (*handler)(void *), void *data);
 564 void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,
 565                 void (*handler)(void *), void *data);
 566
 567 /* dispc ops */
 568
 569 struct dispc_ops {
 570         u32 (*read_irqstatus)(struct dispc_device *dispc);
 571         void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask);
 572         void (*write_irqenable)(struct dispc_device *dispc, u32 mask);
 573
 574         int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler,
 575                            void *dev_id);
 576         void (*free_irq)(struct dispc_device *dispc, void *dev_id);
 577
 578         int (*runtime_get)(struct dispc_device *dispc);
 579         void (*runtime_put)(struct dispc_device *dispc);
 580
 581         int (*get_num_ovls)(struct dispc_device *dispc);
 582         int (*get_num_mgrs)(struct dispc_device *dispc);
 583
 584         u32 (*get_memory_bandwidth_limit)(struct dispc_device *dispc);
 585
 586         void (*mgr_enable)(struct dispc_device *dispc,
 587                            enum omap_channel channel, bool enable);
 588         bool (*mgr_is_enabled)(struct dispc_device *dispc,
 589                                enum omap_channel channel);
 590         u32 (*mgr_get_vsync_irq)(struct dispc_device *dispc,
 591                                  enum omap_channel channel);
 592         u32 (*mgr_get_framedone_irq)(struct dispc_device *dispc,
 593                                      enum omap_channel channel);
 594         u32 (*mgr_get_sync_lost_irq)(struct dispc_device *dispc,
 595                                      enum omap_channel channel);
 596         bool (*mgr_go_busy)(struct dispc_device *dispc,
 597                             enum omap_channel channel);
 598         void (*mgr_go)(struct dispc_device *dispc, enum omap_channel channel);
 599         void (*mgr_set_lcd_config)(struct dispc_device *dispc,
 600                                    enum omap_channel channel,
 601                                    const struct dss_lcd_mgr_config *config);
 602         int (*mgr_check_timings)(struct dispc_device *dispc,
 603                                  enum omap_channel channel,
 604                                  const struct videomode *vm);
 605         void (*mgr_set_timings)(struct dispc_device *dispc,
 606                                 enum omap_channel channel,
 607                                 const struct videomode *vm);
 608         void (*mgr_setup)(struct dispc_device *dispc, enum omap_channel channel,
 609                           const struct omap_overlay_manager_info *info);
 610         u32 (*mgr_gamma_size)(struct dispc_device *dispc,
 611                               enum omap_channel channel);
 612         void (*mgr_set_gamma)(struct dispc_device *dispc,
 613                               enum omap_channel channel,
 614                               const struct drm_color_lut *lut,
 615                               unsigned int length);
 616
 617         int (*ovl_enable)(struct dispc_device *dispc, enum omap_plane_id plane,
 618                           bool enable);
 619         int (*ovl_setup)(struct dispc_device *dispc, enum omap_plane_id plane,
 620                          const struct omap_overlay_info *oi,
 621                          const struct videomode *vm, bool mem_to_mem,
 622                          enum omap_channel channel);
 623
 624         const u32 *(*ovl_get_color_modes)(struct dispc_device *dispc,
 625                                           enum omap_plane_id plane);
 626
 627         u32 (*wb_get_framedone_irq)(struct dispc_device *dispc);
 628         int (*wb_setup)(struct dispc_device *dispc,
 629                 const struct omap_dss_writeback_info *wi,
 630                 bool mem_to_mem, const struct videomode *vm,
 631                 enum dss_writeback_channel channel_in);
 632         bool (*has_writeback)(struct dispc_device *dispc);
 633         bool (*wb_go_busy)(struct dispc_device *dispc);
 634         void (*wb_go)(struct dispc_device *dispc);
 635 };
 636
 637 struct dispc_device *dispc_get_dispc(struct dss_device *dss);
 638 const struct dispc_ops *dispc_get_ops(struct dss_device *dss);
 639
 640 bool omapdss_stack_is_ready(void);
 641 void omapdss_gather_components(struct device *dev);
 642
 643 #endif /* __OMAP_DRM_DSS_H */