2 * Copyright (C) 2009 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #define DSS_SUBSYS_NAME "SDI"
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/export.h>
25 #include <linux/platform_device.h>
26 #include <linux/string.h>
33 struct platform_device *pdev;
34 struct dss_device *dss;
37 struct regulator *vdds_sdi_reg;
39 struct dss_lcd_mgr_config mgr_config;
40 unsigned long pixelclock;
43 struct omap_dss_device output;
46 #define dssdev_to_sdi(dssdev) container_of(dssdev, struct sdi_device, output)
48 struct sdi_clk_calc_ctx {
49 struct sdi_device *sdi;
50 unsigned long pck_min, pck_max;
53 struct dispc_clock_info dispc_cinfo;
56 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
57 unsigned long pck, void *data)
59 struct sdi_clk_calc_ctx *ctx = data;
61 ctx->dispc_cinfo.lck_div = lckd;
62 ctx->dispc_cinfo.pck_div = pckd;
63 ctx->dispc_cinfo.lck = lck;
64 ctx->dispc_cinfo.pck = pck;
69 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
71 struct sdi_clk_calc_ctx *ctx = data;
75 return dispc_div_calc(ctx->sdi->dss->dispc, fck,
76 ctx->pck_min, ctx->pck_max,
77 dpi_calc_dispc_cb, ctx);
80 static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk,
82 struct dispc_clock_info *dispc_cinfo)
85 struct sdi_clk_calc_ctx ctx;
88 * DSS fclk gives us very few possibilities, so finding a good pixel
89 * clock may not be possible. We try multiple times to find the clock,
90 * each time widening the pixel clock range we look for, up to
94 for (i = 0; i < 10; ++i) {
97 memset(&ctx, 0, sizeof(ctx));
101 if (pclk > 1000 * i * i * i)
102 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
105 ctx.pck_max = pclk + 1000 * i * i * i;
107 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min,
108 dpi_calc_dss_cb, &ctx);
111 *dispc_cinfo = ctx.dispc_cinfo;
119 static void sdi_config_lcd_manager(struct sdi_device *sdi)
121 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
123 sdi->mgr_config.stallmode = false;
124 sdi->mgr_config.fifohandcheck = false;
126 sdi->mgr_config.video_port_width = 24;
127 sdi->mgr_config.lcden_sig_polarity = 1;
129 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config);
132 static void sdi_display_enable(struct omap_dss_device *dssdev)
134 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
135 struct dispc_clock_info dispc_cinfo;
139 r = regulator_enable(sdi->vdds_sdi_reg);
143 r = dispc_runtime_get(sdi->dss->dispc);
147 r = sdi_calc_clock_div(sdi, sdi->pixelclock, &fck, &dispc_cinfo);
149 goto err_calc_clock_div;
151 sdi->mgr_config.clock_info = dispc_cinfo;
153 r = dss_set_fck_rate(sdi->dss, fck);
155 goto err_set_dss_clock_div;
157 sdi_config_lcd_manager(sdi);
160 * LCLK and PCLK divisors are located in shadow registers, and we
161 * normally write them to DISPC registers when enabling the output.
162 * However, SDI uses pck-free as source clock for its PLL, and pck-free
163 * is affected by the divisors. And as we need the PLL before enabling
164 * the output, we need to write the divisors early.
166 * It seems just writing to the DISPC register is enough, and we don't
167 * need to care about the shadow register mechanism for pck-free. The
168 * exact reason for this is unknown.
170 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel,
171 &sdi->mgr_config.clock_info);
173 dss_sdi_init(sdi->dss, sdi->datapairs);
174 r = dss_sdi_enable(sdi->dss);
179 r = dss_mgr_enable(&sdi->output);
186 dss_sdi_disable(sdi->dss);
188 err_set_dss_clock_div:
190 dispc_runtime_put(sdi->dss->dispc);
192 regulator_disable(sdi->vdds_sdi_reg);
195 static void sdi_display_disable(struct omap_dss_device *dssdev)
197 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
199 dss_mgr_disable(&sdi->output);
201 dss_sdi_disable(sdi->dss);
203 dispc_runtime_put(sdi->dss->dispc);
205 regulator_disable(sdi->vdds_sdi_reg);
208 static void sdi_set_timings(struct omap_dss_device *dssdev,
209 const struct drm_display_mode *mode)
211 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
213 sdi->pixelclock = mode->clock * 1000;
216 static int sdi_check_timings(struct omap_dss_device *dssdev,
217 struct drm_display_mode *mode)
219 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
220 struct dispc_clock_info dispc_cinfo;
221 unsigned long pixelclock = mode->clock * 1000;
229 r = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo);
233 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
235 if (pck != pixelclock) {
236 DSSWARN("Pixel clock adjusted from %lu Hz to %lu Hz\n",
239 mode->clock = pck / 1000;
245 static int sdi_connect(struct omap_dss_device *src,
246 struct omap_dss_device *dst)
248 return omapdss_device_connect(dst->dss, dst, dst->next);
251 static void sdi_disconnect(struct omap_dss_device *src,
252 struct omap_dss_device *dst)
254 omapdss_device_disconnect(dst, dst->next);
257 static const struct omap_dss_device_ops sdi_ops = {
258 .connect = sdi_connect,
259 .disconnect = sdi_disconnect,
261 .enable = sdi_display_enable,
262 .disable = sdi_display_disable,
264 .check_timings = sdi_check_timings,
265 .set_timings = sdi_set_timings,
268 static int sdi_init_output(struct sdi_device *sdi)
270 struct omap_dss_device *out = &sdi->output;
273 out->dev = &sdi->pdev->dev;
274 out->id = OMAP_DSS_OUTPUT_SDI;
275 out->type = OMAP_DISPLAY_TYPE_SDI;
277 out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
278 /* We have SDI only on OMAP3, where it's on port 1 */
279 out->of_ports = BIT(1);
281 out->owner = THIS_MODULE;
282 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE /* 15.5.9.1.2 */
283 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE;
285 r = omapdss_device_init_output(out);
289 omapdss_device_register(out);
294 static void sdi_uninit_output(struct sdi_device *sdi)
296 omapdss_device_unregister(&sdi->output);
297 omapdss_device_cleanup_output(&sdi->output);
300 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
301 struct device_node *port)
303 struct sdi_device *sdi;
304 struct device_node *ep;
308 sdi = kzalloc(sizeof(*sdi), GFP_KERNEL);
312 ep = of_get_next_child(port, NULL);
318 r = of_property_read_u32(ep, "datapairs", &datapairs);
321 DSSERR("failed to parse datapairs\n");
325 sdi->datapairs = datapairs;
331 sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi");
332 if (IS_ERR(sdi->vdds_sdi_reg)) {
333 r = PTR_ERR(sdi->vdds_sdi_reg);
334 if (r != -EPROBE_DEFER)
335 DSSERR("can't get VDDS_SDI regulator\n");
339 r = sdi_init_output(sdi);
351 void sdi_uninit_port(struct device_node *port)
353 struct sdi_device *sdi = port->data;
358 sdi_uninit_output(sdi);