2 * Copyright (C) 2009 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 * VENC settings from TI's DSS driver
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "VENC"
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
27 #include <linux/mutex.h>
28 #include <linux/completion.h>
29 #include <linux/delay.h>
30 #include <linux/string.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/pm_runtime.h>
36 #include <linux/of_graph.h>
37 #include <linux/component.h>
38 #include <linux/sys_soc.h>
44 #define VENC_REV_ID 0x00
45 #define VENC_STATUS 0x04
46 #define VENC_F_CONTROL 0x08
47 #define VENC_VIDOUT_CTRL 0x10
48 #define VENC_SYNC_CTRL 0x14
49 #define VENC_LLEN 0x1C
50 #define VENC_FLENS 0x20
51 #define VENC_HFLTR_CTRL 0x24
52 #define VENC_CC_CARR_WSS_CARR 0x28
53 #define VENC_C_PHASE 0x2C
54 #define VENC_GAIN_U 0x30
55 #define VENC_GAIN_V 0x34
56 #define VENC_GAIN_Y 0x38
57 #define VENC_BLACK_LEVEL 0x3C
58 #define VENC_BLANK_LEVEL 0x40
59 #define VENC_X_COLOR 0x44
60 #define VENC_M_CONTROL 0x48
61 #define VENC_BSTAMP_WSS_DATA 0x4C
62 #define VENC_S_CARR 0x50
63 #define VENC_LINE21 0x54
64 #define VENC_LN_SEL 0x58
65 #define VENC_L21__WC_CTL 0x5C
66 #define VENC_HTRIGGER_VTRIGGER 0x60
67 #define VENC_SAVID__EAVID 0x64
68 #define VENC_FLEN__FAL 0x68
69 #define VENC_LAL__PHASE_RESET 0x6C
70 #define VENC_HS_INT_START_STOP_X 0x70
71 #define VENC_HS_EXT_START_STOP_X 0x74
72 #define VENC_VS_INT_START_X 0x78
73 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
74 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
75 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
76 #define VENC_VS_EXT_STOP_Y 0x88
77 #define VENC_AVID_START_STOP_X 0x90
78 #define VENC_AVID_START_STOP_Y 0x94
79 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
80 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
81 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
82 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
83 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
84 #define VENC_GEN_CTRL 0xB8
85 #define VENC_OUTPUT_CONTROL 0xC4
86 #define VENC_OUTPUT_TEST 0xC8
87 #define VENC_DAC_B__DAC_C 0xC8
110 u32 htrigger_vtrigger;
113 u32 lal__phase_reset;
114 u32 hs_int_start_stop_x;
115 u32 hs_ext_start_stop_x;
117 u32 vs_int_stop_x__vs_int_start_y;
118 u32 vs_int_stop_y__vs_ext_start_x;
119 u32 vs_ext_stop_x__vs_ext_start_y;
121 u32 avid_start_stop_x;
122 u32 avid_start_stop_y;
123 u32 fid_int_start_x__fid_int_start_y;
124 u32 fid_int_offset_y__fid_ext_start_x;
125 u32 fid_ext_start_y__fid_ext_offset_y;
126 u32 tvdetgp_int_start_stop_x;
127 u32 tvdetgp_int_start_stop_y;
132 static const struct venc_config venc_config_pal_trm = {
136 .llen = 0x35F, /* 863 */
137 .flens = 0x270, /* 624 */
139 .cc_carr_wss_carr = 0x2F7225ED,
148 .bstamp_wss_data = 0x3F,
149 .s_carr = 0x2A098ACB,
151 .ln_sel = 0x01290015,
152 .l21__wc_ctl = 0x0000F603,
153 .htrigger_vtrigger = 0,
155 .savid__eavid = 0x06A70108,
156 .flen__fal = 0x00180270,
157 .lal__phase_reset = 0x00040135,
158 .hs_int_start_stop_x = 0x00880358,
159 .hs_ext_start_stop_x = 0x000F035F,
160 .vs_int_start_x = 0x01A70000,
161 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
162 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
163 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
164 .vs_ext_stop_y = 0x00000025,
165 .avid_start_stop_x = 0x03530083,
166 .avid_start_stop_y = 0x026C002E,
167 .fid_int_start_x__fid_int_start_y = 0x0001008A,
168 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
169 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
171 .tvdetgp_int_start_stop_x = 0x00140001,
172 .tvdetgp_int_start_stop_y = 0x00010001,
173 .gen_ctrl = 0x00FF0000,
177 static const struct venc_config venc_config_ntsc_trm = {
184 .cc_carr_wss_carr = 0x043F2631,
193 .bstamp_wss_data = 0x38,
194 .s_carr = 0x21F07C1F,
196 .ln_sel = 0x01310011,
197 .l21__wc_ctl = 0x0000F003,
198 .htrigger_vtrigger = 0,
200 .savid__eavid = 0x069300F4,
201 .flen__fal = 0x0016020C,
202 .lal__phase_reset = 0x00060107,
203 .hs_int_start_stop_x = 0x008E0350,
204 .hs_ext_start_stop_x = 0x000F0359,
205 .vs_int_start_x = 0x01A00000,
206 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
207 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
208 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
209 .vs_ext_stop_y = 0x00000006,
210 .avid_start_stop_x = 0x03480078,
211 .avid_start_stop_y = 0x02060024,
212 .fid_int_start_x__fid_int_start_y = 0x0001008A,
213 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
214 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
216 .tvdetgp_int_start_stop_x = 0x00140001,
217 .tvdetgp_int_start_stop_y = 0x00010001,
218 .gen_ctrl = 0x00F90000,
221 static const struct venc_config venc_config_pal_bdghi = {
229 .htrigger_vtrigger = 0,
230 .tvdetgp_int_start_stop_x = 0x00140001,
231 .tvdetgp_int_start_stop_y = 0x00010001,
232 .gen_ctrl = 0x00FB0000,
236 .cc_carr_wss_carr = 0x2F7625ED,
243 .m_control = 0<<2 | 1<<1,
244 .bstamp_wss_data = 0x42,
245 .s_carr = 0x2a098acb,
246 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
247 .savid__eavid = 0x06A70108,
248 .flen__fal = 23<<16 | 624<<0,
249 .lal__phase_reset = 2<<17 | 310<<0,
250 .hs_int_start_stop_x = 0x00920358,
251 .hs_ext_start_stop_x = 0x000F035F,
252 .vs_int_start_x = 0x1a7<<16,
253 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
254 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
255 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
256 .vs_ext_stop_y = 0x05,
257 .avid_start_stop_x = 0x03530082,
258 .avid_start_stop_y = 0x0270002E,
259 .fid_int_start_x__fid_int_start_y = 0x0005008A,
260 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
261 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
264 enum venc_videomode {
270 static const struct videomode omap_dss_pal_vm = {
273 .pixelclock = 13500000,
281 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
282 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
283 DISPLAY_FLAGS_PIXDATA_POSEDGE |
284 DISPLAY_FLAGS_SYNC_NEGEDGE,
287 static const struct videomode omap_dss_ntsc_vm = {
290 .pixelclock = 13500000,
298 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
299 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
300 DISPLAY_FLAGS_PIXDATA_POSEDGE |
301 DISPLAY_FLAGS_SYNC_NEGEDGE,
305 struct platform_device *pdev;
307 struct mutex venc_lock;
308 struct regulator *vdda_dac_reg;
309 struct dss_device *dss;
311 struct dss_debugfs_entry *debugfs;
313 struct clk *tv_dac_clk;
315 const struct venc_config *config;
316 enum omap_dss_venc_type type;
317 bool invert_polarity;
318 bool requires_tv_dac_clk;
320 struct omap_dss_device output;
323 #define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output)
325 static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val)
327 __raw_writel(val, venc->base + idx);
330 static inline u32 venc_read_reg(struct venc_device *venc, int idx)
332 u32 l = __raw_readl(venc->base + idx);
336 static void venc_write_config(struct venc_device *venc,
337 const struct venc_config *config)
339 DSSDBG("write venc conf\n");
341 venc_write_reg(venc, VENC_LLEN, config->llen);
342 venc_write_reg(venc, VENC_FLENS, config->flens);
343 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
344 venc_write_reg(venc, VENC_C_PHASE, config->c_phase);
345 venc_write_reg(venc, VENC_GAIN_U, config->gain_u);
346 venc_write_reg(venc, VENC_GAIN_V, config->gain_v);
347 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y);
348 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level);
349 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level);
350 venc_write_reg(venc, VENC_M_CONTROL, config->m_control);
351 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
352 venc_write_reg(venc, VENC_S_CARR, config->s_carr);
353 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl);
354 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid);
355 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal);
356 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset);
357 venc_write_reg(venc, VENC_HS_INT_START_STOP_X,
358 config->hs_int_start_stop_x);
359 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X,
360 config->hs_ext_start_stop_x);
361 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x);
362 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y,
363 config->vs_int_stop_x__vs_int_start_y);
364 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X,
365 config->vs_int_stop_y__vs_ext_start_x);
366 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
367 config->vs_ext_stop_x__vs_ext_start_y);
368 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
369 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x);
370 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
371 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y,
372 config->fid_int_start_x__fid_int_start_y);
373 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
374 config->fid_int_offset_y__fid_ext_start_x);
375 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
376 config->fid_ext_start_y__fid_ext_offset_y);
378 venc_write_reg(venc, VENC_DAC_B__DAC_C,
379 venc_read_reg(venc, VENC_DAC_B__DAC_C));
380 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl);
381 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl);
382 venc_write_reg(venc, VENC_X_COLOR, config->x_color);
383 venc_write_reg(venc, VENC_LINE21, config->line21);
384 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel);
385 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
386 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X,
387 config->tvdetgp_int_start_stop_x);
388 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y,
389 config->tvdetgp_int_start_stop_y);
390 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl);
391 venc_write_reg(venc, VENC_F_CONTROL, config->f_control);
392 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl);
395 static void venc_reset(struct venc_device *venc)
399 venc_write_reg(venc, VENC_F_CONTROL, 1<<8);
400 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) {
402 DSSERR("Failed to reset venc\n");
407 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
408 /* the magical sleep that makes things work */
409 /* XXX more info? What bug this circumvents? */
414 static int venc_runtime_get(struct venc_device *venc)
418 DSSDBG("venc_runtime_get\n");
420 r = pm_runtime_get_sync(&venc->pdev->dev);
422 return r < 0 ? r : 0;
425 static void venc_runtime_put(struct venc_device *venc)
429 DSSDBG("venc_runtime_put\n");
431 r = pm_runtime_put_sync(&venc->pdev->dev);
432 WARN_ON(r < 0 && r != -ENOSYS);
435 static int venc_power_on(struct venc_device *venc)
440 r = venc_runtime_get(venc);
445 venc_write_config(venc, venc->config);
447 dss_set_venc_output(venc->dss, venc->type);
448 dss_set_dac_pwrdn_bgz(venc->dss, 1);
452 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE)
455 l |= (1 << 0) | (1 << 2);
457 if (venc->invert_polarity == false)
460 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l);
462 r = regulator_enable(venc->vdda_dac_reg);
466 r = dss_mgr_enable(&venc->output);
473 regulator_disable(venc->vdda_dac_reg);
475 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
476 dss_set_dac_pwrdn_bgz(venc->dss, 0);
478 venc_runtime_put(venc);
483 static void venc_power_off(struct venc_device *venc)
485 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
486 dss_set_dac_pwrdn_bgz(venc->dss, 0);
488 dss_mgr_disable(&venc->output);
490 regulator_disable(venc->vdda_dac_reg);
492 venc_runtime_put(venc);
495 static void venc_display_enable(struct omap_dss_device *dssdev)
497 struct venc_device *venc = dssdev_to_venc(dssdev);
499 DSSDBG("venc_display_enable\n");
501 mutex_lock(&venc->venc_lock);
505 mutex_unlock(&venc->venc_lock);
508 static void venc_display_disable(struct omap_dss_device *dssdev)
510 struct venc_device *venc = dssdev_to_venc(dssdev);
512 DSSDBG("venc_display_disable\n");
514 mutex_lock(&venc->venc_lock);
516 venc_power_off(venc);
518 mutex_unlock(&venc->venc_lock);
521 static int venc_get_modes(struct omap_dss_device *dssdev,
522 struct drm_connector *connector)
524 static const struct videomode *modes[] = {
530 for (i = 0; i < ARRAY_SIZE(modes); ++i) {
531 struct drm_display_mode *mode;
533 mode = drm_mode_create(connector->dev);
537 drm_display_mode_from_videomode(modes[i], mode);
539 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
540 drm_mode_set_name(mode);
541 drm_mode_probed_add(connector, mode);
544 return ARRAY_SIZE(modes);
547 static enum venc_videomode venc_get_videomode(const struct drm_display_mode *mode)
549 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
550 return VENC_MODE_UNKNOWN;
552 if (mode->clock == omap_dss_pal_vm.pixelclock / 1000 &&
553 mode->hdisplay == omap_dss_pal_vm.hactive &&
554 mode->vdisplay == omap_dss_pal_vm.vactive)
555 return VENC_MODE_PAL;
557 if (mode->clock == omap_dss_ntsc_vm.pixelclock / 1000 &&
558 mode->hdisplay == omap_dss_ntsc_vm.hactive &&
559 mode->vdisplay == omap_dss_ntsc_vm.vactive)
560 return VENC_MODE_NTSC;
562 return VENC_MODE_UNKNOWN;
565 static void venc_set_timings(struct omap_dss_device *dssdev,
566 const struct drm_display_mode *mode)
568 struct venc_device *venc = dssdev_to_venc(dssdev);
569 enum venc_videomode venc_mode = venc_get_videomode(mode);
571 DSSDBG("venc_set_timings\n");
573 mutex_lock(&venc->venc_lock);
580 venc->config = &venc_config_pal_trm;
584 venc->config = &venc_config_ntsc_trm;
588 dispc_set_tv_pclk(venc->dss->dispc, 13500000);
590 mutex_unlock(&venc->venc_lock);
593 static int venc_check_timings(struct omap_dss_device *dssdev,
594 struct drm_display_mode *mode)
596 DSSDBG("venc_check_timings\n");
598 switch (venc_get_videomode(mode)) {
600 drm_display_mode_from_videomode(&omap_dss_pal_vm, mode);
604 drm_display_mode_from_videomode(&omap_dss_ntsc_vm, mode);
612 static int venc_dump_regs(struct seq_file *s, void *p)
614 struct venc_device *venc = s->private;
616 #define DUMPREG(venc, r) \
617 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r))
619 if (venc_runtime_get(venc))
622 DUMPREG(venc, VENC_F_CONTROL);
623 DUMPREG(venc, VENC_VIDOUT_CTRL);
624 DUMPREG(venc, VENC_SYNC_CTRL);
625 DUMPREG(venc, VENC_LLEN);
626 DUMPREG(venc, VENC_FLENS);
627 DUMPREG(venc, VENC_HFLTR_CTRL);
628 DUMPREG(venc, VENC_CC_CARR_WSS_CARR);
629 DUMPREG(venc, VENC_C_PHASE);
630 DUMPREG(venc, VENC_GAIN_U);
631 DUMPREG(venc, VENC_GAIN_V);
632 DUMPREG(venc, VENC_GAIN_Y);
633 DUMPREG(venc, VENC_BLACK_LEVEL);
634 DUMPREG(venc, VENC_BLANK_LEVEL);
635 DUMPREG(venc, VENC_X_COLOR);
636 DUMPREG(venc, VENC_M_CONTROL);
637 DUMPREG(venc, VENC_BSTAMP_WSS_DATA);
638 DUMPREG(venc, VENC_S_CARR);
639 DUMPREG(venc, VENC_LINE21);
640 DUMPREG(venc, VENC_LN_SEL);
641 DUMPREG(venc, VENC_L21__WC_CTL);
642 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER);
643 DUMPREG(venc, VENC_SAVID__EAVID);
644 DUMPREG(venc, VENC_FLEN__FAL);
645 DUMPREG(venc, VENC_LAL__PHASE_RESET);
646 DUMPREG(venc, VENC_HS_INT_START_STOP_X);
647 DUMPREG(venc, VENC_HS_EXT_START_STOP_X);
648 DUMPREG(venc, VENC_VS_INT_START_X);
649 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y);
650 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X);
651 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
652 DUMPREG(venc, VENC_VS_EXT_STOP_Y);
653 DUMPREG(venc, VENC_AVID_START_STOP_X);
654 DUMPREG(venc, VENC_AVID_START_STOP_Y);
655 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y);
656 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
657 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
658 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X);
659 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y);
660 DUMPREG(venc, VENC_GEN_CTRL);
661 DUMPREG(venc, VENC_OUTPUT_CONTROL);
662 DUMPREG(venc, VENC_OUTPUT_TEST);
664 venc_runtime_put(venc);
670 static int venc_get_clocks(struct venc_device *venc)
674 if (venc->requires_tv_dac_clk) {
675 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk");
677 DSSERR("can't get tv_dac_clk\n");
684 venc->tv_dac_clk = clk;
689 static int venc_connect(struct omap_dss_device *src,
690 struct omap_dss_device *dst)
692 return omapdss_device_connect(dst->dss, dst, dst->next);
695 static void venc_disconnect(struct omap_dss_device *src,
696 struct omap_dss_device *dst)
698 omapdss_device_disconnect(dst, dst->next);
701 static const struct omap_dss_device_ops venc_ops = {
702 .connect = venc_connect,
703 .disconnect = venc_disconnect,
705 .enable = venc_display_enable,
706 .disable = venc_display_disable,
708 .check_timings = venc_check_timings,
709 .set_timings = venc_set_timings,
711 .get_modes = venc_get_modes,
714 /* -----------------------------------------------------------------------------
715 * Component Bind & Unbind
718 static int venc_bind(struct device *dev, struct device *master, void *data)
720 struct dss_device *dss = dss_get_device(master);
721 struct venc_device *venc = dev_get_drvdata(dev);
727 r = venc_runtime_get(venc);
731 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff);
732 dev_dbg(dev, "OMAP VENC rev %d\n", rev_id);
734 venc_runtime_put(venc);
736 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs,
742 static void venc_unbind(struct device *dev, struct device *master, void *data)
744 struct venc_device *venc = dev_get_drvdata(dev);
746 dss_debugfs_remove_file(venc->debugfs);
749 static const struct component_ops venc_component_ops = {
751 .unbind = venc_unbind,
754 /* -----------------------------------------------------------------------------
755 * Probe & Remove, Suspend & Resume
758 static int venc_init_output(struct venc_device *venc)
760 struct omap_dss_device *out = &venc->output;
763 out->dev = &venc->pdev->dev;
764 out->id = OMAP_DSS_OUTPUT_VENC;
765 out->output_type = OMAP_DISPLAY_TYPE_VENC;
766 out->name = "venc.0";
767 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
768 out->ops = &venc_ops;
769 out->owner = THIS_MODULE;
770 out->of_ports = BIT(0);
771 out->ops_flags = OMAP_DSS_DEVICE_OP_MODES;
773 r = omapdss_device_init_output(out);
777 omapdss_device_register(out);
782 static void venc_uninit_output(struct venc_device *venc)
784 omapdss_device_unregister(&venc->output);
785 omapdss_device_cleanup_output(&venc->output);
788 static int venc_probe_of(struct venc_device *venc)
790 struct device_node *node = venc->pdev->dev.of_node;
791 struct device_node *ep;
795 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
799 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
801 r = of_property_read_u32(ep, "ti,channels", &channels);
803 dev_err(&venc->pdev->dev,
804 "failed to read property 'ti,channels': %d\n", r);
810 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE;
813 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO;
816 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n",
831 static const struct soc_device_attribute venc_soc_devices[] = {
832 { .machine = "OMAP3[45]*" },
833 { .machine = "AM35*" },
837 static int venc_probe(struct platform_device *pdev)
839 struct venc_device *venc;
840 struct resource *venc_mem;
843 venc = kzalloc(sizeof(*venc), GFP_KERNEL);
849 platform_set_drvdata(pdev, venc);
851 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */
852 if (soc_device_match(venc_soc_devices))
853 venc->requires_tv_dac_clk = true;
855 mutex_init(&venc->venc_lock);
857 venc->config = &venc_config_pal_trm;
859 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0);
860 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem);
861 if (IS_ERR(venc->base)) {
862 r = PTR_ERR(venc->base);
866 venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda");
867 if (IS_ERR(venc->vdda_dac_reg)) {
868 r = PTR_ERR(venc->vdda_dac_reg);
869 if (r != -EPROBE_DEFER)
870 DSSERR("can't get VDDA_DAC regulator\n");
874 r = venc_get_clocks(venc);
878 r = venc_probe_of(venc);
882 pm_runtime_enable(&pdev->dev);
884 r = venc_init_output(venc);
888 r = component_add(&pdev->dev, &venc_component_ops);
890 goto err_uninit_output;
895 venc_uninit_output(venc);
897 pm_runtime_disable(&pdev->dev);
903 static int venc_remove(struct platform_device *pdev)
905 struct venc_device *venc = platform_get_drvdata(pdev);
907 component_del(&pdev->dev, &venc_component_ops);
909 venc_uninit_output(venc);
911 pm_runtime_disable(&pdev->dev);
917 static int venc_runtime_suspend(struct device *dev)
919 struct venc_device *venc = dev_get_drvdata(dev);
921 if (venc->tv_dac_clk)
922 clk_disable_unprepare(venc->tv_dac_clk);
927 static int venc_runtime_resume(struct device *dev)
929 struct venc_device *venc = dev_get_drvdata(dev);
931 if (venc->tv_dac_clk)
932 clk_prepare_enable(venc->tv_dac_clk);
937 static const struct dev_pm_ops venc_pm_ops = {
938 .runtime_suspend = venc_runtime_suspend,
939 .runtime_resume = venc_runtime_resume,
942 static const struct of_device_id venc_of_match[] = {
943 { .compatible = "ti,omap2-venc", },
944 { .compatible = "ti,omap3-venc", },
945 { .compatible = "ti,omap4-venc", },
949 struct platform_driver omap_venchw_driver = {
951 .remove = venc_remove,
953 .name = "omapdss_venc",
955 .of_match_table = venc_of_match,
956 .suppress_bind_attrs = true,