drivers/gpu/drm/omapdrm/omap_irq.c

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  * Author: Rob Clark <rob.clark@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "omap_drv.h"
  19
  20 struct omap_irq_wait {
  21         struct list_head node;
  22         wait_queue_head_t wq;
  23         u32 irqmask;
  24         int count;
  25 };
  26
  27 /* call with wait_lock and dispc runtime held */
  28 static void omap_irq_update(struct drm_device *dev)
  29 {
  30         struct omap_drm_private *priv = dev->dev_private;
  31         struct omap_irq_wait *wait;
  32         u32 irqmask = priv->irq_mask;
  33
  34         assert_spin_locked(&priv->wait_lock);
  35
  36         list_for_each_entry(wait, &priv->wait_list, node)
  37                 irqmask |= wait->irqmask;
  38
  39         DBG("irqmask=%08x", irqmask);
  40
  41         priv->dispc_ops->write_irqenable(priv->dispc, irqmask);
  42 }
  43
  44 static void omap_irq_wait_handler(struct omap_irq_wait *wait)
  45 {
  46         wait->count--;
  47         wake_up(&wait->wq);
  48 }
  49
  50 struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev,
  51                 u32 irqmask, int count)
  52 {
  53         struct omap_drm_private *priv = dev->dev_private;
  54         struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL);
  55         unsigned long flags;
  56
  57         init_waitqueue_head(&wait->wq);
  58         wait->irqmask = irqmask;
  59         wait->count = count;
  60
  61         spin_lock_irqsave(&priv->wait_lock, flags);
  62         list_add(&wait->node, &priv->wait_list);
  63         omap_irq_update(dev);
  64         spin_unlock_irqrestore(&priv->wait_lock, flags);
  65
  66         return wait;
  67 }
  68
  69 int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait,
  70                 unsigned long timeout)
  71 {
  72         struct omap_drm_private *priv = dev->dev_private;
  73         unsigned long flags;
  74         int ret;
  75
  76         ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout);
  77
  78         spin_lock_irqsave(&priv->wait_lock, flags);
  79         list_del(&wait->node);
  80         omap_irq_update(dev);
  81         spin_unlock_irqrestore(&priv->wait_lock, flags);
  82
  83         kfree(wait);
  84
  85         return ret == 0 ? -1 : 0;
  86 }
  87
  88 int omap_irq_enable_framedone(struct drm_crtc *crtc, bool enable)
  89 {
  90         struct drm_device *dev = crtc->dev;
  91         struct omap_drm_private *priv = dev->dev_private;
  92         unsigned long flags;
  93         enum omap_channel channel = omap_crtc_channel(crtc);
  94         int framedone_irq =
  95                 priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel);
  96
  97         DBG("dev=%p, crtc=%u, enable=%d", dev, channel, enable);
  98
  99         spin_lock_irqsave(&priv->wait_lock, flags);
 100         if (enable)
 101                 priv->irq_mask |= framedone_irq;
 102         else
 103                 priv->irq_mask &= ~framedone_irq;
 104         omap_irq_update(dev);
 105         spin_unlock_irqrestore(&priv->wait_lock, flags);
 106
 107         return 0;
 108 }
 109
 110 /**
 111  * enable_vblank - enable vblank interrupt events
 112  * @dev: DRM device
 113  * @pipe: which irq to enable
 114  *
 115  * Enable vblank interrupts for @crtc.  If the device doesn't have
 116  * a hardware vblank counter, this routine should be a no-op, since
 117  * interrupts will have to stay on to keep the count accurate.
 118  *
 119  * RETURNS
 120  * Zero on success, appropriate errno if the given @crtc's vblank
 121  * interrupt cannot be enabled.
 122  */
 123 int omap_irq_enable_vblank(struct drm_crtc *crtc)
 124 {
 125         struct drm_device *dev = crtc->dev;
 126         struct omap_drm_private *priv = dev->dev_private;
 127         unsigned long flags;
 128         enum omap_channel channel = omap_crtc_channel(crtc);
 129
 130         DBG("dev=%p, crtc=%u", dev, channel);
 131
 132         spin_lock_irqsave(&priv->wait_lock, flags);
 133         priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
 134                                                              channel);
 135         omap_irq_update(dev);
 136         spin_unlock_irqrestore(&priv->wait_lock, flags);
 137
 138         return 0;
 139 }
 140
 141 /**
 142  * disable_vblank - disable vblank interrupt events
 143  * @dev: DRM device
 144  * @pipe: which irq to enable
 145  *
 146  * Disable vblank interrupts for @crtc.  If the device doesn't have
 147  * a hardware vblank counter, this routine should be a no-op, since
 148  * interrupts will have to stay on to keep the count accurate.
 149  */
 150 void omap_irq_disable_vblank(struct drm_crtc *crtc)
 151 {
 152         struct drm_device *dev = crtc->dev;
 153         struct omap_drm_private *priv = dev->dev_private;
 154         unsigned long flags;
 155         enum omap_channel channel = omap_crtc_channel(crtc);
 156
 157         DBG("dev=%p, crtc=%u", dev, channel);
 158
 159         spin_lock_irqsave(&priv->wait_lock, flags);
 160         priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
 161                                                               channel);
 162         omap_irq_update(dev);
 163         spin_unlock_irqrestore(&priv->wait_lock, flags);
 164 }
 165
 166 static void omap_irq_fifo_underflow(struct omap_drm_private *priv,
 167                                     u32 irqstatus)
 168 {
 169         static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL,
 170                                       DEFAULT_RATELIMIT_BURST);
 171         static const struct {
 172                 const char *name;
 173                 u32 mask;
 174         } sources[] = {
 175                 { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW },
 176                 { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW },
 177                 { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW },
 178                 { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW },
 179         };
 180
 181         const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW
 182                        | DISPC_IRQ_VID1_FIFO_UNDERFLOW
 183                        | DISPC_IRQ_VID2_FIFO_UNDERFLOW
 184                        | DISPC_IRQ_VID3_FIFO_UNDERFLOW;
 185         unsigned int i;
 186
 187         spin_lock(&priv->wait_lock);
 188         irqstatus &= priv->irq_mask & mask;
 189         spin_unlock(&priv->wait_lock);
 190
 191         if (!irqstatus)
 192                 return;
 193
 194         if (!__ratelimit(&_rs))
 195                 return;
 196
 197         DRM_ERROR("FIFO underflow on ");
 198
 199         for (i = 0; i < ARRAY_SIZE(sources); ++i) {
 200                 if (sources[i].mask & irqstatus)
 201                         pr_cont("%s ", sources[i].name);
 202         }
 203
 204         pr_cont("(0x%08x)\n", irqstatus);
 205 }
 206
 207 static void omap_irq_ocp_error_handler(struct drm_device *dev,
 208         u32 irqstatus)
 209 {
 210         if (!(irqstatus & DISPC_IRQ_OCP_ERR))
 211                 return;
 212
 213         dev_err_ratelimited(dev->dev, "OCP error\n");
 214 }
 215
 216 static irqreturn_t omap_irq_handler(int irq, void *arg)
 217 {
 218         struct drm_device *dev = (struct drm_device *) arg;
 219         struct omap_drm_private *priv = dev->dev_private;
 220         struct omap_irq_wait *wait, *n;
 221         unsigned long flags;
 222         unsigned int id;
 223         u32 irqstatus;
 224
 225         irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc);
 226         priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus);
 227         priv->dispc_ops->read_irqstatus(priv->dispc);   /* flush posted write */
 228
 229         VERB("irqs: %08x", irqstatus);
 230
 231         for (id = 0; id < priv->num_pipes; id++) {
 232                 struct drm_crtc *crtc = priv->pipes[id].crtc;
 233                 enum omap_channel channel = omap_crtc_channel(crtc);
 234
 235                 if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) {
 236                         drm_handle_vblank(dev, id);
 237                         omap_crtc_vblank_irq(crtc);
 238                 }
 239
 240                 if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel))
 241                         omap_crtc_error_irq(crtc, irqstatus);
 242
 243                 if (irqstatus & priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel))
 244                         omap_crtc_framedone_irq(crtc, irqstatus);
 245         }
 246
 247         omap_irq_ocp_error_handler(dev, irqstatus);
 248         omap_irq_fifo_underflow(priv, irqstatus);
 249
 250         spin_lock_irqsave(&priv->wait_lock, flags);
 251         list_for_each_entry_safe(wait, n, &priv->wait_list, node) {
 252                 if (wait->irqmask & irqstatus)
 253                         omap_irq_wait_handler(wait);
 254         }
 255         spin_unlock_irqrestore(&priv->wait_lock, flags);
 256
 257         return IRQ_HANDLED;
 258 }
 259
 260 static const u32 omap_underflow_irqs[] = {
 261         [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW,
 262         [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW,
 263         [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW,
 264         [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW,
 265 };
 266
 267 /*
 268  * We need a special version, instead of just using drm_irq_install(),
 269  * because we need to register the irq via omapdss.  Once omapdss and
 270  * omapdrm are merged together we can assign the dispc hwmod data to
 271  * ourselves and drop these and just use drm_irq_{install,uninstall}()
 272  */
 273
 274 int omap_drm_irq_install(struct drm_device *dev)
 275 {
 276         struct omap_drm_private *priv = dev->dev_private;
 277         unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
 278         unsigned int max_planes;
 279         unsigned int i;
 280         int ret;
 281
 282         spin_lock_init(&priv->wait_lock);
 283         INIT_LIST_HEAD(&priv->wait_list);
 284
 285         priv->irq_mask = DISPC_IRQ_OCP_ERR;
 286
 287         max_planes = min(ARRAY_SIZE(priv->planes),
 288                          ARRAY_SIZE(omap_underflow_irqs));
 289         for (i = 0; i < max_planes; ++i) {
 290                 if (priv->planes[i])
 291                         priv->irq_mask |= omap_underflow_irqs[i];
 292         }
 293
 294         for (i = 0; i < num_mgrs; ++i)
 295                 priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, i);
 296
 297         priv->dispc_ops->runtime_get(priv->dispc);
 298         priv->dispc_ops->clear_irqstatus(priv->dispc, 0xffffffff);
 299         priv->dispc_ops->runtime_put(priv->dispc);
 300
 301         ret = priv->dispc_ops->request_irq(priv->dispc, omap_irq_handler, dev);
 302         if (ret < 0)
 303                 return ret;
 304
 305         dev->irq_enabled = true;
 306
 307         return 0;
 308 }
 309
 310 void omap_drm_irq_uninstall(struct drm_device *dev)
 311 {
 312         struct omap_drm_private *priv = dev->dev_private;
 313
 314         if (!dev->irq_enabled)
 315                 return;
 316
 317         dev->irq_enabled = false;
 318
 319         priv->dispc_ops->free_irq(priv->dispc, dev);
 320 }