2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
31 #include <video/display_timing.h>
32 #include <video/of_display_timing.h>
33 #include <video/videomode.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_device.h>
37 #include <drm/drm_mipi_dsi.h>
38 #include <drm/drm_panel.h>
41 * @modes: Pointer to array of fixed modes appropriate for this panel. If
42 * only one mode then this can just be the address of this the mode.
43 * NOTE: cannot be used with "timings" and also if this is specified
44 * then you cannot override the mode in the device tree.
45 * @num_modes: Number of elements in modes array.
46 * @timings: Pointer to array of display timings. NOTE: cannot be used with
47 * "modes" and also these will be used to validate a device tree
48 * override if one is present.
49 * @num_timings: Number of elements in timings array.
50 * @bpc: Bits per color.
51 * @size: Structure containing the physical size of this panel.
52 * @delay: Structure containing various delay values for this panel.
53 * @bus_format: See MEDIA_BUS_FMT_... defines.
54 * @bus_flags: See DRM_BUS_FLAG_... defines.
57 const struct drm_display_mode *modes;
58 unsigned int num_modes;
59 const struct display_timing *timings;
60 unsigned int num_timings;
65 * @width: width (in millimeters) of the panel's active display area
66 * @height: height (in millimeters) of the panel's active display area
74 * @prepare: the time (in milliseconds) that it takes for the panel to
75 * become ready and start receiving video data
76 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
77 * Plug Detect isn't used.
78 * @enable: the time (in milliseconds) that it takes for the panel to
79 * display the first valid frame after starting to receive
81 * @disable: the time (in milliseconds) that it takes for the panel to
82 * turn the display off (no content is visible)
83 * @unprepare: the time (in milliseconds) that it takes for the panel
84 * to power itself down completely
88 unsigned int hpd_absent_delay;
91 unsigned int unprepare;
100 struct drm_panel base;
105 const struct panel_desc *desc;
107 struct regulator *supply;
108 struct i2c_adapter *ddc;
110 struct gpio_desc *enable_gpio;
112 struct drm_display_mode override_mode;
115 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
117 return container_of(panel, struct panel_simple, base);
120 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
121 struct drm_connector *connector)
123 struct drm_display_mode *mode;
124 unsigned int i, num = 0;
126 for (i = 0; i < panel->desc->num_timings; i++) {
127 const struct display_timing *dt = &panel->desc->timings[i];
130 videomode_from_timing(dt, &vm);
131 mode = drm_mode_create(connector->dev);
133 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
134 dt->hactive.typ, dt->vactive.typ);
138 drm_display_mode_from_videomode(&vm, mode);
140 mode->type |= DRM_MODE_TYPE_DRIVER;
142 if (panel->desc->num_timings == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
145 drm_mode_probed_add(connector, mode);
152 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
153 struct drm_connector *connector)
155 struct drm_display_mode *mode;
156 unsigned int i, num = 0;
158 for (i = 0; i < panel->desc->num_modes; i++) {
159 const struct drm_display_mode *m = &panel->desc->modes[i];
161 mode = drm_mode_duplicate(connector->dev, m);
163 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
164 m->hdisplay, m->vdisplay, m->vrefresh);
168 mode->type |= DRM_MODE_TYPE_DRIVER;
170 if (panel->desc->num_modes == 1)
171 mode->type |= DRM_MODE_TYPE_PREFERRED;
173 drm_mode_set_name(mode);
175 drm_mode_probed_add(connector, mode);
182 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
183 struct drm_connector *connector)
185 struct drm_display_mode *mode;
186 bool has_override = panel->override_mode.type;
187 unsigned int num = 0;
193 mode = drm_mode_duplicate(connector->dev,
194 &panel->override_mode);
196 drm_mode_probed_add(connector, mode);
199 dev_err(panel->base.dev, "failed to add override mode\n");
203 /* Only add timings if override was not there or failed to validate */
204 if (num == 0 && panel->desc->num_timings)
205 num = panel_simple_get_timings_modes(panel, connector);
208 * Only add fixed modes if timings/override added no mode.
210 * We should only ever have either the display timings specified
211 * or a fixed mode. Anything else is rather bogus.
213 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
215 num = panel_simple_get_display_modes(panel, connector);
217 connector->display_info.bpc = panel->desc->bpc;
218 connector->display_info.width_mm = panel->desc->size.width;
219 connector->display_info.height_mm = panel->desc->size.height;
220 if (panel->desc->bus_format)
221 drm_display_info_set_bus_formats(&connector->display_info,
222 &panel->desc->bus_format, 1);
223 connector->display_info.bus_flags = panel->desc->bus_flags;
228 static int panel_simple_disable(struct drm_panel *panel)
230 struct panel_simple *p = to_panel_simple(panel);
235 if (p->desc->delay.disable)
236 msleep(p->desc->delay.disable);
243 static int panel_simple_unprepare(struct drm_panel *panel)
245 struct panel_simple *p = to_panel_simple(panel);
250 gpiod_set_value_cansleep(p->enable_gpio, 0);
252 regulator_disable(p->supply);
254 if (p->desc->delay.unprepare)
255 msleep(p->desc->delay.unprepare);
262 static int panel_simple_prepare(struct drm_panel *panel)
264 struct panel_simple *p = to_panel_simple(panel);
271 err = regulator_enable(p->supply);
273 dev_err(panel->dev, "failed to enable supply: %d\n", err);
277 gpiod_set_value_cansleep(p->enable_gpio, 1);
279 delay = p->desc->delay.prepare;
281 delay += p->desc->delay.hpd_absent_delay;
290 static int panel_simple_enable(struct drm_panel *panel)
292 struct panel_simple *p = to_panel_simple(panel);
297 if (p->desc->delay.enable)
298 msleep(p->desc->delay.enable);
305 static int panel_simple_get_modes(struct drm_panel *panel,
306 struct drm_connector *connector)
308 struct panel_simple *p = to_panel_simple(panel);
311 /* probe EDID if a DDC bus is available */
313 struct edid *edid = drm_get_edid(connector, p->ddc);
315 drm_connector_update_edid_property(connector, edid);
317 num += drm_add_edid_modes(connector, edid);
322 /* add hard-coded panel modes */
323 num += panel_simple_get_non_edid_modes(p, connector);
328 static int panel_simple_get_timings(struct drm_panel *panel,
329 unsigned int num_timings,
330 struct display_timing *timings)
332 struct panel_simple *p = to_panel_simple(panel);
335 if (p->desc->num_timings < num_timings)
336 num_timings = p->desc->num_timings;
339 for (i = 0; i < num_timings; i++)
340 timings[i] = p->desc->timings[i];
342 return p->desc->num_timings;
345 static const struct drm_panel_funcs panel_simple_funcs = {
346 .disable = panel_simple_disable,
347 .unprepare = panel_simple_unprepare,
348 .prepare = panel_simple_prepare,
349 .enable = panel_simple_enable,
350 .get_modes = panel_simple_get_modes,
351 .get_timings = panel_simple_get_timings,
354 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
355 (to_check->field.typ >= bounds->field.min && \
356 to_check->field.typ <= bounds->field.max)
357 static void panel_simple_parse_panel_timing_node(struct device *dev,
358 struct panel_simple *panel,
359 const struct display_timing *ot)
361 const struct panel_desc *desc = panel->desc;
365 if (WARN_ON(desc->num_modes)) {
366 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
369 if (WARN_ON(!desc->num_timings)) {
370 dev_err(dev, "Reject override mode: no timings specified\n");
374 for (i = 0; i < panel->desc->num_timings; i++) {
375 const struct display_timing *dt = &panel->desc->timings[i];
377 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
378 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
379 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
380 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
381 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
382 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
383 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
384 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
387 if (ot->flags != dt->flags)
390 videomode_from_timing(ot, &vm);
391 drm_display_mode_from_videomode(&vm, &panel->override_mode);
392 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
393 DRM_MODE_TYPE_PREFERRED;
397 if (WARN_ON(!panel->override_mode.type))
398 dev_err(dev, "Reject override mode: No display_timing found\n");
401 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
403 struct panel_simple *panel;
404 struct display_timing dt;
405 struct device_node *ddc;
408 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
412 panel->enabled = false;
413 panel->prepared = false;
416 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
418 panel->supply = devm_regulator_get(dev, "power");
419 if (IS_ERR(panel->supply))
420 return PTR_ERR(panel->supply);
422 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
424 if (IS_ERR(panel->enable_gpio)) {
425 err = PTR_ERR(panel->enable_gpio);
426 if (err != -EPROBE_DEFER)
427 dev_err(dev, "failed to request GPIO: %d\n", err);
431 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
433 panel->ddc = of_find_i2c_adapter_by_node(ddc);
437 return -EPROBE_DEFER;
440 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
441 panel_simple_parse_panel_timing_node(dev, panel, &dt);
443 drm_panel_init(&panel->base, dev, &panel_simple_funcs,
444 desc->connector_type);
446 err = drm_panel_of_backlight(&panel->base);
450 err = drm_panel_add(&panel->base);
454 dev_set_drvdata(dev, panel);
460 put_device(&panel->ddc->dev);
465 static int panel_simple_remove(struct device *dev)
467 struct panel_simple *panel = dev_get_drvdata(dev);
469 drm_panel_remove(&panel->base);
470 drm_panel_disable(&panel->base);
471 drm_panel_unprepare(&panel->base);
474 put_device(&panel->ddc->dev);
479 static void panel_simple_shutdown(struct device *dev)
481 struct panel_simple *panel = dev_get_drvdata(dev);
483 drm_panel_disable(&panel->base);
484 drm_panel_unprepare(&panel->base);
487 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
490 .hsync_start = 480 + 2,
491 .hsync_end = 480 + 2 + 41,
492 .htotal = 480 + 2 + 41 + 2,
494 .vsync_start = 272 + 2,
495 .vsync_end = 272 + 2 + 10,
496 .vtotal = 272 + 2 + 10 + 2,
498 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
501 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
502 .modes = &ire_am_480272h3tmqw_t01h_mode,
509 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
512 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
515 .hsync_start = 800 + 0,
516 .hsync_end = 800 + 0 + 255,
517 .htotal = 800 + 0 + 255 + 0,
519 .vsync_start = 480 + 2,
520 .vsync_end = 480 + 2 + 45,
521 .vtotal = 480 + 2 + 45 + 0,
523 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
526 static const struct panel_desc ampire_am800480r3tmqwa1h = {
527 .modes = &ire_am800480r3tmqwa1h_mode,
534 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
537 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
538 .pixelclock = { 26400000, 33300000, 46800000 },
539 .hactive = { 800, 800, 800 },
540 .hfront_porch = { 16, 210, 354 },
541 .hback_porch = { 45, 36, 6 },
542 .hsync_len = { 1, 10, 40 },
543 .vactive = { 480, 480, 480 },
544 .vfront_porch = { 7, 22, 147 },
545 .vback_porch = { 22, 13, 3 },
546 .vsync_len = { 1, 10, 20 },
547 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
548 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
551 static const struct panel_desc armadeus_st0700_adapt = {
552 .timings = &santek_st0700i5y_rbslw_f_timing,
559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
560 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
563 static const struct drm_display_mode auo_b101aw03_mode = {
566 .hsync_start = 1024 + 156,
567 .hsync_end = 1024 + 156 + 8,
568 .htotal = 1024 + 156 + 8 + 156,
570 .vsync_start = 600 + 16,
571 .vsync_end = 600 + 16 + 6,
572 .vtotal = 600 + 16 + 6 + 16,
576 static const struct panel_desc auo_b101aw03 = {
577 .modes = &auo_b101aw03_mode,
586 static const struct display_timing auo_b101ean01_timing = {
587 .pixelclock = { 65300000, 72500000, 75000000 },
588 .hactive = { 1280, 1280, 1280 },
589 .hfront_porch = { 18, 119, 119 },
590 .hback_porch = { 21, 21, 21 },
591 .hsync_len = { 32, 32, 32 },
592 .vactive = { 800, 800, 800 },
593 .vfront_porch = { 4, 4, 4 },
594 .vback_porch = { 8, 8, 8 },
595 .vsync_len = { 18, 20, 20 },
598 static const struct panel_desc auo_b101ean01 = {
599 .timings = &auo_b101ean01_timing,
608 static const struct drm_display_mode auo_b101xtn01_mode = {
611 .hsync_start = 1366 + 20,
612 .hsync_end = 1366 + 20 + 70,
613 .htotal = 1366 + 20 + 70,
615 .vsync_start = 768 + 14,
616 .vsync_end = 768 + 14 + 42,
617 .vtotal = 768 + 14 + 42,
619 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
622 static const struct panel_desc auo_b101xtn01 = {
623 .modes = &auo_b101xtn01_mode,
632 static const struct drm_display_mode auo_b116xak01_mode = {
635 .hsync_start = 1366 + 48,
636 .hsync_end = 1366 + 48 + 32,
637 .htotal = 1366 + 48 + 32 + 10,
639 .vsync_start = 768 + 4,
640 .vsync_end = 768 + 4 + 6,
641 .vtotal = 768 + 4 + 6 + 15,
643 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
646 static const struct panel_desc auo_b116xak01 = {
647 .modes = &auo_b116xak01_mode,
655 .hpd_absent_delay = 200,
657 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
658 .connector_type = DRM_MODE_CONNECTOR_eDP,
661 static const struct drm_display_mode auo_b116xw03_mode = {
664 .hsync_start = 1366 + 40,
665 .hsync_end = 1366 + 40 + 40,
666 .htotal = 1366 + 40 + 40 + 32,
668 .vsync_start = 768 + 10,
669 .vsync_end = 768 + 10 + 12,
670 .vtotal = 768 + 10 + 12 + 6,
674 static const struct panel_desc auo_b116xw03 = {
675 .modes = &auo_b116xw03_mode,
684 static const struct drm_display_mode auo_b133xtn01_mode = {
687 .hsync_start = 1366 + 48,
688 .hsync_end = 1366 + 48 + 32,
689 .htotal = 1366 + 48 + 32 + 20,
691 .vsync_start = 768 + 3,
692 .vsync_end = 768 + 3 + 6,
693 .vtotal = 768 + 3 + 6 + 13,
697 static const struct panel_desc auo_b133xtn01 = {
698 .modes = &auo_b133xtn01_mode,
707 static const struct drm_display_mode auo_b133htn01_mode = {
710 .hsync_start = 1920 + 172,
711 .hsync_end = 1920 + 172 + 80,
712 .htotal = 1920 + 172 + 80 + 60,
714 .vsync_start = 1080 + 25,
715 .vsync_end = 1080 + 25 + 10,
716 .vtotal = 1080 + 25 + 10 + 10,
720 static const struct panel_desc auo_b133htn01 = {
721 .modes = &auo_b133htn01_mode,
735 static const struct display_timing auo_g070vvn01_timings = {
736 .pixelclock = { 33300000, 34209000, 45000000 },
737 .hactive = { 800, 800, 800 },
738 .hfront_porch = { 20, 40, 200 },
739 .hback_porch = { 87, 40, 1 },
740 .hsync_len = { 1, 48, 87 },
741 .vactive = { 480, 480, 480 },
742 .vfront_porch = { 5, 13, 200 },
743 .vback_porch = { 31, 31, 29 },
744 .vsync_len = { 1, 1, 3 },
747 static const struct panel_desc auo_g070vvn01 = {
748 .timings = &auo_g070vvn01_timings,
763 static const struct drm_display_mode auo_g101evn010_mode = {
766 .hsync_start = 1280 + 82,
767 .hsync_end = 1280 + 82 + 2,
768 .htotal = 1280 + 82 + 2 + 84,
770 .vsync_start = 800 + 8,
771 .vsync_end = 800 + 8 + 2,
772 .vtotal = 800 + 8 + 2 + 6,
776 static const struct panel_desc auo_g101evn010 = {
777 .modes = &auo_g101evn010_mode,
784 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
787 static const struct drm_display_mode auo_g104sn02_mode = {
790 .hsync_start = 800 + 40,
791 .hsync_end = 800 + 40 + 216,
792 .htotal = 800 + 40 + 216 + 128,
794 .vsync_start = 600 + 10,
795 .vsync_end = 600 + 10 + 35,
796 .vtotal = 600 + 10 + 35 + 2,
800 static const struct panel_desc auo_g104sn02 = {
801 .modes = &auo_g104sn02_mode,
810 static const struct display_timing auo_g133han01_timings = {
811 .pixelclock = { 134000000, 141200000, 149000000 },
812 .hactive = { 1920, 1920, 1920 },
813 .hfront_porch = { 39, 58, 77 },
814 .hback_porch = { 59, 88, 117 },
815 .hsync_len = { 28, 42, 56 },
816 .vactive = { 1080, 1080, 1080 },
817 .vfront_porch = { 3, 8, 11 },
818 .vback_porch = { 5, 14, 19 },
819 .vsync_len = { 4, 14, 19 },
822 static const struct panel_desc auo_g133han01 = {
823 .timings = &auo_g133han01_timings,
836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
837 .connector_type = DRM_MODE_CONNECTOR_LVDS,
840 static const struct display_timing auo_g185han01_timings = {
841 .pixelclock = { 120000000, 144000000, 175000000 },
842 .hactive = { 1920, 1920, 1920 },
843 .hfront_porch = { 36, 120, 148 },
844 .hback_porch = { 24, 88, 108 },
845 .hsync_len = { 20, 48, 64 },
846 .vactive = { 1080, 1080, 1080 },
847 .vfront_porch = { 6, 10, 40 },
848 .vback_porch = { 2, 5, 20 },
849 .vsync_len = { 2, 5, 20 },
852 static const struct panel_desc auo_g185han01 = {
853 .timings = &auo_g185han01_timings,
866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
867 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870 static const struct display_timing auo_p320hvn03_timings = {
871 .pixelclock = { 106000000, 148500000, 164000000 },
872 .hactive = { 1920, 1920, 1920 },
873 .hfront_porch = { 25, 50, 130 },
874 .hback_porch = { 25, 50, 130 },
875 .hsync_len = { 20, 40, 105 },
876 .vactive = { 1080, 1080, 1080 },
877 .vfront_porch = { 8, 17, 150 },
878 .vback_porch = { 8, 17, 150 },
879 .vsync_len = { 4, 11, 100 },
882 static const struct panel_desc auo_p320hvn03 = {
883 .timings = &auo_p320hvn03_timings,
895 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
896 .connector_type = DRM_MODE_CONNECTOR_LVDS,
899 static const struct drm_display_mode auo_t215hvn01_mode = {
902 .hsync_start = 1920 + 88,
903 .hsync_end = 1920 + 88 + 44,
904 .htotal = 1920 + 88 + 44 + 148,
906 .vsync_start = 1080 + 4,
907 .vsync_end = 1080 + 4 + 5,
908 .vtotal = 1080 + 4 + 5 + 36,
912 static const struct panel_desc auo_t215hvn01 = {
913 .modes = &auo_t215hvn01_mode,
926 static const struct drm_display_mode avic_tm070ddh03_mode = {
929 .hsync_start = 1024 + 160,
930 .hsync_end = 1024 + 160 + 4,
931 .htotal = 1024 + 160 + 4 + 156,
933 .vsync_start = 600 + 17,
934 .vsync_end = 600 + 17 + 1,
935 .vtotal = 600 + 17 + 1 + 17,
939 static const struct panel_desc avic_tm070ddh03 = {
940 .modes = &avic_tm070ddh03_mode,
954 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
957 .hsync_start = 800 + 40,
958 .hsync_end = 800 + 40 + 48,
959 .htotal = 800 + 40 + 48 + 40,
961 .vsync_start = 480 + 13,
962 .vsync_end = 480 + 13 + 3,
963 .vtotal = 480 + 13 + 3 + 29,
966 static const struct panel_desc bananapi_s070wv20_ct16 = {
967 .modes = &bananapi_s070wv20_ct16_mode,
976 static const struct drm_display_mode boe_hv070wsa_mode = {
979 .hsync_start = 1024 + 30,
980 .hsync_end = 1024 + 30 + 30,
981 .htotal = 1024 + 30 + 30 + 30,
983 .vsync_start = 600 + 10,
984 .vsync_end = 600 + 10 + 10,
985 .vtotal = 600 + 10 + 10 + 10,
989 static const struct panel_desc boe_hv070wsa = {
990 .modes = &boe_hv070wsa_mode,
998 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1002 .hsync_start = 1280 + 48,
1003 .hsync_end = 1280 + 48 + 32,
1004 .htotal = 1280 + 48 + 32 + 80,
1006 .vsync_start = 800 + 3,
1007 .vsync_end = 800 + 3 + 5,
1008 .vtotal = 800 + 3 + 5 + 24,
1014 .hsync_start = 1280 + 48,
1015 .hsync_end = 1280 + 48 + 32,
1016 .htotal = 1280 + 48 + 32 + 80,
1018 .vsync_start = 800 + 3,
1019 .vsync_end = 800 + 3 + 5,
1020 .vtotal = 800 + 3 + 5 + 24,
1025 static const struct panel_desc boe_nv101wxmn51 = {
1026 .modes = boe_nv101wxmn51_modes,
1027 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1040 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1043 .hsync_start = 480 + 5,
1044 .hsync_end = 480 + 5 + 5,
1045 .htotal = 480 + 5 + 5 + 40,
1047 .vsync_start = 272 + 8,
1048 .vsync_end = 272 + 8 + 8,
1049 .vtotal = 272 + 8 + 8 + 8,
1051 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1054 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1055 .modes = &cdtech_s043wq26h_ct7_mode,
1062 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1065 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1068 .hsync_start = 800 + 40,
1069 .hsync_end = 800 + 40 + 40,
1070 .htotal = 800 + 40 + 40 + 48,
1072 .vsync_start = 480 + 29,
1073 .vsync_end = 480 + 29 + 13,
1074 .vtotal = 480 + 29 + 13 + 3,
1076 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1079 static const struct panel_desc cdtech_s070wv95_ct16 = {
1080 .modes = &cdtech_s070wv95_ct16_mode,
1089 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1092 .hsync_start = 800 + 49,
1093 .hsync_end = 800 + 49 + 33,
1094 .htotal = 800 + 49 + 33 + 17,
1096 .vsync_start = 1280 + 1,
1097 .vsync_end = 1280 + 1 + 7,
1098 .vtotal = 1280 + 1 + 7 + 15,
1100 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1103 static const struct panel_desc chunghwa_claa070wp03xg = {
1104 .modes = &chunghwa_claa070wp03xg_mode,
1113 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1116 .hsync_start = 1366 + 58,
1117 .hsync_end = 1366 + 58 + 58,
1118 .htotal = 1366 + 58 + 58 + 58,
1120 .vsync_start = 768 + 4,
1121 .vsync_end = 768 + 4 + 4,
1122 .vtotal = 768 + 4 + 4 + 4,
1126 static const struct panel_desc chunghwa_claa101wa01a = {
1127 .modes = &chunghwa_claa101wa01a_mode,
1136 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1139 .hsync_start = 1366 + 48,
1140 .hsync_end = 1366 + 48 + 32,
1141 .htotal = 1366 + 48 + 32 + 20,
1143 .vsync_start = 768 + 16,
1144 .vsync_end = 768 + 16 + 8,
1145 .vtotal = 768 + 16 + 8 + 16,
1149 static const struct panel_desc chunghwa_claa101wb01 = {
1150 .modes = &chunghwa_claa101wb01_mode,
1159 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1162 .hsync_start = 800 + 40,
1163 .hsync_end = 800 + 40 + 128,
1164 .htotal = 800 + 40 + 128 + 88,
1166 .vsync_start = 480 + 10,
1167 .vsync_end = 480 + 10 + 2,
1168 .vtotal = 480 + 10 + 2 + 33,
1170 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1173 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1174 .modes = &dataimage_scf0700c48ggu18_mode,
1181 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1182 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1185 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1186 .pixelclock = { 45000000, 51200000, 57000000 },
1187 .hactive = { 1024, 1024, 1024 },
1188 .hfront_porch = { 100, 106, 113 },
1189 .hback_porch = { 100, 106, 113 },
1190 .hsync_len = { 100, 108, 114 },
1191 .vactive = { 600, 600, 600 },
1192 .vfront_porch = { 8, 11, 15 },
1193 .vback_porch = { 8, 11, 15 },
1194 .vsync_len = { 9, 13, 15 },
1195 .flags = DISPLAY_FLAGS_DE_HIGH,
1198 static const struct panel_desc dlc_dlc0700yzg_1 = {
1199 .timings = &dlc_dlc0700yzg_1_timing,
1211 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1212 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1215 static const struct display_timing dlc_dlc1010gig_timing = {
1216 .pixelclock = { 68900000, 71100000, 73400000 },
1217 .hactive = { 1280, 1280, 1280 },
1218 .hfront_porch = { 43, 53, 63 },
1219 .hback_porch = { 43, 53, 63 },
1220 .hsync_len = { 44, 54, 64 },
1221 .vactive = { 800, 800, 800 },
1222 .vfront_porch = { 5, 8, 11 },
1223 .vback_porch = { 5, 8, 11 },
1224 .vsync_len = { 5, 7, 11 },
1225 .flags = DISPLAY_FLAGS_DE_HIGH,
1228 static const struct panel_desc dlc_dlc1010gig = {
1229 .timings = &dlc_dlc1010gig_timing,
1242 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1243 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1246 static const struct drm_display_mode edt_et035012dm6_mode = {
1249 .hsync_start = 320 + 20,
1250 .hsync_end = 320 + 20 + 30,
1251 .htotal = 320 + 20 + 68,
1253 .vsync_start = 240 + 4,
1254 .vsync_end = 240 + 4 + 4,
1255 .vtotal = 240 + 4 + 4 + 14,
1257 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1260 static const struct panel_desc edt_et035012dm6 = {
1261 .modes = &edt_et035012dm6_mode,
1268 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1269 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1272 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1275 .hsync_start = 480 + 2,
1276 .hsync_end = 480 + 2 + 41,
1277 .htotal = 480 + 2 + 41 + 2,
1279 .vsync_start = 272 + 2,
1280 .vsync_end = 272 + 2 + 10,
1281 .vtotal = 272 + 2 + 10 + 2,
1283 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1286 static const struct panel_desc edt_etm0430g0dh6 = {
1287 .modes = &edt_etm0430g0dh6_mode,
1296 static const struct drm_display_mode edt_et057090dhu_mode = {
1299 .hsync_start = 640 + 16,
1300 .hsync_end = 640 + 16 + 30,
1301 .htotal = 640 + 16 + 30 + 114,
1303 .vsync_start = 480 + 10,
1304 .vsync_end = 480 + 10 + 3,
1305 .vtotal = 480 + 10 + 3 + 32,
1307 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1310 static const struct panel_desc edt_et057090dhu = {
1311 .modes = &edt_et057090dhu_mode,
1318 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1319 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1322 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1325 .hsync_start = 800 + 40,
1326 .hsync_end = 800 + 40 + 128,
1327 .htotal = 800 + 40 + 128 + 88,
1329 .vsync_start = 480 + 10,
1330 .vsync_end = 480 + 10 + 2,
1331 .vtotal = 480 + 10 + 2 + 33,
1333 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1336 static const struct panel_desc edt_etm0700g0dh6 = {
1337 .modes = &edt_etm0700g0dh6_mode,
1344 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1345 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1348 static const struct panel_desc edt_etm0700g0bdh6 = {
1349 .modes = &edt_etm0700g0dh6_mode,
1356 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1357 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1360 static const struct display_timing evervision_vgg804821_timing = {
1361 .pixelclock = { 27600000, 33300000, 50000000 },
1362 .hactive = { 800, 800, 800 },
1363 .hfront_porch = { 40, 66, 70 },
1364 .hback_porch = { 40, 67, 70 },
1365 .hsync_len = { 40, 67, 70 },
1366 .vactive = { 480, 480, 480 },
1367 .vfront_porch = { 6, 10, 10 },
1368 .vback_porch = { 7, 11, 11 },
1369 .vsync_len = { 7, 11, 11 },
1370 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1371 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1372 DISPLAY_FLAGS_SYNC_NEGEDGE,
1375 static const struct panel_desc evervision_vgg804821 = {
1376 .timings = &evervision_vgg804821_timing,
1383 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1384 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1387 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1390 .hsync_start = 800 + 168,
1391 .hsync_end = 800 + 168 + 64,
1392 .htotal = 800 + 168 + 64 + 88,
1394 .vsync_start = 480 + 37,
1395 .vsync_end = 480 + 37 + 2,
1396 .vtotal = 480 + 37 + 2 + 8,
1400 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1401 .modes = &foxlink_fl500wvr00_a0t_mode,
1408 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1411 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1414 .hsync_start = 800 + 20,
1415 .hsync_end = 800 + 20 + 24,
1416 .htotal = 800 + 20 + 24 + 20,
1418 .vsync_start = 1280 + 4,
1419 .vsync_end = 1280 + 4 + 8,
1420 .vtotal = 1280 + 4 + 8 + 4,
1422 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1425 static const struct panel_desc friendlyarm_hd702e = {
1426 .modes = &friendlyarm_hd702e_mode,
1434 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1437 .hsync_start = 480 + 5,
1438 .hsync_end = 480 + 5 + 1,
1439 .htotal = 480 + 5 + 1 + 40,
1441 .vsync_start = 272 + 8,
1442 .vsync_end = 272 + 8 + 1,
1443 .vtotal = 272 + 8 + 1 + 8,
1447 static const struct panel_desc giantplus_gpg482739qs5 = {
1448 .modes = &giantplus_gpg482739qs5_mode,
1455 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1458 static const struct display_timing giantplus_gpm940b0_timing = {
1459 .pixelclock = { 13500000, 27000000, 27500000 },
1460 .hactive = { 320, 320, 320 },
1461 .hfront_porch = { 14, 686, 718 },
1462 .hback_porch = { 50, 70, 255 },
1463 .hsync_len = { 1, 1, 1 },
1464 .vactive = { 240, 240, 240 },
1465 .vfront_porch = { 1, 1, 179 },
1466 .vback_porch = { 1, 21, 31 },
1467 .vsync_len = { 1, 1, 6 },
1468 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1471 static const struct panel_desc giantplus_gpm940b0 = {
1472 .timings = &giantplus_gpm940b0_timing,
1479 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1480 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1483 static const struct display_timing hannstar_hsd070pww1_timing = {
1484 .pixelclock = { 64300000, 71100000, 82000000 },
1485 .hactive = { 1280, 1280, 1280 },
1486 .hfront_porch = { 1, 1, 10 },
1487 .hback_porch = { 1, 1, 10 },
1489 * According to the data sheet, the minimum horizontal blanking interval
1490 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1491 * minimum working horizontal blanking interval to be 60 clocks.
1493 .hsync_len = { 58, 158, 661 },
1494 .vactive = { 800, 800, 800 },
1495 .vfront_porch = { 1, 1, 10 },
1496 .vback_porch = { 1, 1, 10 },
1497 .vsync_len = { 1, 21, 203 },
1498 .flags = DISPLAY_FLAGS_DE_HIGH,
1501 static const struct panel_desc hannstar_hsd070pww1 = {
1502 .timings = &hannstar_hsd070pww1_timing,
1509 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1510 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1513 static const struct display_timing hannstar_hsd100pxn1_timing = {
1514 .pixelclock = { 55000000, 65000000, 75000000 },
1515 .hactive = { 1024, 1024, 1024 },
1516 .hfront_porch = { 40, 40, 40 },
1517 .hback_porch = { 220, 220, 220 },
1518 .hsync_len = { 20, 60, 100 },
1519 .vactive = { 768, 768, 768 },
1520 .vfront_porch = { 7, 7, 7 },
1521 .vback_porch = { 21, 21, 21 },
1522 .vsync_len = { 10, 10, 10 },
1523 .flags = DISPLAY_FLAGS_DE_HIGH,
1526 static const struct panel_desc hannstar_hsd100pxn1 = {
1527 .timings = &hannstar_hsd100pxn1_timing,
1534 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1535 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1538 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1541 .hsync_start = 800 + 85,
1542 .hsync_end = 800 + 85 + 86,
1543 .htotal = 800 + 85 + 86 + 85,
1545 .vsync_start = 480 + 16,
1546 .vsync_end = 480 + 16 + 13,
1547 .vtotal = 480 + 16 + 13 + 16,
1551 static const struct panel_desc hitachi_tx23d38vm0caa = {
1552 .modes = &hitachi_tx23d38vm0caa_mode,
1565 static const struct drm_display_mode innolux_at043tn24_mode = {
1568 .hsync_start = 480 + 2,
1569 .hsync_end = 480 + 2 + 41,
1570 .htotal = 480 + 2 + 41 + 2,
1572 .vsync_start = 272 + 2,
1573 .vsync_end = 272 + 2 + 10,
1574 .vtotal = 272 + 2 + 10 + 2,
1576 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1579 static const struct panel_desc innolux_at043tn24 = {
1580 .modes = &innolux_at043tn24_mode,
1587 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1588 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1591 static const struct drm_display_mode innolux_at070tn92_mode = {
1594 .hsync_start = 800 + 210,
1595 .hsync_end = 800 + 210 + 20,
1596 .htotal = 800 + 210 + 20 + 46,
1598 .vsync_start = 480 + 22,
1599 .vsync_end = 480 + 22 + 10,
1600 .vtotal = 480 + 22 + 23 + 10,
1604 static const struct panel_desc innolux_at070tn92 = {
1605 .modes = &innolux_at070tn92_mode,
1611 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1614 static const struct display_timing innolux_g070y2_l01_timing = {
1615 .pixelclock = { 28000000, 29500000, 32000000 },
1616 .hactive = { 800, 800, 800 },
1617 .hfront_porch = { 61, 91, 141 },
1618 .hback_porch = { 60, 90, 140 },
1619 .hsync_len = { 12, 12, 12 },
1620 .vactive = { 480, 480, 480 },
1621 .vfront_porch = { 4, 9, 30 },
1622 .vback_porch = { 4, 8, 28 },
1623 .vsync_len = { 2, 2, 2 },
1624 .flags = DISPLAY_FLAGS_DE_HIGH,
1627 static const struct panel_desc innolux_g070y2_l01 = {
1628 .timings = &innolux_g070y2_l01_timing,
1641 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1642 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1645 static const struct display_timing innolux_g101ice_l01_timing = {
1646 .pixelclock = { 60400000, 71100000, 74700000 },
1647 .hactive = { 1280, 1280, 1280 },
1648 .hfront_porch = { 41, 80, 100 },
1649 .hback_porch = { 40, 79, 99 },
1650 .hsync_len = { 1, 1, 1 },
1651 .vactive = { 800, 800, 800 },
1652 .vfront_porch = { 5, 11, 14 },
1653 .vback_porch = { 4, 11, 14 },
1654 .vsync_len = { 1, 1, 1 },
1655 .flags = DISPLAY_FLAGS_DE_HIGH,
1658 static const struct panel_desc innolux_g101ice_l01 = {
1659 .timings = &innolux_g101ice_l01_timing,
1670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1671 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1674 static const struct display_timing innolux_g121i1_l01_timing = {
1675 .pixelclock = { 67450000, 71000000, 74550000 },
1676 .hactive = { 1280, 1280, 1280 },
1677 .hfront_porch = { 40, 80, 160 },
1678 .hback_porch = { 39, 79, 159 },
1679 .hsync_len = { 1, 1, 1 },
1680 .vactive = { 800, 800, 800 },
1681 .vfront_porch = { 5, 11, 100 },
1682 .vback_porch = { 4, 11, 99 },
1683 .vsync_len = { 1, 1, 1 },
1686 static const struct panel_desc innolux_g121i1_l01 = {
1687 .timings = &innolux_g121i1_l01_timing,
1698 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1699 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1702 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1705 .hsync_start = 1024 + 0,
1706 .hsync_end = 1024 + 1,
1707 .htotal = 1024 + 0 + 1 + 320,
1709 .vsync_start = 768 + 38,
1710 .vsync_end = 768 + 38 + 1,
1711 .vtotal = 768 + 38 + 1 + 0,
1713 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1716 static const struct panel_desc innolux_g121x1_l03 = {
1717 .modes = &innolux_g121x1_l03_mode,
1732 * Datasheet specifies that at 60 Hz refresh rate:
1733 * - total horizontal time: { 1506, 1592, 1716 }
1734 * - total vertical time: { 788, 800, 868 }
1736 * ...but doesn't go into exactly how that should be split into a front
1737 * porch, back porch, or sync length. For now we'll leave a single setting
1738 * here which allows a bit of tweaking of the pixel clock at the expense of
1741 static const struct display_timing innolux_n116bge_timing = {
1742 .pixelclock = { 72600000, 76420000, 80240000 },
1743 .hactive = { 1366, 1366, 1366 },
1744 .hfront_porch = { 136, 136, 136 },
1745 .hback_porch = { 60, 60, 60 },
1746 .hsync_len = { 30, 30, 30 },
1747 .vactive = { 768, 768, 768 },
1748 .vfront_porch = { 8, 8, 8 },
1749 .vback_porch = { 12, 12, 12 },
1750 .vsync_len = { 12, 12, 12 },
1751 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
1754 static const struct panel_desc innolux_n116bge = {
1755 .timings = &innolux_n116bge_timing,
1764 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1767 .hsync_start = 1366 + 16,
1768 .hsync_end = 1366 + 16 + 34,
1769 .htotal = 1366 + 16 + 34 + 50,
1771 .vsync_start = 768 + 2,
1772 .vsync_end = 768 + 2 + 6,
1773 .vtotal = 768 + 2 + 6 + 12,
1777 static const struct panel_desc innolux_n156bge_l21 = {
1778 .modes = &innolux_n156bge_l21_mode,
1787 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1790 .hsync_start = 2160 + 48,
1791 .hsync_end = 2160 + 48 + 32,
1792 .htotal = 2160 + 48 + 32 + 80,
1794 .vsync_start = 1440 + 3,
1795 .vsync_end = 1440 + 3 + 10,
1796 .vtotal = 1440 + 3 + 10 + 27,
1798 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1801 static const struct panel_desc innolux_p120zdg_bf1 = {
1802 .modes = &innolux_p120zdg_bf1_mode,
1810 .hpd_absent_delay = 200,
1815 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1818 .hsync_start = 1024 + 128,
1819 .hsync_end = 1024 + 128 + 64,
1820 .htotal = 1024 + 128 + 64 + 128,
1822 .vsync_start = 600 + 16,
1823 .vsync_end = 600 + 16 + 4,
1824 .vtotal = 600 + 16 + 4 + 16,
1828 static const struct panel_desc innolux_zj070na_01p = {
1829 .modes = &innolux_zj070na_01p_mode,
1838 static const struct display_timing koe_tx14d24vm1bpa_timing = {
1839 .pixelclock = { 5580000, 5850000, 6200000 },
1840 .hactive = { 320, 320, 320 },
1841 .hfront_porch = { 30, 30, 30 },
1842 .hback_porch = { 30, 30, 30 },
1843 .hsync_len = { 1, 5, 17 },
1844 .vactive = { 240, 240, 240 },
1845 .vfront_porch = { 6, 6, 6 },
1846 .vback_porch = { 5, 5, 5 },
1847 .vsync_len = { 1, 2, 11 },
1848 .flags = DISPLAY_FLAGS_DE_HIGH,
1851 static const struct panel_desc koe_tx14d24vm1bpa = {
1852 .timings = &koe_tx14d24vm1bpa_timing,
1861 static const struct display_timing koe_tx31d200vm0baa_timing = {
1862 .pixelclock = { 39600000, 43200000, 48000000 },
1863 .hactive = { 1280, 1280, 1280 },
1864 .hfront_porch = { 16, 36, 56 },
1865 .hback_porch = { 16, 36, 56 },
1866 .hsync_len = { 8, 8, 8 },
1867 .vactive = { 480, 480, 480 },
1868 .vfront_porch = { 6, 21, 33 },
1869 .vback_porch = { 6, 21, 33 },
1870 .vsync_len = { 8, 8, 8 },
1871 .flags = DISPLAY_FLAGS_DE_HIGH,
1874 static const struct panel_desc koe_tx31d200vm0baa = {
1875 .timings = &koe_tx31d200vm0baa_timing,
1882 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1883 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1886 static const struct display_timing kyo_tcg121xglp_timing = {
1887 .pixelclock = { 52000000, 65000000, 71000000 },
1888 .hactive = { 1024, 1024, 1024 },
1889 .hfront_porch = { 2, 2, 2 },
1890 .hback_porch = { 2, 2, 2 },
1891 .hsync_len = { 86, 124, 244 },
1892 .vactive = { 768, 768, 768 },
1893 .vfront_porch = { 2, 2, 2 },
1894 .vback_porch = { 2, 2, 2 },
1895 .vsync_len = { 6, 34, 73 },
1896 .flags = DISPLAY_FLAGS_DE_HIGH,
1899 static const struct panel_desc kyo_tcg121xglp = {
1900 .timings = &kyo_tcg121xglp_timing,
1907 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1908 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1911 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1914 .hsync_start = 320 + 20,
1915 .hsync_end = 320 + 20 + 30,
1916 .htotal = 320 + 20 + 30 + 38,
1918 .vsync_start = 240 + 4,
1919 .vsync_end = 240 + 4 + 3,
1920 .vtotal = 240 + 4 + 3 + 15,
1924 static const struct panel_desc lemaker_bl035_rgb_002 = {
1925 .modes = &lemaker_bl035_rgb_002_mode,
1931 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1932 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1935 static const struct drm_display_mode lg_lb070wv8_mode = {
1938 .hsync_start = 800 + 88,
1939 .hsync_end = 800 + 88 + 80,
1940 .htotal = 800 + 88 + 80 + 88,
1942 .vsync_start = 480 + 10,
1943 .vsync_end = 480 + 10 + 25,
1944 .vtotal = 480 + 10 + 25 + 10,
1948 static const struct panel_desc lg_lb070wv8 = {
1949 .modes = &lg_lb070wv8_mode,
1956 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1957 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1960 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1963 .hsync_start = 1536 + 12,
1964 .hsync_end = 1536 + 12 + 16,
1965 .htotal = 1536 + 12 + 16 + 48,
1967 .vsync_start = 2048 + 8,
1968 .vsync_end = 2048 + 8 + 4,
1969 .vtotal = 2048 + 8 + 4 + 8,
1971 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1974 static const struct panel_desc lg_lp079qx1_sp0v = {
1975 .modes = &lg_lp079qx1_sp0v_mode,
1983 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1986 .hsync_start = 2048 + 150,
1987 .hsync_end = 2048 + 150 + 5,
1988 .htotal = 2048 + 150 + 5 + 5,
1990 .vsync_start = 1536 + 3,
1991 .vsync_end = 1536 + 3 + 1,
1992 .vtotal = 1536 + 3 + 1 + 9,
1996 static const struct panel_desc lg_lp097qx1_spa1 = {
1997 .modes = &lg_lp097qx1_spa1_mode,
2005 static const struct drm_display_mode lg_lp120up1_mode = {
2008 .hsync_start = 1920 + 40,
2009 .hsync_end = 1920 + 40 + 40,
2010 .htotal = 1920 + 40 + 40+ 80,
2012 .vsync_start = 1280 + 4,
2013 .vsync_end = 1280 + 4 + 4,
2014 .vtotal = 1280 + 4 + 4 + 12,
2018 static const struct panel_desc lg_lp120up1 = {
2019 .modes = &lg_lp120up1_mode,
2028 static const struct drm_display_mode lg_lp129qe_mode = {
2031 .hsync_start = 2560 + 48,
2032 .hsync_end = 2560 + 48 + 32,
2033 .htotal = 2560 + 48 + 32 + 80,
2035 .vsync_start = 1700 + 3,
2036 .vsync_end = 1700 + 3 + 10,
2037 .vtotal = 1700 + 3 + 10 + 36,
2041 static const struct panel_desc lg_lp129qe = {
2042 .modes = &lg_lp129qe_mode,
2051 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2054 .hsync_start = 800 + 0,
2055 .hsync_end = 800 + 1,
2056 .htotal = 800 + 0 + 1 + 160,
2058 .vsync_start = 480 + 0,
2059 .vsync_end = 480 + 48 + 1,
2060 .vtotal = 480 + 48 + 1 + 0,
2062 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2065 static const struct drm_display_mode logicpd_type_28_mode = {
2068 .hsync_start = 480 + 3,
2069 .hsync_end = 480 + 3 + 42,
2070 .htotal = 480 + 3 + 42 + 2,
2073 .vsync_start = 272 + 2,
2074 .vsync_end = 272 + 2 + 11,
2075 .vtotal = 272 + 2 + 11 + 3,
2077 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2080 static const struct panel_desc logicpd_type_28 = {
2081 .modes = &logicpd_type_28_mode,
2094 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2096 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2099 static const struct panel_desc mitsubishi_aa070mc01 = {
2100 .modes = &mitsubishi_aa070mc01_mode,
2113 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2114 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2115 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2118 static const struct display_timing nec_nl12880bc20_05_timing = {
2119 .pixelclock = { 67000000, 71000000, 75000000 },
2120 .hactive = { 1280, 1280, 1280 },
2121 .hfront_porch = { 2, 30, 30 },
2122 .hback_porch = { 6, 100, 100 },
2123 .hsync_len = { 2, 30, 30 },
2124 .vactive = { 800, 800, 800 },
2125 .vfront_porch = { 5, 5, 5 },
2126 .vback_porch = { 11, 11, 11 },
2127 .vsync_len = { 7, 7, 7 },
2130 static const struct panel_desc nec_nl12880bc20_05 = {
2131 .timings = &nec_nl12880bc20_05_timing,
2142 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2143 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2146 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2149 .hsync_start = 480 + 2,
2150 .hsync_end = 480 + 2 + 41,
2151 .htotal = 480 + 2 + 41 + 2,
2153 .vsync_start = 272 + 2,
2154 .vsync_end = 272 + 2 + 4,
2155 .vtotal = 272 + 2 + 4 + 2,
2157 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2160 static const struct panel_desc nec_nl4827hc19_05b = {
2161 .modes = &nec_nl4827hc19_05b_mode,
2168 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2169 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2172 static const struct drm_display_mode netron_dy_e231732_mode = {
2175 .hsync_start = 1024 + 160,
2176 .hsync_end = 1024 + 160 + 70,
2177 .htotal = 1024 + 160 + 70 + 90,
2179 .vsync_start = 600 + 127,
2180 .vsync_end = 600 + 127 + 20,
2181 .vtotal = 600 + 127 + 20 + 3,
2185 static const struct panel_desc netron_dy_e231732 = {
2186 .modes = &netron_dy_e231732_mode,
2192 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2195 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2198 .hsync_start = 480 + 2,
2199 .hsync_end = 480 + 2 + 41,
2200 .htotal = 480 + 2 + 41 + 2,
2202 .vsync_start = 272 + 2,
2203 .vsync_end = 272 + 2 + 10,
2204 .vtotal = 272 + 2 + 10 + 2,
2206 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2209 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2210 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2217 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2218 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2219 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2222 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2223 .pixelclock = { 130000000, 148350000, 163000000 },
2224 .hactive = { 1920, 1920, 1920 },
2225 .hfront_porch = { 80, 100, 100 },
2226 .hback_porch = { 100, 120, 120 },
2227 .hsync_len = { 50, 60, 60 },
2228 .vactive = { 1080, 1080, 1080 },
2229 .vfront_porch = { 12, 30, 30 },
2230 .vback_porch = { 4, 10, 10 },
2231 .vsync_len = { 4, 5, 5 },
2234 static const struct panel_desc nlt_nl192108ac18_02d = {
2235 .timings = &nlt_nl192108ac18_02d_timing,
2245 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2246 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2249 static const struct drm_display_mode nvd_9128_mode = {
2252 .hsync_start = 800 + 130,
2253 .hsync_end = 800 + 130 + 98,
2254 .htotal = 800 + 0 + 130 + 98,
2256 .vsync_start = 480 + 10,
2257 .vsync_end = 480 + 10 + 50,
2258 .vtotal = 480 + 0 + 10 + 50,
2261 static const struct panel_desc nvd_9128 = {
2262 .modes = &nvd_9128_mode,
2269 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2270 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2273 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2274 .pixelclock = { 30000000, 30000000, 40000000 },
2275 .hactive = { 800, 800, 800 },
2276 .hfront_porch = { 40, 40, 40 },
2277 .hback_porch = { 40, 40, 40 },
2278 .hsync_len = { 1, 48, 48 },
2279 .vactive = { 480, 480, 480 },
2280 .vfront_porch = { 13, 13, 13 },
2281 .vback_porch = { 29, 29, 29 },
2282 .vsync_len = { 3, 3, 3 },
2283 .flags = DISPLAY_FLAGS_DE_HIGH,
2286 static const struct panel_desc okaya_rs800480t_7x0gp = {
2287 .timings = &okaya_rs800480t_7x0gp_timing,
2300 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2303 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2306 .hsync_start = 480 + 5,
2307 .hsync_end = 480 + 5 + 30,
2308 .htotal = 480 + 5 + 30 + 10,
2310 .vsync_start = 272 + 8,
2311 .vsync_end = 272 + 8 + 5,
2312 .vtotal = 272 + 8 + 5 + 3,
2316 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2317 .modes = &olimex_lcd_olinuxino_43ts_mode,
2323 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2327 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2328 * pixel clocks, but this is the timing that was being used in the Adafruit
2329 * installation instructions.
2331 static const struct drm_display_mode ontat_yx700wv03_mode = {
2342 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2347 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2349 static const struct panel_desc ontat_yx700wv03 = {
2350 .modes = &ontat_yx700wv03_mode,
2357 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2360 static const struct drm_display_mode ortustech_com37h3m_mode = {
2363 .hsync_start = 480 + 8,
2364 .hsync_end = 480 + 8 + 10,
2365 .htotal = 480 + 8 + 10 + 10,
2367 .vsync_start = 640 + 4,
2368 .vsync_end = 640 + 4 + 3,
2369 .vtotal = 640 + 4 + 3 + 4,
2371 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2374 static const struct panel_desc ortustech_com37h3m = {
2375 .modes = &ortustech_com37h3m_mode,
2379 .width = 56, /* 56.16mm */
2380 .height = 75, /* 74.88mm */
2382 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2383 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2384 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2387 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2390 .hsync_start = 480 + 10,
2391 .hsync_end = 480 + 10 + 10,
2392 .htotal = 480 + 10 + 10 + 15,
2394 .vsync_start = 800 + 3,
2395 .vsync_end = 800 + 3 + 3,
2396 .vtotal = 800 + 3 + 3 + 3,
2400 static const struct panel_desc ortustech_com43h4m85ulc = {
2401 .modes = &ortustech_com43h4m85ulc_mode,
2408 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2409 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2412 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2415 .hsync_start = 800 + 210,
2416 .hsync_end = 800 + 210 + 30,
2417 .htotal = 800 + 210 + 30 + 16,
2419 .vsync_start = 480 + 22,
2420 .vsync_end = 480 + 22 + 13,
2421 .vtotal = 480 + 22 + 13 + 10,
2423 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2426 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2427 .modes = &osddisplays_osd070t1718_19ts_mode,
2434 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2435 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2436 .connector_type = DRM_MODE_CONNECTOR_DPI,
2439 static const struct drm_display_mode pda_91_00156_a0_mode = {
2442 .hsync_start = 800 + 1,
2443 .hsync_end = 800 + 1 + 64,
2444 .htotal = 800 + 1 + 64 + 64,
2446 .vsync_start = 480 + 1,
2447 .vsync_end = 480 + 1 + 23,
2448 .vtotal = 480 + 1 + 23 + 22,
2452 static const struct panel_desc pda_91_00156_a0 = {
2453 .modes = &pda_91_00156_a0_mode,
2459 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2463 static const struct drm_display_mode qd43003c0_40_mode = {
2466 .hsync_start = 480 + 8,
2467 .hsync_end = 480 + 8 + 4,
2468 .htotal = 480 + 8 + 4 + 39,
2470 .vsync_start = 272 + 4,
2471 .vsync_end = 272 + 4 + 10,
2472 .vtotal = 272 + 4 + 10 + 2,
2476 static const struct panel_desc qd43003c0_40 = {
2477 .modes = &qd43003c0_40_mode,
2484 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2487 static const struct display_timing rocktech_rk070er9427_timing = {
2488 .pixelclock = { 26400000, 33300000, 46800000 },
2489 .hactive = { 800, 800, 800 },
2490 .hfront_porch = { 16, 210, 354 },
2491 .hback_porch = { 46, 46, 46 },
2492 .hsync_len = { 1, 1, 1 },
2493 .vactive = { 480, 480, 480 },
2494 .vfront_porch = { 7, 22, 147 },
2495 .vback_porch = { 23, 23, 23 },
2496 .vsync_len = { 1, 1, 1 },
2497 .flags = DISPLAY_FLAGS_DE_HIGH,
2500 static const struct panel_desc rocktech_rk070er9427 = {
2501 .timings = &rocktech_rk070er9427_timing,
2514 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2517 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2520 .hsync_start = 2560 + 48,
2521 .hsync_end = 2560 + 48 + 32,
2522 .htotal = 2560 + 48 + 32 + 80,
2524 .vsync_start = 1600 + 2,
2525 .vsync_end = 1600 + 2 + 5,
2526 .vtotal = 1600 + 2 + 5 + 57,
2530 static const struct panel_desc samsung_lsn122dl01_c01 = {
2531 .modes = &samsung_lsn122dl01_c01_mode,
2539 static const struct drm_display_mode samsung_ltn101nt05_mode = {
2542 .hsync_start = 1024 + 24,
2543 .hsync_end = 1024 + 24 + 136,
2544 .htotal = 1024 + 24 + 136 + 160,
2546 .vsync_start = 600 + 3,
2547 .vsync_end = 600 + 3 + 6,
2548 .vtotal = 600 + 3 + 6 + 61,
2552 static const struct panel_desc samsung_ltn101nt05 = {
2553 .modes = &samsung_ltn101nt05_mode,
2562 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2565 .hsync_start = 1366 + 64,
2566 .hsync_end = 1366 + 64 + 48,
2567 .htotal = 1366 + 64 + 48 + 128,
2569 .vsync_start = 768 + 2,
2570 .vsync_end = 768 + 2 + 5,
2571 .vtotal = 768 + 2 + 5 + 17,
2575 static const struct panel_desc samsung_ltn140at29_301 = {
2576 .modes = &samsung_ltn140at29_301_mode,
2585 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2588 .hsync_start = 1920 + 48,
2589 .hsync_end = 1920 + 48 + 32,
2590 .htotal = 1920 + 48 + 32 + 80,
2592 .vsync_start = 1280 + 3,
2593 .vsync_end = 1280 + 3 + 10,
2594 .vtotal = 1280 + 3 + 10 + 57,
2596 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2599 static const struct panel_desc sharp_ld_d5116z01b = {
2600 .modes = &sharp_ld_d5116z01b_mode,
2607 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2608 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2611 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2614 .hsync_start = 800 + 64,
2615 .hsync_end = 800 + 64 + 128,
2616 .htotal = 800 + 64 + 128 + 64,
2618 .vsync_start = 480 + 8,
2619 .vsync_end = 480 + 8 + 2,
2620 .vtotal = 480 + 8 + 2 + 35,
2622 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2625 static const struct panel_desc sharp_lq070y3dg3b = {
2626 .modes = &sharp_lq070y3dg3b_mode,
2630 .width = 152, /* 152.4mm */
2631 .height = 91, /* 91.4mm */
2633 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2634 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2635 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2638 static const struct drm_display_mode sharp_lq035q7db03_mode = {
2641 .hsync_start = 240 + 16,
2642 .hsync_end = 240 + 16 + 7,
2643 .htotal = 240 + 16 + 7 + 5,
2645 .vsync_start = 320 + 9,
2646 .vsync_end = 320 + 9 + 1,
2647 .vtotal = 320 + 9 + 1 + 7,
2651 static const struct panel_desc sharp_lq035q7db03 = {
2652 .modes = &sharp_lq035q7db03_mode,
2659 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2662 static const struct display_timing sharp_lq101k1ly04_timing = {
2663 .pixelclock = { 60000000, 65000000, 80000000 },
2664 .hactive = { 1280, 1280, 1280 },
2665 .hfront_porch = { 20, 20, 20 },
2666 .hback_porch = { 20, 20, 20 },
2667 .hsync_len = { 10, 10, 10 },
2668 .vactive = { 800, 800, 800 },
2669 .vfront_porch = { 4, 4, 4 },
2670 .vback_porch = { 4, 4, 4 },
2671 .vsync_len = { 4, 4, 4 },
2672 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2675 static const struct panel_desc sharp_lq101k1ly04 = {
2676 .timings = &sharp_lq101k1ly04_timing,
2683 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2684 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2687 static const struct display_timing sharp_lq123p1jx31_timing = {
2688 .pixelclock = { 252750000, 252750000, 266604720 },
2689 .hactive = { 2400, 2400, 2400 },
2690 .hfront_porch = { 48, 48, 48 },
2691 .hback_porch = { 80, 80, 84 },
2692 .hsync_len = { 32, 32, 32 },
2693 .vactive = { 1600, 1600, 1600 },
2694 .vfront_porch = { 3, 3, 3 },
2695 .vback_porch = { 33, 33, 120 },
2696 .vsync_len = { 10, 10, 10 },
2697 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2700 static const struct panel_desc sharp_lq123p1jx31 = {
2701 .timings = &sharp_lq123p1jx31_timing,
2715 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2718 .hsync_start = 1024 + 168,
2719 .hsync_end = 1024 + 168 + 64,
2720 .htotal = 1024 + 168 + 64 + 88,
2722 .vsync_start = 768 + 37,
2723 .vsync_end = 768 + 37 + 2,
2724 .vtotal = 768 + 37 + 2 + 8,
2728 static const struct panel_desc sharp_lq150x1lg11 = {
2729 .modes = &sharp_lq150x1lg11_mode,
2736 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2739 static const struct display_timing sharp_ls020b1dd01d_timing = {
2740 .pixelclock = { 2000000, 4200000, 5000000 },
2741 .hactive = { 240, 240, 240 },
2742 .hfront_porch = { 66, 66, 66 },
2743 .hback_porch = { 1, 1, 1 },
2744 .hsync_len = { 1, 1, 1 },
2745 .vactive = { 160, 160, 160 },
2746 .vfront_porch = { 52, 52, 52 },
2747 .vback_porch = { 6, 6, 6 },
2748 .vsync_len = { 10, 10, 10 },
2749 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2752 static const struct panel_desc sharp_ls020b1dd01d = {
2753 .timings = &sharp_ls020b1dd01d_timing,
2760 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2761 .bus_flags = DRM_BUS_FLAG_DE_HIGH
2762 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2763 | DRM_BUS_FLAG_SHARP_SIGNALS,
2766 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2769 .hsync_start = 800 + 1,
2770 .hsync_end = 800 + 1 + 64,
2771 .htotal = 800 + 1 + 64 + 64,
2773 .vsync_start = 480 + 1,
2774 .vsync_end = 480 + 1 + 23,
2775 .vtotal = 480 + 1 + 23 + 22,
2779 static const struct panel_desc shelly_sca07010_bfn_lnn = {
2780 .modes = &shelly_sca07010_bfn_lnn_mode,
2786 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2789 static const struct drm_display_mode starry_kr122ea0sra_mode = {
2792 .hsync_start = 1920 + 16,
2793 .hsync_end = 1920 + 16 + 16,
2794 .htotal = 1920 + 16 + 16 + 32,
2796 .vsync_start = 1200 + 15,
2797 .vsync_end = 1200 + 15 + 2,
2798 .vtotal = 1200 + 15 + 2 + 18,
2800 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2803 static const struct panel_desc starry_kr122ea0sra = {
2804 .modes = &starry_kr122ea0sra_mode,
2811 .prepare = 10 + 200,
2813 .unprepare = 10 + 500,
2817 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2820 .hsync_start = 800 + 39,
2821 .hsync_end = 800 + 39 + 47,
2822 .htotal = 800 + 39 + 47 + 39,
2824 .vsync_start = 480 + 13,
2825 .vsync_end = 480 + 13 + 2,
2826 .vtotal = 480 + 13 + 2 + 29,
2830 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2831 .modes = &tfc_s9700rtwv43tr_01b_mode,
2838 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2839 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2842 static const struct display_timing tianma_tm070jdhg30_timing = {
2843 .pixelclock = { 62600000, 68200000, 78100000 },
2844 .hactive = { 1280, 1280, 1280 },
2845 .hfront_porch = { 15, 64, 159 },
2846 .hback_porch = { 5, 5, 5 },
2847 .hsync_len = { 1, 1, 256 },
2848 .vactive = { 800, 800, 800 },
2849 .vfront_porch = { 3, 40, 99 },
2850 .vback_porch = { 2, 2, 2 },
2851 .vsync_len = { 1, 1, 128 },
2852 .flags = DISPLAY_FLAGS_DE_HIGH,
2855 static const struct panel_desc tianma_tm070jdhg30 = {
2856 .timings = &tianma_tm070jdhg30_timing,
2863 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2864 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2867 static const struct display_timing tianma_tm070rvhg71_timing = {
2868 .pixelclock = { 27700000, 29200000, 39600000 },
2869 .hactive = { 800, 800, 800 },
2870 .hfront_porch = { 12, 40, 212 },
2871 .hback_porch = { 88, 88, 88 },
2872 .hsync_len = { 1, 1, 40 },
2873 .vactive = { 480, 480, 480 },
2874 .vfront_porch = { 1, 13, 88 },
2875 .vback_porch = { 32, 32, 32 },
2876 .vsync_len = { 1, 1, 3 },
2877 .flags = DISPLAY_FLAGS_DE_HIGH,
2880 static const struct panel_desc tianma_tm070rvhg71 = {
2881 .timings = &tianma_tm070rvhg71_timing,
2888 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2889 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2892 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2896 .hsync_start = 320 + 50,
2897 .hsync_end = 320 + 50 + 6,
2898 .htotal = 320 + 50 + 6 + 38,
2900 .vsync_start = 240 + 3,
2901 .vsync_end = 240 + 3 + 1,
2902 .vtotal = 240 + 3 + 1 + 17,
2904 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2908 static const struct panel_desc ti_nspire_cx_lcd_panel = {
2909 .modes = ti_nspire_cx_lcd_mode,
2916 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2917 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2920 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2924 .hsync_start = 320 + 6,
2925 .hsync_end = 320 + 6 + 6,
2926 .htotal = 320 + 6 + 6 + 6,
2928 .vsync_start = 240 + 0,
2929 .vsync_end = 240 + 0 + 1,
2930 .vtotal = 240 + 0 + 1 + 0,
2932 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2936 static const struct panel_desc ti_nspire_classic_lcd_panel = {
2937 .modes = ti_nspire_classic_lcd_mode,
2939 /* The grayscale panel has 8 bit for the color .. Y (black) */
2945 /* This is the grayscale bus format */
2946 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
2947 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2950 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2953 .hsync_start = 1280 + 192,
2954 .hsync_end = 1280 + 192 + 128,
2955 .htotal = 1280 + 192 + 128 + 64,
2957 .vsync_start = 768 + 20,
2958 .vsync_end = 768 + 20 + 7,
2959 .vtotal = 768 + 20 + 7 + 3,
2963 static const struct panel_desc toshiba_lt089ac29000 = {
2964 .modes = &toshiba_lt089ac29000_mode,
2970 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2971 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2972 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2975 static const struct drm_display_mode tpk_f07a_0102_mode = {
2978 .hsync_start = 800 + 40,
2979 .hsync_end = 800 + 40 + 128,
2980 .htotal = 800 + 40 + 128 + 88,
2982 .vsync_start = 480 + 10,
2983 .vsync_end = 480 + 10 + 2,
2984 .vtotal = 480 + 10 + 2 + 33,
2988 static const struct panel_desc tpk_f07a_0102 = {
2989 .modes = &tpk_f07a_0102_mode,
2995 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2998 static const struct drm_display_mode tpk_f10a_0102_mode = {
3001 .hsync_start = 1024 + 176,
3002 .hsync_end = 1024 + 176 + 5,
3003 .htotal = 1024 + 176 + 5 + 88,
3005 .vsync_start = 600 + 20,
3006 .vsync_end = 600 + 20 + 5,
3007 .vtotal = 600 + 20 + 5 + 25,
3011 static const struct panel_desc tpk_f10a_0102 = {
3012 .modes = &tpk_f10a_0102_mode,
3020 static const struct display_timing urt_umsh_8596md_timing = {
3021 .pixelclock = { 33260000, 33260000, 33260000 },
3022 .hactive = { 800, 800, 800 },
3023 .hfront_porch = { 41, 41, 41 },
3024 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3025 .hsync_len = { 71, 128, 128 },
3026 .vactive = { 480, 480, 480 },
3027 .vfront_porch = { 10, 10, 10 },
3028 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3029 .vsync_len = { 2, 2, 2 },
3030 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3031 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3034 static const struct panel_desc urt_umsh_8596md_lvds = {
3035 .timings = &urt_umsh_8596md_timing,
3042 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3043 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3046 static const struct panel_desc urt_umsh_8596md_parallel = {
3047 .timings = &urt_umsh_8596md_timing,
3054 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3057 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3060 .hsync_start = 800 + 210,
3061 .hsync_end = 800 + 210 + 20,
3062 .htotal = 800 + 210 + 20 + 46,
3064 .vsync_start = 480 + 22,
3065 .vsync_end = 480 + 22 + 10,
3066 .vtotal = 480 + 22 + 10 + 23,
3068 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3071 static const struct panel_desc vl050_8048nt_c01 = {
3072 .modes = &vl050_8048nt_c01_mode,
3079 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3080 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3083 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3086 .hsync_start = 320 + 20,
3087 .hsync_end = 320 + 20 + 30,
3088 .htotal = 320 + 20 + 30 + 38,
3090 .vsync_start = 240 + 4,
3091 .vsync_end = 240 + 4 + 3,
3092 .vtotal = 240 + 4 + 3 + 15,
3094 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3097 static const struct panel_desc winstar_wf35ltiacd = {
3098 .modes = &winstar_wf35ltiacd_mode,
3105 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3108 static const struct drm_display_mode arm_rtsm_mode[] = {
3112 .hsync_start = 1024 + 24,
3113 .hsync_end = 1024 + 24 + 136,
3114 .htotal = 1024 + 24 + 136 + 160,
3116 .vsync_start = 768 + 3,
3117 .vsync_end = 768 + 3 + 6,
3118 .vtotal = 768 + 3 + 6 + 29,
3120 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3124 static const struct panel_desc arm_rtsm = {
3125 .modes = arm_rtsm_mode,
3132 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3135 static const struct of_device_id platform_of_match[] = {
3137 .compatible = "ampire,am-480272h3tmqw-t01h",
3138 .data = &ire_am_480272h3tmqw_t01h,
3140 .compatible = "ampire,am800480r3tmqwa1h",
3141 .data = &ire_am800480r3tmqwa1h,
3143 .compatible = "arm,rtsm-display",
3146 .compatible = "armadeus,st0700-adapt",
3147 .data = &armadeus_st0700_adapt,
3149 .compatible = "auo,b101aw03",
3150 .data = &auo_b101aw03,
3152 .compatible = "auo,b101ean01",
3153 .data = &auo_b101ean01,
3155 .compatible = "auo,b101xtn01",
3156 .data = &auo_b101xtn01,
3158 .compatible = "auo,b116xa01",
3159 .data = &auo_b116xak01,
3161 .compatible = "auo,b116xw03",
3162 .data = &auo_b116xw03,
3164 .compatible = "auo,b133htn01",
3165 .data = &auo_b133htn01,
3167 .compatible = "auo,b133xtn01",
3168 .data = &auo_b133xtn01,
3170 .compatible = "auo,g070vvn01",
3171 .data = &auo_g070vvn01,
3173 .compatible = "auo,g101evn010",
3174 .data = &auo_g101evn010,
3176 .compatible = "auo,g104sn02",
3177 .data = &auo_g104sn02,
3179 .compatible = "auo,g133han01",
3180 .data = &auo_g133han01,
3182 .compatible = "auo,g185han01",
3183 .data = &auo_g185han01,
3185 .compatible = "auo,p320hvn03",
3186 .data = &auo_p320hvn03,
3188 .compatible = "auo,t215hvn01",
3189 .data = &auo_t215hvn01,
3191 .compatible = "avic,tm070ddh03",
3192 .data = &avic_tm070ddh03,
3194 .compatible = "bananapi,s070wv20-ct16",
3195 .data = &bananapi_s070wv20_ct16,
3197 .compatible = "boe,hv070wsa-100",
3198 .data = &boe_hv070wsa
3200 .compatible = "boe,nv101wxmn51",
3201 .data = &boe_nv101wxmn51,
3203 .compatible = "cdtech,s043wq26h-ct7",
3204 .data = &cdtech_s043wq26h_ct7,
3206 .compatible = "cdtech,s070wv95-ct16",
3207 .data = &cdtech_s070wv95_ct16,
3209 .compatible = "chunghwa,claa070wp03xg",
3210 .data = &chunghwa_claa070wp03xg,
3212 .compatible = "chunghwa,claa101wa01a",
3213 .data = &chunghwa_claa101wa01a
3215 .compatible = "chunghwa,claa101wb01",
3216 .data = &chunghwa_claa101wb01
3218 .compatible = "dataimage,scf0700c48ggu18",
3219 .data = &dataimage_scf0700c48ggu18,
3221 .compatible = "dlc,dlc0700yzg-1",
3222 .data = &dlc_dlc0700yzg_1,
3224 .compatible = "dlc,dlc1010gig",
3225 .data = &dlc_dlc1010gig,
3227 .compatible = "edt,et035012dm6",
3228 .data = &edt_et035012dm6,
3230 .compatible = "edt,etm0430g0dh6",
3231 .data = &edt_etm0430g0dh6,
3233 .compatible = "edt,et057090dhu",
3234 .data = &edt_et057090dhu,
3236 .compatible = "edt,et070080dh6",
3237 .data = &edt_etm0700g0dh6,
3239 .compatible = "edt,etm0700g0dh6",
3240 .data = &edt_etm0700g0dh6,
3242 .compatible = "edt,etm0700g0bdh6",
3243 .data = &edt_etm0700g0bdh6,
3245 .compatible = "edt,etm0700g0edh6",
3246 .data = &edt_etm0700g0bdh6,
3248 .compatible = "evervision,vgg804821",
3249 .data = &evervision_vgg804821,
3251 .compatible = "foxlink,fl500wvr00-a0t",
3252 .data = &foxlink_fl500wvr00_a0t,
3254 .compatible = "friendlyarm,hd702e",
3255 .data = &friendlyarm_hd702e,
3257 .compatible = "giantplus,gpg482739qs5",
3258 .data = &giantplus_gpg482739qs5
3260 .compatible = "giantplus,gpm940b0",
3261 .data = &giantplus_gpm940b0,
3263 .compatible = "hannstar,hsd070pww1",
3264 .data = &hannstar_hsd070pww1,
3266 .compatible = "hannstar,hsd100pxn1",
3267 .data = &hannstar_hsd100pxn1,
3269 .compatible = "hit,tx23d38vm0caa",
3270 .data = &hitachi_tx23d38vm0caa
3272 .compatible = "innolux,at043tn24",
3273 .data = &innolux_at043tn24,
3275 .compatible = "innolux,at070tn92",
3276 .data = &innolux_at070tn92,
3278 .compatible = "innolux,g070y2-l01",
3279 .data = &innolux_g070y2_l01,
3281 .compatible = "innolux,g101ice-l01",
3282 .data = &innolux_g101ice_l01
3284 .compatible = "innolux,g121i1-l01",
3285 .data = &innolux_g121i1_l01
3287 .compatible = "innolux,g121x1-l03",
3288 .data = &innolux_g121x1_l03,
3290 .compatible = "innolux,n116bge",
3291 .data = &innolux_n116bge,
3293 .compatible = "innolux,n156bge-l21",
3294 .data = &innolux_n156bge_l21,
3296 .compatible = "innolux,p120zdg-bf1",
3297 .data = &innolux_p120zdg_bf1,
3299 .compatible = "innolux,zj070na-01p",
3300 .data = &innolux_zj070na_01p,
3302 .compatible = "koe,tx14d24vm1bpa",
3303 .data = &koe_tx14d24vm1bpa,
3305 .compatible = "koe,tx31d200vm0baa",
3306 .data = &koe_tx31d200vm0baa,
3308 .compatible = "kyo,tcg121xglp",
3309 .data = &kyo_tcg121xglp,
3311 .compatible = "lemaker,bl035-rgb-002",
3312 .data = &lemaker_bl035_rgb_002,
3314 .compatible = "lg,lb070wv8",
3315 .data = &lg_lb070wv8,
3317 .compatible = "lg,lp079qx1-sp0v",
3318 .data = &lg_lp079qx1_sp0v,
3320 .compatible = "lg,lp097qx1-spa1",
3321 .data = &lg_lp097qx1_spa1,
3323 .compatible = "lg,lp120up1",
3324 .data = &lg_lp120up1,
3326 .compatible = "lg,lp129qe",
3327 .data = &lg_lp129qe,
3329 .compatible = "logicpd,type28",
3330 .data = &logicpd_type_28,
3332 .compatible = "mitsubishi,aa070mc01-ca1",
3333 .data = &mitsubishi_aa070mc01,
3335 .compatible = "nec,nl12880bc20-05",
3336 .data = &nec_nl12880bc20_05,
3338 .compatible = "nec,nl4827hc19-05b",
3339 .data = &nec_nl4827hc19_05b,
3341 .compatible = "netron-dy,e231732",
3342 .data = &netron_dy_e231732,
3344 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3345 .data = &newhaven_nhd_43_480272ef_atxl,
3347 .compatible = "nlt,nl192108ac18-02d",
3348 .data = &nlt_nl192108ac18_02d,
3350 .compatible = "nvd,9128",
3353 .compatible = "okaya,rs800480t-7x0gp",
3354 .data = &okaya_rs800480t_7x0gp,
3356 .compatible = "olimex,lcd-olinuxino-43-ts",
3357 .data = &olimex_lcd_olinuxino_43ts,
3359 .compatible = "ontat,yx700wv03",
3360 .data = &ontat_yx700wv03,
3362 .compatible = "ortustech,com37h3m05dtc",
3363 .data = &ortustech_com37h3m,
3365 .compatible = "ortustech,com37h3m99dtc",
3366 .data = &ortustech_com37h3m,
3368 .compatible = "ortustech,com43h4m85ulc",
3369 .data = &ortustech_com43h4m85ulc,
3371 .compatible = "osddisplays,osd070t1718-19ts",
3372 .data = &osddisplays_osd070t1718_19ts,
3374 .compatible = "pda,91-00156-a0",
3375 .data = &pda_91_00156_a0,
3377 .compatible = "qiaodian,qd43003c0-40",
3378 .data = &qd43003c0_40,
3380 .compatible = "rocktech,rk070er9427",
3381 .data = &rocktech_rk070er9427,
3383 .compatible = "samsung,lsn122dl01-c01",
3384 .data = &samsung_lsn122dl01_c01,
3386 .compatible = "samsung,ltn101nt05",
3387 .data = &samsung_ltn101nt05,
3389 .compatible = "samsung,ltn140at29-301",
3390 .data = &samsung_ltn140at29_301,
3392 .compatible = "sharp,ld-d5116z01b",
3393 .data = &sharp_ld_d5116z01b,
3395 .compatible = "sharp,lq035q7db03",
3396 .data = &sharp_lq035q7db03,
3398 .compatible = "sharp,lq070y3dg3b",
3399 .data = &sharp_lq070y3dg3b,
3401 .compatible = "sharp,lq101k1ly04",
3402 .data = &sharp_lq101k1ly04,
3404 .compatible = "sharp,lq123p1jx31",
3405 .data = &sharp_lq123p1jx31,
3407 .compatible = "sharp,lq150x1lg11",
3408 .data = &sharp_lq150x1lg11,
3410 .compatible = "sharp,ls020b1dd01d",
3411 .data = &sharp_ls020b1dd01d,
3413 .compatible = "shelly,sca07010-bfn-lnn",
3414 .data = &shelly_sca07010_bfn_lnn,
3416 .compatible = "starry,kr122ea0sra",
3417 .data = &starry_kr122ea0sra,
3419 .compatible = "tfc,s9700rtwv43tr-01b",
3420 .data = &tfc_s9700rtwv43tr_01b,
3422 .compatible = "tianma,tm070jdhg30",
3423 .data = &tianma_tm070jdhg30,
3425 .compatible = "tianma,tm070rvhg71",
3426 .data = &tianma_tm070rvhg71,
3428 .compatible = "ti,nspire-cx-lcd-panel",
3429 .data = &ti_nspire_cx_lcd_panel,
3431 .compatible = "ti,nspire-classic-lcd-panel",
3432 .data = &ti_nspire_classic_lcd_panel,
3434 .compatible = "toshiba,lt089ac29000",
3435 .data = &toshiba_lt089ac29000,
3437 .compatible = "tpk,f07a-0102",
3438 .data = &tpk_f07a_0102,
3440 .compatible = "tpk,f10a-0102",
3441 .data = &tpk_f10a_0102,
3443 .compatible = "urt,umsh-8596md-t",
3444 .data = &urt_umsh_8596md_parallel,
3446 .compatible = "urt,umsh-8596md-1t",
3447 .data = &urt_umsh_8596md_parallel,
3449 .compatible = "urt,umsh-8596md-7t",
3450 .data = &urt_umsh_8596md_parallel,
3452 .compatible = "urt,umsh-8596md-11t",
3453 .data = &urt_umsh_8596md_lvds,
3455 .compatible = "urt,umsh-8596md-19t",
3456 .data = &urt_umsh_8596md_lvds,
3458 .compatible = "urt,umsh-8596md-20t",
3459 .data = &urt_umsh_8596md_parallel,
3461 .compatible = "vxt,vl050-8048nt-c01",
3462 .data = &vl050_8048nt_c01,
3464 .compatible = "winstar,wf35ltiacd",
3465 .data = &winstar_wf35ltiacd,
3470 MODULE_DEVICE_TABLE(of, platform_of_match);
3472 static int panel_simple_platform_probe(struct platform_device *pdev)
3474 const struct of_device_id *id;
3476 id = of_match_node(platform_of_match, pdev->dev.of_node);
3480 return panel_simple_probe(&pdev->dev, id->data);
3483 static int panel_simple_platform_remove(struct platform_device *pdev)
3485 return panel_simple_remove(&pdev->dev);
3488 static void panel_simple_platform_shutdown(struct platform_device *pdev)
3490 panel_simple_shutdown(&pdev->dev);
3493 static struct platform_driver panel_simple_platform_driver = {
3495 .name = "panel-simple",
3496 .of_match_table = platform_of_match,
3498 .probe = panel_simple_platform_probe,
3499 .remove = panel_simple_platform_remove,
3500 .shutdown = panel_simple_platform_shutdown,
3503 struct panel_desc_dsi {
3504 struct panel_desc desc;
3506 unsigned long flags;
3507 enum mipi_dsi_pixel_format format;
3511 static const struct drm_display_mode auo_b080uan01_mode = {
3514 .hsync_start = 1200 + 62,
3515 .hsync_end = 1200 + 62 + 4,
3516 .htotal = 1200 + 62 + 4 + 62,
3518 .vsync_start = 1920 + 9,
3519 .vsync_end = 1920 + 9 + 2,
3520 .vtotal = 1920 + 9 + 2 + 8,
3524 static const struct panel_desc_dsi auo_b080uan01 = {
3526 .modes = &auo_b080uan01_mode,
3534 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3535 .format = MIPI_DSI_FMT_RGB888,
3539 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3542 .hsync_start = 1200 + 120,
3543 .hsync_end = 1200 + 120 + 20,
3544 .htotal = 1200 + 120 + 20 + 21,
3546 .vsync_start = 1920 + 21,
3547 .vsync_end = 1920 + 21 + 3,
3548 .vtotal = 1920 + 21 + 3 + 18,
3550 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3553 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3555 .modes = &boe_tv080wum_nl0_mode,
3562 .flags = MIPI_DSI_MODE_VIDEO |
3563 MIPI_DSI_MODE_VIDEO_BURST |
3564 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3565 .format = MIPI_DSI_FMT_RGB888,
3569 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3572 .hsync_start = 800 + 32,
3573 .hsync_end = 800 + 32 + 1,
3574 .htotal = 800 + 32 + 1 + 57,
3576 .vsync_start = 1280 + 28,
3577 .vsync_end = 1280 + 28 + 1,
3578 .vtotal = 1280 + 28 + 1 + 14,
3582 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3584 .modes = &lg_ld070wx3_sl01_mode,
3592 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3593 .format = MIPI_DSI_FMT_RGB888,
3597 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3600 .hsync_start = 720 + 12,
3601 .hsync_end = 720 + 12 + 4,
3602 .htotal = 720 + 12 + 4 + 112,
3604 .vsync_start = 1280 + 8,
3605 .vsync_end = 1280 + 8 + 4,
3606 .vtotal = 1280 + 8 + 4 + 12,
3610 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3612 .modes = &lg_lh500wx1_sd03_mode,
3620 .flags = MIPI_DSI_MODE_VIDEO,
3621 .format = MIPI_DSI_FMT_RGB888,
3625 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3628 .hsync_start = 1920 + 154,
3629 .hsync_end = 1920 + 154 + 16,
3630 .htotal = 1920 + 154 + 16 + 32,
3632 .vsync_start = 1200 + 17,
3633 .vsync_end = 1200 + 17 + 2,
3634 .vtotal = 1200 + 17 + 2 + 16,
3638 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3640 .modes = &panasonic_vvx10f004b00_mode,
3648 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3649 MIPI_DSI_CLOCK_NON_CONTINUOUS,
3650 .format = MIPI_DSI_FMT_RGB888,
3654 static const struct drm_display_mode lg_acx467akm_7_mode = {
3657 .hsync_start = 1080 + 2,
3658 .hsync_end = 1080 + 2 + 2,
3659 .htotal = 1080 + 2 + 2 + 2,
3661 .vsync_start = 1920 + 2,
3662 .vsync_end = 1920 + 2 + 2,
3663 .vtotal = 1920 + 2 + 2 + 2,
3667 static const struct panel_desc_dsi lg_acx467akm_7 = {
3669 .modes = &lg_acx467akm_7_mode,
3678 .format = MIPI_DSI_FMT_RGB888,
3682 static const struct drm_display_mode osd101t2045_53ts_mode = {
3685 .hsync_start = 1920 + 112,
3686 .hsync_end = 1920 + 112 + 16,
3687 .htotal = 1920 + 112 + 16 + 32,
3689 .vsync_start = 1200 + 16,
3690 .vsync_end = 1200 + 16 + 2,
3691 .vtotal = 1200 + 16 + 2 + 16,
3693 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3696 static const struct panel_desc_dsi osd101t2045_53ts = {
3698 .modes = &osd101t2045_53ts_mode,
3706 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3707 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3708 MIPI_DSI_MODE_EOT_PACKET,
3709 .format = MIPI_DSI_FMT_RGB888,
3713 static const struct of_device_id dsi_of_match[] = {
3715 .compatible = "auo,b080uan01",
3716 .data = &auo_b080uan01
3718 .compatible = "boe,tv080wum-nl0",
3719 .data = &boe_tv080wum_nl0
3721 .compatible = "lg,ld070wx3-sl01",
3722 .data = &lg_ld070wx3_sl01
3724 .compatible = "lg,lh500wx1-sd03",
3725 .data = &lg_lh500wx1_sd03
3727 .compatible = "panasonic,vvx10f004b00",
3728 .data = &panasonic_vvx10f004b00
3730 .compatible = "lg,acx467akm-7",
3731 .data = &lg_acx467akm_7
3733 .compatible = "osddisplays,osd101t2045-53ts",
3734 .data = &osd101t2045_53ts
3739 MODULE_DEVICE_TABLE(of, dsi_of_match);
3741 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3743 const struct panel_desc_dsi *desc;
3744 const struct of_device_id *id;
3747 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3753 err = panel_simple_probe(&dsi->dev, &desc->desc);
3757 dsi->mode_flags = desc->flags;
3758 dsi->format = desc->format;
3759 dsi->lanes = desc->lanes;
3761 err = mipi_dsi_attach(dsi);
3763 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3765 drm_panel_remove(&panel->base);
3771 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3775 err = mipi_dsi_detach(dsi);
3777 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3779 return panel_simple_remove(&dsi->dev);
3782 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3784 panel_simple_shutdown(&dsi->dev);
3787 static struct mipi_dsi_driver panel_simple_dsi_driver = {
3789 .name = "panel-simple-dsi",
3790 .of_match_table = dsi_of_match,
3792 .probe = panel_simple_dsi_probe,
3793 .remove = panel_simple_dsi_remove,
3794 .shutdown = panel_simple_dsi_shutdown,
3797 static int __init panel_simple_init(void)
3801 err = platform_driver_register(&panel_simple_platform_driver);
3805 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3806 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3813 module_init(panel_simple_init);
3815 static void __exit panel_simple_exit(void)
3817 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3818 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3820 platform_driver_unregister(&panel_simple_platform_driver);
3822 module_exit(panel_simple_exit);
3824 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3825 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3826 MODULE_LICENSE("GPL and additional rights");